From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2008B4227B; Fri, 1 Sep 2023 19:10:14 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C691940285; Fri, 1 Sep 2023 19:10:13 +0200 (CEST) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by mails.dpdk.org (Postfix) with ESMTP id 998BC4014F for ; Fri, 1 Sep 2023 19:10:11 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1693588211; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yX5BS34jWKM96tn9OzOUdSB8zicxhHOa/H0MjHZuEqc=; b=UWx40u55bfltPhnkyQsj+m8lvRyeFjD0OdVhb14Lk4TNEYoDfiER4SdsBB4Z3PeF5bmYcI zQsL+f8hc9iD1oQuvO8zJhA4fEelsEDP5/113PnhSUOuaeBt9OvMTkN/p+A1RcdHLM6coO 7PayjCB4hpcILZDEL2wqet1VvDb2ypI= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-335-Dn6zsp-yOf6Lt8jHwFtxow-1; Fri, 01 Sep 2023 13:10:08 -0400 X-MC-Unique: Dn6zsp-yOf6Lt8jHwFtxow-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 95563939182; Fri, 1 Sep 2023 17:10:07 +0000 (UTC) Received: from [10.39.208.19] (unknown [10.39.208.19]) by smtp.corp.redhat.com (Postfix) with ESMTPS id B988449310F; Fri, 1 Sep 2023 17:10:05 +0000 (UTC) Message-ID: Date: Fri, 1 Sep 2023 19:10:04 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH v2 6/6] baseband/fpga_5gnr_fec: cosmetic comment changes To: Hernan Vargas , dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com References: <20230525182812.152907-1-hernan.vargas@intel.com> <20230525182812.152907-7-hernan.vargas@intel.com> From: Maxime Coquelin In-Reply-To: <20230525182812.152907-7-hernan.vargas@intel.com> X-Scanned-By: MIMEDefang 3.1 on 10.11.54.10 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On 5/25/23 20:28, Hernan Vargas wrote: > Cosmetic changes for comments. > No functional impact. > > Signed-off-by: Hernan Vargas > --- > .../baseband/fpga_5gnr_fec/fpga_5gnr_fec.h | 93 ++-- > .../fpga_5gnr_fec/rte_fpga_5gnr_fec.c | 398 +++++++++--------- > .../fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h | 16 +- > 3 files changed, 252 insertions(+), 255 deletions(-) Some of the changes are fixing code introduced earlier in the series. Fix that in these patches directly. > diff --git a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h > index d0d9ee64dbde..c2aa5af2af40 100644 > --- a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h > +++ b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h > @@ -11,7 +11,7 @@ > #include "agx100_pmd.h" > #include "vc_5gnr_pmd.h" > > -/* Helper macro for logging */ > +/* Helper macro for logging. */ > #define rte_bbdev_log(level, fmt, ...) \ > rte_log(RTE_LOG_ ## level, fpga_5gnr_fec_logtype, fmt "\n", \ > ##__VA_ARGS__) > @@ -24,7 +24,7 @@ > #define rte_bbdev_log_debug(fmt, ...) > #endif > > -/* FPGA 5GNR FEC driver names */ > +/* FPGA 5GNR FEC driver names. */ > #define FPGA_5GNR_FEC_PF_DRIVER_NAME intel_fpga_5gnr_fec_pf > #define FPGA_5GNR_FEC_VF_DRIVER_NAME intel_fpga_5gnr_fec_vf > > @@ -43,15 +43,15 @@ > #define VC_5GNR_FPGA_VARIANT 0 > #define AGX100_FPGA_VARIANT 1 > > -/* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2 */ > -#define N_ZC_1 66 /* N = 66 Zc for BG 1 */ > -#define N_ZC_2 50 /* N = 50 Zc for BG 2 */ > -#define K0_1_1 17 /* K0 fraction numerator for rv 1 and BG 1 */ > -#define K0_1_2 13 /* K0 fraction numerator for rv 1 and BG 2 */ > -#define K0_2_1 33 /* K0 fraction numerator for rv 2 and BG 1 */ > -#define K0_2_2 25 /* K0 fraction numerator for rv 2 and BG 2 */ > -#define K0_3_1 56 /* K0 fraction numerator for rv 3 and BG 1 */ > -#define K0_3_2 43 /* K0 fraction numerator for rv 3 and BG 2 */ > +/* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2. */ > +#define N_ZC_1 66 /**< N = 66 Zc for BG 1. */ > +#define N_ZC_2 50 /**< N = 50 Zc for BG 2. */ > +#define K0_1_1 17 /**< K0 fraction numerator for rv 1 and BG 1. */ > +#define K0_1_2 13 /**< K0 fraction numerator for rv 1 and BG 2. */ > +#define K0_2_1 33 /**< K0 fraction numerator for rv 2 and BG 1. */ > +#define K0_2_2 25 /**< K0 fraction numerator for rv 2 and BG 2. */ > +#define K0_3_1 56 /**< K0 fraction numerator for rv 3 and BG 1. */ > +#define K0_3_2 43 /**< K0 fraction numerator for rv 3 and BG 2. */ > > /* FPGA 5GNR Ring Control Registers. */ > enum { > @@ -66,25 +66,25 @@ enum { > > /* VC 5GNR and AGX100 common register mapping on BAR0. */ > enum { > - FPGA_5GNR_FEC_VERSION_ID = 0x00000000, /**< len: 4B */ > - FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE = 0x00000008, /**< len: 1B */ > - FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR = 0x0000000A, /**< len: 2B */ > - FPGA_5GNR_FEC_RING_DESC_LEN = 0x0000000C, /**< len: 2B */ > - FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_LW = 0x00000018, /**< len: 4B */ > - FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_HI = 0x0000001C, /**< len: 4B */ > - FPGA_5GNR_FEC_RING_CTRL_REGS = 0x00000200, /**< len: 2048B */ > - FPGA_5GNR_FEC_DDR4_WR_ADDR_REGS = 0x00000A00, /**< len: 4B */ > - FPGA_5GNR_FEC_DDR4_WR_DATA_REGS = 0x00000A08, /**< len: 8B */ > - FPGA_5GNR_FEC_DDR4_WR_DONE_REGS = 0x00000A10, /**< len: 1B */ > - FPGA_5GNR_FEC_DDR4_RD_ADDR_REGS = 0x00000A18, /**< len: 4B */ > - FPGA_5GNR_FEC_DDR4_RD_DONE_REGS = 0x00000A20, /**< len: 1B */ > - FPGA_5GNR_FEC_DDR4_RD_RDY_REGS = 0x00000A28, /**< len: 1B */ > - FPGA_5GNR_FEC_DDR4_RD_DATA_REGS = 0x00000A30, /**< len: 8B */ > - FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS = 0x00000A38, /**< len: 1B */ > - FPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS = 0x00000A40, /**< len: 1B */ > - FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS = 0x00000A48, /**< len: 4B */ > - FPGA_5GNR_FEC_MUTEX = 0x00000A60, /**< len: 4B */ > - FPGA_5GNR_FEC_MUTEX_RESET = 0x00000A68 /**< len: 4B */ > + FPGA_5GNR_FEC_VERSION_ID = 0x00000000, /**< len: 4B. */ > + FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE = 0x00000008, /**< len: 1B. */ > + FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR = 0x0000000A, /**< len: 2B. */ > + FPGA_5GNR_FEC_RING_DESC_LEN = 0x0000000C, /**< len: 2B. */ > + FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_LW = 0x00000018, /**< len: 4B. */ > + FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_HI = 0x0000001C, /**< len: 4B. */ > + FPGA_5GNR_FEC_RING_CTRL_REGS = 0x00000200, /**< len: 2048B. */ > + FPGA_5GNR_FEC_DDR4_WR_ADDR_REGS = 0x00000A00, /**< len: 4B. */ > + FPGA_5GNR_FEC_DDR4_WR_DATA_REGS = 0x00000A08, /**< len: 8B. */ > + FPGA_5GNR_FEC_DDR4_WR_DONE_REGS = 0x00000A10, /**< len: 1B. */ > + FPGA_5GNR_FEC_DDR4_RD_ADDR_REGS = 0x00000A18, /**< len: 4B. */ > + FPGA_5GNR_FEC_DDR4_RD_DONE_REGS = 0x00000A20, /**< len: 1B. */ > + FPGA_5GNR_FEC_DDR4_RD_RDY_REGS = 0x00000A28, /**< len: 1B. */ > + FPGA_5GNR_FEC_DDR4_RD_DATA_REGS = 0x00000A30, /**< len: 8B. */ > + FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS = 0x00000A38, /**< len: 1B. */ > + FPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS = 0x00000A40, /**< len: 1B. */ > + FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS = 0x00000A48, /**< len: 4B. */ > + FPGA_5GNR_FEC_MUTEX = 0x00000A60, /**< len: 4B. */ > + FPGA_5GNR_FEC_MUTEX_RESET = 0x00000A68 /**< len: 4B. */ > }; > > /* FPGA 5GNR Ring Control Register. */ > @@ -93,7 +93,7 @@ struct __rte_packed fpga_5gnr_ring_ctrl_reg { > uint64_t ring_head_addr; > uint16_t ring_size:11; > uint16_t rsrvd0; > - union { /* Miscellaneous register */ > + union { /* Miscellaneous register. */ > uint8_t misc; > uint8_t max_ul_dec:5, > max_ul_dec_en:1, > @@ -132,30 +132,27 @@ struct fpga_5gnr_fec_device { > uint64_t q_assigned_bit_map; > /** True if this is a PF FPGA 5GNR device. */ > bool pf_device; > - /** Maximum number of possible queues for this device */ > + /** Maximum number of possible queues for this device. */ > uint8_t total_num_queues; > - /** FPGA Variant. VC_5GNR_FPGA_VARIANT = 0; AGX100_FPGA_VARIANT = 1 */ > + /** FPGA Variant. VC_5GNR_FPGA_VARIANT = 0; AGX100_FPGA_VARIANT = 1. */ > uint8_t fpga_variant; > }; > > /** Structure associated with each queue. */ > struct __rte_cache_aligned fpga_5gnr_queue { > - struct fpga_5gnr_ring_ctrl_reg ring_ctrl_reg; /**< Ring Control Register */ > + struct fpga_5gnr_ring_ctrl_reg ring_ctrl_reg; /**< Ring Control Register. */ > union vc_5gnr_dma_desc *vc_5gnr_ring_addr; /**< Virtual address of VC 5GNR software ring. */ > - union agx100_dma_desc *agx100_ring_addr; /**< Virtual address of AGX100 software ring */ > - uint64_t *ring_head_addr; /* Virtual address of completion_head */ > - uint64_t shadow_completion_head; /* Shadow completion head value */ > - uint16_t head_free_desc; /* Ring head */ > - uint16_t tail; /* Ring tail */ > - /* Mask used to wrap enqueued descriptors on the sw ring */ > - uint32_t sw_ring_wrap_mask; > - uint32_t irq_enable; /* Enable ops dequeue interrupts if set to 1 */ > - uint8_t q_idx; /* Queue index */ > - /** uuid used for MUTEX acquision for DDR */ > - uint16_t ddr_mutex_uuid; > - struct fpga_5gnr_fec_device *d; > - /* MMIO register of shadow_tail used to enqueue descriptors */ > - void *shadow_tail_addr; > + union agx100_dma_desc *agx100_ring_addr; /**< Virtual address of AGX100 software ring. */ > + uint64_t *ring_head_addr; /**< Virtual address of completion_head. */ > + uint64_t shadow_completion_head; /**< Shadow completion head value. */ > + uint16_t head_free_desc; /**< Ring head. */ > + uint16_t tail; /**< Ring tail. */ > + uint32_t sw_ring_wrap_mask; /**< Mask used to wrap enqueued descriptors on the sw ring. */ > + uint32_t irq_enable; /**< Enable ops dequeue interrupts if set to 1. */ > + uint8_t q_idx; /**< Queue index. */ > + uint16_t ddr_mutex_uuid; /**< uuid used for MUTEX acquision for DDR. */ > + struct fpga_5gnr_fec_device *d; /**< FPGA 5GNR device structure. */ > + void *shadow_tail_addr; /**< MMIO register of shadow_tail used to enqueue descriptors. */ > }; > > /* Write to 16 bit MMIO register address. */ > diff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c > index 5fb1d6f96d30..ef656895d6eb 100644 > --- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c > +++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c > @@ -29,7 +29,7 @@ RTE_LOG_REGISTER_DEFAULT(fpga_5gnr_fec_logtype, NOTICE); > > #ifdef RTE_LIBRTE_BBDEV_DEBUG > > -/* Read Ring Control Register of FPGA 5GNR FEC device */ > +/* Read Ring Control Register of FPGA 5GNR FEC device. */ > static inline void > print_ring_reg_debug_info(void *mmio_base, uint32_t offset) > { > @@ -149,7 +149,7 @@ vc_5gnr_print_dma_dec_desc_debug_info(union vc_5gnr_dma_desc *desc) > word[4], word[5], word[6], word[7]); > } > > -/* Print decode DMA Descriptor of AGX100 Decoder device */ > +/* Print decode DMA Descriptor of AGX100 Decoder device. */ > static void > agx100_print_dma_dec_desc_debug_info(union agx100_dma_desc *desc) > { > @@ -251,7 +251,7 @@ agx100_print_dma_dec_desc_debug_info(union agx100_dma_desc *desc) > word[12], word[13], word[14], word[15]); > } > > -/* Print decode DMA Descriptor of Vista Creek encoder device */ > +/* Print decode DMA Descriptor of Vista Creek encoder device. */ > static void > vc_5gnr_print_dma_enc_desc_debug_info(union vc_5gnr_dma_desc *desc) > { > @@ -284,7 +284,7 @@ vc_5gnr_print_dma_enc_desc_debug_info(union vc_5gnr_dma_desc *desc) > word[4], word[5], word[6], word[7]); > } > > -/* Print decode DMA Descriptor of AGX100 encoder device */ > +/* Print decode DMA Descriptor of AGX100 encoder device. */ > static void > agx100_print_dma_enc_desc_debug_info(union agx100_dma_desc *desc) > { > @@ -370,7 +370,7 @@ agx100_print_dma_enc_desc_debug_info(union agx100_dma_desc *desc) > static int > fpga_5gnr_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) > { > - /* Number of queues bound to a PF/VF */ > + /* Number of queues bound to a PF/VF. */ > uint32_t hw_q_num = 0; > uint32_t ring_size, payload, address, q_id, offset; > rte_iova_t phys_addr; > @@ -385,11 +385,11 @@ fpga_5gnr_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id > return -EPERM; > } > > - /* Clear queue registers structure */ > + /* Clear queue registers structure. */ > memset(&ring_reg, 0, sizeof(struct fpga_5gnr_ring_ctrl_reg)); > > if (d->fpga_variant == AGX100_FPGA_VARIANT) { > - /* Maximum number of queues possible for this device */ > + /* Maximum number of queues possible for this device. */ > d->total_num_queues = fpga_5gnr_reg_read_32( > d->mmio_base, > FPGA_5GNR_FEC_VERSION_ID) >> 24; > @@ -420,7 +420,7 @@ fpga_5gnr_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id > > if (hw_q_id != FPGA_5GNR_INVALID_HW_QUEUE_ID) { > d->q_bound_bit_map |= (1ULL << q_id); > - /* Clear queue register of found queue */ > + /* Clear queue register of found queue. */ > offset = FPGA_5GNR_FEC_RING_CTRL_REGS + > (sizeof(struct fpga_5gnr_ring_ctrl_reg) * q_id); > fpga_ring_reg_write(d->mmio_base, offset, ring_reg); > @@ -444,10 +444,10 @@ fpga_5gnr_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id > else > ring_size = FPGA_5GNR_RING_MAX_SIZE * sizeof(struct agx100_dma_dec_desc); > > - /* Enforce 32 byte alignment */ > + /* Enforce 32 byte alignment. */ > RTE_BUILD_BUG_ON((RTE_CACHE_LINE_SIZE % 32) != 0); > > - /* Allocate memory for SW descriptor rings */ > + /* Allocate memory for SW descriptor rings. */ > d->sw_rings = rte_zmalloc_socket(dev->device->driver->name, > num_queues * ring_size, RTE_CACHE_LINE_SIZE, > socket_id); > @@ -462,7 +462,7 @@ fpga_5gnr_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id > d->sw_ring_size = ring_size; > d->sw_ring_max_depth = FPGA_5GNR_RING_MAX_SIZE; > > - /* Allocate memory for ring flush status */ > + /* Allocate memory for ring flush status. */ > d->flush_queue_status = rte_zmalloc_socket(NULL, > sizeof(uint64_t), RTE_CACHE_LINE_SIZE, socket_id); > if (d->flush_queue_status == NULL) { > @@ -472,7 +472,7 @@ fpga_5gnr_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id > return -ENOMEM; > } > > - /* Set the flush status address registers */ > + /* Set the flush status address registers. */ > phys_addr = rte_malloc_virt2iova(d->flush_queue_status); > > address = FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_LW; > @@ -543,7 +543,7 @@ fpga_5gnr_dev_info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_ > RTE_BBDEV_END_OF_CAPABILITIES_LIST() > }; > > - /* Check the HARQ DDR size available */ > + /* Check the HARQ DDR size available (in MB). */ > uint8_t timeout_counter = 0; > uint32_t harq_buf_ready = fpga_5gnr_reg_read_32(d->mmio_base, > FPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS); > @@ -578,7 +578,7 @@ fpga_5gnr_dev_info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_ > dev_info->data_endianness = RTE_LITTLE_ENDIAN; > dev_info->device_status = RTE_BBDEV_DEV_NOT_SUPPORTED; > > - /* Calculates number of queues assigned to device */ > + /* Calculates number of queues assigned to device. */ > dev_info->max_num_queues = 0; > for (q_id = 0; q_id < d->total_num_queues; ++q_id) { > uint32_t hw_q_id; > @@ -591,7 +591,7 @@ fpga_5gnr_dev_info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_ > if (hw_q_id != FPGA_5GNR_INVALID_HW_QUEUE_ID) > dev_info->max_num_queues++; > } > - /* Expose number of queue per operation type */ > + /* Expose number of queue per operation type. */ > dev_info->num_queues[RTE_BBDEV_OP_NONE] = 0; > dev_info->num_queues[RTE_BBDEV_OP_TURBO_DEC] = 0; > dev_info->num_queues[RTE_BBDEV_OP_TURBO_ENC] = 0; > @@ -621,9 +621,9 @@ fpga_5gnr_find_free_queue_idx(struct rte_bbdev *dev, > > for (; i < range; ++i) { > q_idx = 1ULL << i; > - /* Check if index of queue is bound to current PF/VF */ > + /* Check if index of queue is bound to current PF/VF. */ > if (d->q_bound_bit_map & q_idx) > - /* Check if found queue was not already assigned */ > + /* Check if found queue was not already assigned. */ > if (!(d->q_assigned_bit_map & q_idx)) { > d->q_assigned_bit_map |= q_idx; > return i; > @@ -644,7 +644,7 @@ fpga_5gnr_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, > struct fpga_5gnr_queue *q; > int8_t q_idx; > > - /* Check if there is a free queue to assign */ > + /* Check if there is a free queue to assign. */ > q_idx = fpga_5gnr_find_free_queue_idx(dev, conf); > if (q_idx == -1) > return -1; > @@ -653,7 +653,7 @@ fpga_5gnr_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, > q = rte_zmalloc_socket(dev->device->driver->name, sizeof(*q), > RTE_CACHE_LINE_SIZE, conf->socket); > if (q == NULL) { > - /* Mark queue as un-assigned */ > + /* Mark queue as un-assigned. */ > d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q_idx)); > rte_bbdev_log(ERR, "Failed to allocate queue memory"); > return -ENOMEM; > @@ -662,7 +662,7 @@ fpga_5gnr_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, > q->d = d; > q->q_idx = q_idx; > > - /* Set ring_base_addr */ > + /* Set ring_base_addr. */ > if (d->fpga_variant == VC_5GNR_FPGA_VARIANT) > q->vc_5gnr_ring_addr = RTE_PTR_ADD(d->sw_rings, (d->sw_ring_size * queue_id)); > else > @@ -670,11 +670,11 @@ fpga_5gnr_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, > > q->ring_ctrl_reg.ring_base_addr = d->sw_rings_phys + (d->sw_ring_size * queue_id); > > - /* Allocate memory for Completion Head variable*/ > + /* Allocate memory for Completion Head variable. */ > q->ring_head_addr = rte_zmalloc_socket(dev->device->driver->name, > sizeof(uint64_t), RTE_CACHE_LINE_SIZE, conf->socket); > if (q->ring_head_addr == NULL) { > - /* Mark queue as un-assigned */ > + /* Mark queue as un-assigned. */ > d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q_idx)); > rte_free(q); > rte_bbdev_log(ERR, > @@ -682,15 +682,15 @@ fpga_5gnr_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, > dev->device->driver->name, dev->data->dev_id); > return -ENOMEM; > } > - /* Set ring_head_addr */ > + /* Set ring_head_addr. */ > q->ring_ctrl_reg.ring_head_addr = rte_malloc_virt2iova(q->ring_head_addr); > > - /* Clear shadow_completion_head */ > + /* Clear shadow_completion_head. */ > q->shadow_completion_head = 0; > > - /* Set ring_size */ > + /* Set ring_size. */ > if (conf->queue_size > FPGA_5GNR_RING_MAX_SIZE) { > - /* Mark queue as un-assigned */ > + /* Mark queue as un-assigned. */ > d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q_idx)); > rte_free(q->ring_head_addr); > rte_free(q); > @@ -703,34 +703,34 @@ fpga_5gnr_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, > q->ring_ctrl_reg.ring_size = conf->queue_size; > > /* Set Miscellaneous FPGA 5GNR register. */ > - /* Max iteration number for TTI mitigation - todo */ > + /* TODO: Max iteration number for TTI mitigation. */ > q->ring_ctrl_reg.max_ul_dec = 0; > - /* Enable max iteration number for TTI - todo */ > + /* TODO: Enable max iteration number for TTI. */ > q->ring_ctrl_reg.max_ul_dec_en = 0; > > - /* Enable the ring */ > + /* Enable the ring. */ > q->ring_ctrl_reg.enable = 1; > > - /* Set FPGA 5GNR head_point and tail registers */ > + /* Set FPGA 5GNR head_point and tail registers. */ > q->ring_ctrl_reg.head_point = q->tail = 0; > > - /* Set FPGA 5GNR shadow_tail register */ > + /* Set FPGA 5GNR shadow_tail register. */ > q->ring_ctrl_reg.shadow_tail = q->tail; > > - /* Calculates the ring offset for found queue */ > + /* Calculates the ring offset for found queue. */ > ring_offset = FPGA_5GNR_FEC_RING_CTRL_REGS + > (sizeof(struct fpga_5gnr_ring_ctrl_reg) * q_idx); > > - /* Set FPGA 5GNR Ring Control Registers */ > + /* Set FPGA 5GNR Ring Control Registers. */ > fpga_ring_reg_write(d->mmio_base, ring_offset, q->ring_ctrl_reg); > > - /* Store MMIO register of shadow_tail */ > + /* Store MMIO register of shadow_tail. */ > address = ring_offset + FPGA_5GNR_FEC_RING_SHADOW_TAIL; > q->shadow_tail_addr = RTE_PTR_ADD(d->mmio_base, address); > > q->head_free_desc = q->tail; > > - /* Set wrap mask */ > + /* Set wrap mask. */ > q->sw_ring_wrap_mask = conf->queue_size - 1; > > rte_bbdev_log_debug("Setup dev%u q%u: queue_idx=%u", > @@ -741,7 +741,7 @@ fpga_5gnr_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, > rte_bbdev_log_debug("BBDEV queue[%d] set up for FPGA 5GNR queue[%d]", queue_id, q_idx); > > #ifdef RTE_LIBRTE_BBDEV_DEBUG > - /* Read FPGA Ring Control Registers after configuration*/ > + /* Read FPGA Ring Control Registers after configuration. */ > print_ring_reg_debug_info(d->mmio_base, ring_offset); > #endif > return 0; > @@ -761,13 +761,13 @@ fpga_5gnr_queue_release(struct rte_bbdev *dev, uint16_t queue_id) > memset(&ring_reg, 0, sizeof(struct fpga_5gnr_ring_ctrl_reg)); > offset = FPGA_5GNR_FEC_RING_CTRL_REGS + > (sizeof(struct fpga_5gnr_ring_ctrl_reg) * q->q_idx); > - /* Disable queue */ > + /* Disable queue. */ > fpga_5gnr_reg_write_8(d->mmio_base, > offset + FPGA_5GNR_FEC_RING_ENABLE, 0x00); > - /* Clear queue registers */ > + /* Clear queue registers. */ > fpga_ring_reg_write(d->mmio_base, offset, ring_reg); > > - /* Mark the Queue as un-assigned */ > + /* Mark the Queue as un-assigned. */ > d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q->q_idx)); > rte_free(q->ring_head_addr); > rte_free(q); > @@ -798,14 +798,14 @@ fpga_5gnr_queue_start(struct rte_bbdev *dev, uint16_t queue_id) > return -1; > } > > - /* Clear queue head and tail variables */ > + /* Clear queue head and tail variables. */ > q->tail = q->head_free_desc = 0; > > - /* Clear FPGA 5GNR head_point and tail registers */ > + /* Clear FPGA 5GNR head_point and tail registers. */ > fpga_5gnr_reg_write_16(d->mmio_base, offset + FPGA_5GNR_FEC_RING_HEAD_POINT, zero); > fpga_5gnr_reg_write_16(d->mmio_base, offset + FPGA_5GNR_FEC_RING_SHADOW_TAIL, zero); > > - /* Enable queue */ > + /* Enable queue. */ > fpga_5gnr_reg_write_8(d->mmio_base, offset + FPGA_5GNR_FEC_RING_ENABLE, enable); > > rte_bbdev_log_debug("FPGA 5GNR Queue[%d] started", queue_id); > @@ -830,7 +830,7 @@ fpga_5gnr_queue_stop(struct rte_bbdev *dev, uint16_t queue_id) > uint8_t counter = 0; > uint8_t timeout = FPGA_5GNR_QUEUE_FLUSH_TIMEOUT_US / FPGA_5GNR_TIMEOUT_CHECK_INTERVAL; > > - /* Set flush_queue_en bit to trigger queue flushing */ > + /* Set flush_queue_en bit to trigger queue flushing. */ > fpga_5gnr_reg_write_8(d->mmio_base, > offset + FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN, payload); > > @@ -848,7 +848,7 @@ fpga_5gnr_queue_stop(struct rte_bbdev *dev, uint16_t queue_id) > counter++; > } > > - /* Disable queue */ > + /* Disable queue. */ > payload = 0x00; > fpga_5gnr_reg_write_8(d->mmio_base, offset + FPGA_5GNR_FEC_RING_ENABLE, payload); > > @@ -882,7 +882,7 @@ fpga_5gnr_dev_interrupt_handler(void *cb_arg) > uint16_t queue_id; > uint8_t i; > > - /* Scan queue assigned to this device */ > + /* Scan queue assigned to this device. */ > for (i = 0; i < d->total_num_queues; ++i) { > q_idx = 1ULL << i; > if (d->q_bound_bit_map & q_idx) { > @@ -890,7 +890,7 @@ fpga_5gnr_dev_interrupt_handler(void *cb_arg) > if (queue_id == (uint16_t) -1) > continue; > > - /* Check if completion head was changed */ > + /* Check if completion head was changed. */ > q = dev->data->queues[queue_id].queue_private; > ring_head = *q->ring_head_addr; > if (q->shadow_completion_head != ring_head && > @@ -1014,7 +1014,7 @@ fpga_5gnr_dma_enqueue(struct fpga_5gnr_queue *q, uint16_t num_desc, > uint64_t start_time = 0; > queue_stats->acc_offload_cycles = 0; > > - /* Update tail and shadow_tail register */ > + /* Update tail and shadow_tail register. */ > q->tail = (q->tail + num_desc) & q->sw_ring_wrap_mask; > > rte_wmb(); > @@ -1027,7 +1027,7 @@ fpga_5gnr_dma_enqueue(struct fpga_5gnr_queue *q, uint16_t num_desc, > queue_stats->acc_offload_cycles += rte_rdtsc_precise() - start_time; > } > > -/* Read flag value 0/1/ from bitmap */ > +/* Read flag value 0/1/ from bitmap. */ > static inline bool > check_bit(uint32_t bitmap, uint32_t bitmask) > { > @@ -1171,7 +1171,7 @@ get_k0(uint16_t n_cb, uint16_t z_c, uint8_t bg, uint8_t rv_index) > else > return (bg == 1 ? K0_3_1 : K0_3_2) * z_c; > } > - /* LBRM case - includes a division by N */ > + /* LBRM case - includes a division by N. */ > if (rv_index == 1) > return (((bg == 1 ? K0_1_1 : K0_1_2) * n_cb) > / n) * z_c; > @@ -1215,7 +1215,7 @@ vc_5gnr_dma_desc_te_fill(struct rte_bbdev_enc_op *op, > uint32_t in_offset, uint32_t out_offset, uint16_t desc_offset, > uint8_t cbs_in_op) > { > - /* reset */ > + /* reset. */ > desc->done = 0; > desc->error = 0; > desc->k_ = k_; > @@ -1231,7 +1231,7 @@ vc_5gnr_dma_desc_te_fill(struct rte_bbdev_enc_op *op, > op->ldpc_enc.basegraph, op->ldpc_enc.rv_index); > desc->ncb = op->ldpc_enc.n_cb; > desc->num_null = op->ldpc_enc.n_filler; > - /* Set inbound data buffer address */ > + /* Set inbound data buffer address. */ > desc->in_addr_hi = (uint32_t)( > rte_pktmbuf_iova_offset(input, in_offset) >> 32); > desc->in_addr_lw = (uint32_t)( > @@ -1241,9 +1241,9 @@ vc_5gnr_dma_desc_te_fill(struct rte_bbdev_enc_op *op, > rte_pktmbuf_iova_offset(output, out_offset) >> 32); > desc->out_addr_lw = (uint32_t)( > rte_pktmbuf_iova_offset(output, out_offset)); > - /* Save software context needed for dequeue */ > + /* Save software context needed for dequeue. */ > desc->op_addr = op; > - /* Set total number of CBs in an op */ > + /* Set total number of CBs in an op. */ > desc->cbs_in_op = cbs_in_op; > return 0; > } > @@ -1280,7 +1280,7 @@ agx100_dma_desc_le_fill(struct rte_bbdev_enc_op *op, > uint32_t in_offset, uint32_t out_offset, uint16_t desc_offset, > uint8_t cbs_in_op) > { > - /* reset */ > + /* reset. */ > desc->done = 0; > desc->error_msg = 0; > desc->error_code = 0; > @@ -1289,28 +1289,28 @@ agx100_dma_desc_le_fill(struct rte_bbdev_enc_op *op, > desc->qm_idx = op->ldpc_enc.q_m >> 1; > desc->zc = op->ldpc_enc.z_c; > desc->rv = op->ldpc_enc.rv_index; > - desc->int_en = 0; /**< Set by device externally*/ > - desc->max_cbg = 0; /*TODO: CBG specific */ > - desc->cbgti = 0; /*TODO: CBG specific */ > - desc->cbgs = 0; /*TODO: CBG specific */ > + desc->int_en = 0; /**< Set by device externally. */ > + desc->max_cbg = 0; /**< TODO: CBG specific. */ > + desc->cbgti = 0; /**< TODO: CBG specific. */ > + desc->cbgs = 0; /**< TODO: CBG specific. */ > desc->desc_idx = desc_offset; > - desc->ca = 0; /*TODO: CBG specific */ > - desc->c = 0; /*TODO: CBG specific */ > + desc->ca = 0; /**< TODO: CBG specific. */ > + desc->c = 0; /**< TODO: CBG specific. */ > desc->num_null = op->ldpc_enc.n_filler; > desc->ea = e; > - desc->eb = e; /*TODO: TB/CBG specific */ > + desc->eb = e; /**< TODO: TB/CBG specific. */ > desc->k_ = k_; > - desc->en_slice_ts = 0; /*TODO: Slice specific*/ > - desc->en_host_ts = 0; /*TODO: Slice specific*/ > - desc->en_cb_wr_status = 0; /*TODO: Event Queue specific*/ > - desc->en_output_sg = 0; /*TODO: Slice specific*/ > - desc->en_input_sg = 0; /*TODO: Slice specific*/ > - desc->tb_cb = 0; /*Descriptor for CB. TODO: Add TB and CBG logic*/ > + desc->en_slice_ts = 0; /**< TODO: Slice specific. */ > + desc->en_host_ts = 0; /**< TODO: Slice specific. */ > + desc->en_cb_wr_status = 0; /**< TODO: Event Queue specific. */ > + desc->en_output_sg = 0; /**< TODO: Slice specific. */ > + desc->en_input_sg = 0; /**< TODO: Slice specific. */ > + desc->tb_cb = 0; /**< Descriptor for CB. TODO: Add TB and CBG logic. */ > desc->crc_en = check_bit(op->ldpc_enc.op_flags, > RTE_BBDEV_LDPC_CRC_24B_ATTACH); > > - /* Set inbound/outbound data buffer address */ > - /* TODO: add logic for input_slice */ > + /* Set inbound/outbound data buffer address. */ > + /* TODO: add logic for input_slice. */ > desc->output_start_addr_hi = (uint32_t)( > rte_pktmbuf_iova_offset(output, out_offset) >> 32); > desc->output_start_addr_lo = (uint32_t)( > @@ -1319,13 +1319,13 @@ agx100_dma_desc_le_fill(struct rte_bbdev_enc_op *op, > rte_pktmbuf_iova_offset(input, in_offset) >> 32); > desc->input_start_addr_lo = (uint32_t)( > rte_pktmbuf_iova_offset(input, in_offset)); > - desc->output_length = (e + 7) >> 3; /* in bytes */ > + desc->output_length = (e + 7) >> 3; /* in bytes. */ > desc->input_length = input->data_len; > desc->enqueue_timestamp = 0; > desc->completion_timestamp = 0; > - /* Save software context needed for dequeue */ > + /* Save software context needed for dequeue. */ > desc->op_addr = op; > - /* Set total number of CBs in an op */ > + /* Set total number of CBs in an op. */ > desc->cbs_in_op = cbs_in_op; > return 0; > } > @@ -1359,10 +1359,10 @@ vc_5gnr_dma_desc_ld_fill(struct rte_bbdev_dec_op *op, > uint16_t desc_offset, > uint8_t cbs_in_op) > { > - /* reset */ > + /* reset. */ > desc->done = 0; > desc->error = 0; > - /* Set inbound data buffer address */ > + /* Set inbound data buffer address. */ > desc->in_addr_hi = (uint32_t)( > rte_pktmbuf_iova_offset(input, in_offset) >> 32); > desc->in_addr_lw = (uint32_t)( > @@ -1390,9 +1390,9 @@ vc_5gnr_dma_desc_ld_fill(struct rte_bbdev_dec_op *op, > rte_pktmbuf_iova_offset(output, out_offset) >> 32); > desc->out_addr_lw = (uint32_t)( > rte_pktmbuf_iova_offset(output, out_offset)); > - /* Save software context needed for dequeue */ > + /* Save software context needed for dequeue. */ > desc->op_addr = op; > - /* Set total number of CBs in an op */ > + /* Set total number of CBs in an op. */ > desc->cbs_in_op = cbs_in_op; > > return 0; > @@ -1428,13 +1428,13 @@ agx100_dma_desc_ld_fill(struct rte_bbdev_dec_op *op, > uint16_t desc_offset, > uint8_t cbs_in_op) > { > - /* reset */ > + /* reset. */ > desc->done = 0; > desc->tb_crc_pass = 0; > desc->cb_crc_all_pass = 0; > desc->cb_all_et_pass = 0; > desc->max_iter_ret = 0; > - desc->cgb_crc_bitmap = 0; /*TODO: CBG specific */ > + desc->cgb_crc_bitmap = 0; /**< TODO: CBG specific. */ > desc->error_msg = 0; > desc->error_code = 0; > desc->et_dis = !check_bit(op->ldpc_dec.op_flags, > @@ -1447,36 +1447,36 @@ agx100_dma_desc_ld_fill(struct rte_bbdev_dec_op *op, > desc->qm_idx = op->ldpc_dec.q_m >> 1; > desc->zc = op->ldpc_dec.z_c; > desc->rv = op->ldpc_dec.rv_index; > - desc->int_en = 0; /**< Set by device externally*/ > - desc->max_cbg = 0; /*TODO: CBG specific*/ > - desc->cbgti = 0; /*TODO: CBG specific*/ > - desc->cbgfi = 0; /*TODO: CBG specific*/ > - desc->cbgs = 0; /*TODO: CBG specific*/ > + desc->int_en = 0; /**< Set by device externally. */ > + desc->max_cbg = 0; /**< TODO: CBG specific. */ > + desc->cbgti = 0; /**< TODO: CBG specific. */ > + desc->cbgfi = 0; /**< TODO: CBG specific. */ > + desc->cbgs = 0; /**< TODO: CBG specific. */ > desc->desc_idx = desc_offset; > - desc->ca = 0; /*TODO: CBG specific*/ > - desc->c = 0; /*TODO: CBG specific*/ > - desc->llr_pckg = 0; /*TODO: Not implemented yet*/ > - desc->syndrome_check_mode = 1; /*TODO: Make it configurable*/ > + desc->ca = 0; /**< TODO: CBG specific. */ > + desc->c = 0; /**< TODO: CBG specific. */ > + desc->llr_pckg = 0; /**< TODO: Not implemented yet. */ > + desc->syndrome_check_mode = 1; /**< TODO: Make it configurable. */ > desc->num_null = op->ldpc_dec.n_filler; > - desc->ea = op->ldpc_dec.cb_params.e; /*TODO: TB/CBG specific*/ > - desc->eba = 0; /*TODO: TB/CBG specific*/ > + desc->ea = op->ldpc_dec.cb_params.e; /**< TODO: TB/CBG specific. */ > + desc->eba = 0; /**< TODO: TB/CBG specific. */ > desc->hbstore_offset_out = harq_out_offset >> 10; > desc->hbstore_offset_in = harq_in_offset >> 10; > - desc->en_slice_ts = 0; /*TODO: Slice specific*/ > - desc->en_host_ts = 0; /*TODO: Slice specific*/ > - desc->en_cb_wr_status = 0; /*TODO: Event Queue specific*/ > - desc->en_output_sg = 0; /*TODO: Slice specific*/ > - desc->en_input_sg = 0; /*TODO: Slice specific*/ > - desc->tb_cb = 0; /* Descriptor for CB. TODO: Add TB and CBG logic*/ > + desc->en_slice_ts = 0; /**< TODO: Slice specific. */ > + desc->en_host_ts = 0; /**< TODO: Slice specific. */ > + desc->en_cb_wr_status = 0; /**< TODO: Event Queue specific. */ > + desc->en_output_sg = 0; /**< TODO: Slice specific. */ > + desc->en_input_sg = 0; /**< TODO: Slice specific. */ > + desc->tb_cb = 0; /**< Descriptor for CB. TODO: Add TB and CBG logic. */ > desc->crc24b_ind = check_bit(op->ldpc_dec.op_flags, > RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK); > desc->drop_crc24b = check_bit(op->ldpc_dec.op_flags, > RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP); > desc->harq_input_length_a = > - harq_in_length; /*Descriptor for CB. TODO: Add TB and CBG logic*/ > - desc->harq_input_length_b = 0; /*Descriptor for CB. TODO: Add TB and CBG logic*/ > - /* Set inbound/outbound data buffer address */ > - /* TODO: add logic for input_slice */ > + harq_in_length; /**< Descriptor for CB. TODO: Add TB and CBG logic. */ > + desc->harq_input_length_b = 0; /**< Descriptor for CB. TODO: Add TB and CBG logic. */ > + /* Set inbound/outbound data buffer address. */ > + /* TODO: add logic for input_slice. */ > desc->output_start_addr_hi = (uint32_t)( > rte_pktmbuf_iova_offset(output, out_offset) >> 32); > desc->output_start_addr_lo = (uint32_t)( > @@ -1487,12 +1487,12 @@ agx100_dma_desc_ld_fill(struct rte_bbdev_dec_op *op, > rte_pktmbuf_iova_offset(input, in_offset)); > desc->output_length = (((op->ldpc_dec.basegraph == 1) ? 22 : 10) * op->ldpc_dec.z_c > - op->ldpc_dec.n_filler - desc->drop_crc24b * 24) >> 3; > - desc->input_length = op->ldpc_dec.cb_params.e; /*TODO: TB/CBG specific*/ > + desc->input_length = op->ldpc_dec.cb_params.e; /**< TODO: TB/CBG specific. */ > desc->enqueue_timestamp = 0; > desc->completion_timestamp = 0; > - /* Save software context needed for dequeue */ > + /* Save software context needed for dequeue. */ > desc->op_addr = op; > - /* Set total number of CBs in an op */ > + /* Set total number of CBs in an op. */ > desc->cbs_in_op = cbs_in_op; > return 0; > } > @@ -1546,7 +1546,7 @@ vc_5gnr_validate_ldpc_enc_op(struct rte_bbdev_enc_op *op) > } > > z_c = ldpc_enc->z_c; > - /* Check Zc is valid value */ > + /* Check Zc is valid value. */ > if ((z_c > 384) || (z_c < 4)) { > rte_bbdev_log(ERR, "Zc (%u) is out of range", z_c); > return -1; > @@ -1602,7 +1602,7 @@ vc_5gnr_validate_ldpc_enc_op(struct rte_bbdev_enc_op *op) > > } > > - /* K' range check */ > + /* K' range check. */ > if (Kp % 8 > 0) { > rte_bbdev_log(ERR, "K' not byte aligned %u", Kp); > return -1; > @@ -1619,23 +1619,23 @@ vc_5gnr_validate_ldpc_enc_op(struct rte_bbdev_enc_op *op) > rte_bbdev_log(ERR, "K - F invalid %u %u", K, n_filler); > return -1; > } > - /* Ncb range check */ > + /* Ncb range check. */ > if ((n_cb > N) || (n_cb < 32) || (n_cb <= (Kp - crc24))) { > rte_bbdev_log(ERR, "Ncb (%u) is out of range K %d N %d", n_cb, K, N); > return -1; > } > - /* Qm range check */ > + /* Qm range check. */ > if (!check_bit(op->ldpc_enc.op_flags, RTE_BBDEV_LDPC_INTERLEAVER_BYPASS) && > ((q_m == 0) || ((q_m > 2) && ((q_m % 2) == 1)) || (q_m > 8))) { > rte_bbdev_log(ERR, "Qm (%u) is out of range", q_m); > return -1; > } > - /* K0 range check */ > + /* K0 range check. */ > if (((k0 % z_c) > 0) || (k0 >= n_cb) || ((k0 >= (Kp - 2 * z_c)) && (k0 < (K - 2 * z_c)))) { > rte_bbdev_log(ERR, "K0 (%u) is out of range", k0); > return -1; > } > - /* E range check */ > + /* E range check. */ > if (e <= RTE_MAX(32, z_c)) { > rte_bbdev_log(ERR, "E is too small %"PRIu32"", e); > return -1; > @@ -1650,7 +1650,7 @@ vc_5gnr_validate_ldpc_enc_op(struct rte_bbdev_enc_op *op) > return -1; > } > } > - /* Code word in RM range check */ > + /* Code word in RM range check. */ > if (k0 > (Kp - 2 * z_c)) > L = k0 + e; > else > @@ -1750,7 +1750,7 @@ vc_5gnr_validate_ldpc_dec_op(struct rte_bbdev_dec_op *op) > } > > z_c = ldpc_dec->z_c; > - /* Check Zc is valid value */ > + /* Check Zc is valid value. */ > if ((z_c > 384) || (z_c < 4)) { > rte_bbdev_log(ERR, "Zc (%u) is out of range", z_c); > return -1; > @@ -1799,7 +1799,7 @@ vc_5gnr_validate_ldpc_dec_op(struct rte_bbdev_dec_op *op) > rte_bbdev_log(ERR, "TB mode not supported"); > return -1; > } > - /* Enforce HARQ input length */ > + /* Enforce HARQ input length. */ > ldpc_dec->harq_combined_input.length = RTE_MIN((uint32_t) n_cb, > ldpc_dec->harq_combined_input.length); > if ((ldpc_dec->harq_combined_input.length == 0) && > @@ -1816,7 +1816,7 @@ vc_5gnr_validate_ldpc_dec_op(struct rte_bbdev_dec_op *op) > ldpc_dec->harq_combined_input.length = 0; > } > > - /* K' range check */ > + /* K' range check. */ > if (Kp % 8 > 0) { > rte_bbdev_log(ERR, "K' not byte aligned %u", Kp); > return -1; > @@ -1833,12 +1833,12 @@ vc_5gnr_validate_ldpc_dec_op(struct rte_bbdev_dec_op *op) > rte_bbdev_log(ERR, "K - F invalid %u %u", K, n_filler); > return -1; > } > - /* Ncb range check */ > + /* Ncb range check. */ > if (n_cb != N) { > rte_bbdev_log(ERR, "Ncb (%u) is out of range K %d N %d", n_cb, K, N); > return -1; > } > - /* Qm range check */ > + /* Qm range check. */ > if (!check_bit(op->ldpc_dec.op_flags, > RTE_BBDEV_LDPC_INTERLEAVER_BYPASS) && > ((q_m == 0) || ((q_m > 2) && ((q_m % 2) == 1)) > @@ -1846,12 +1846,12 @@ vc_5gnr_validate_ldpc_dec_op(struct rte_bbdev_dec_op *op) > rte_bbdev_log(ERR, "Qm (%u) is out of range", q_m); > return -1; > } > - /* K0 range check */ > + /* K0 range check. */ > if (((k0 % z_c) > 0) || (k0 >= n_cb) || ((k0 >= (Kp - 2 * z_c)) && (k0 < (K - 2 * z_c)))) { > rte_bbdev_log(ERR, "K0 (%u) is out of range", k0); > return -1; > } > - /* E range check */ > + /* E range check. */ > if (e <= RTE_MAX(32, z_c)) { > rte_bbdev_log(ERR, "E is too small"); > return -1; > @@ -1866,7 +1866,7 @@ vc_5gnr_validate_ldpc_dec_op(struct rte_bbdev_dec_op *op) > return -1; > } > } > - /* Code word in RM range check */ > + /* Code word in RM range check. */ > if (k0 > (Kp - 2 * z_c)) > L = k0 + e; > else > @@ -1924,9 +1924,9 @@ static inline void > fpga_5gnr_mutex_acquisition(struct fpga_5gnr_queue *q) > { > uint32_t mutex_ctrl, mutex_read, cnt = 0; > - /* Assign a unique id for the duration of the DDR access */ > + /* Assign a unique id for the duration of the DDR access. */ > q->ddr_mutex_uuid = rand(); > - /* Request and wait for acquisition of the mutex */ > + /* Request and wait for acquisition of the mutex. */ > mutex_ctrl = (q->ddr_mutex_uuid << 16) + 1; > do { > if (cnt > 0) > @@ -2121,7 +2121,7 @@ enqueue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op *o > } > } > > - /* Clear op status */ > + /* Clear op status. */ > op->status = 0; > > if (m_in == NULL || m_out == NULL) { > @@ -2134,15 +2134,15 @@ enqueue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op *o > crc24_bits = 24; > > if (enc->code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) { > - /* TODO: For Transport Block mode */ > + /* TODO: For Transport Block mode. */ > rte_bbdev_log(ERR, "Transport Block not supported yet"); > return -1; > } > - /* For Code Block mode */ > + /* For Code Block mode. */ > c = 1; > e = enc->cb_params.e; > > - /* Update total_left */ > + /* Update total_left. */ > K = (enc->basegraph == 1 ? 22 : 10) * enc->z_c; > k_ = K - enc->n_filler; > in_length = (k_ - crc24_bits) >> 3; > @@ -2150,7 +2150,7 @@ enqueue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op *o > > total_left = rte_pktmbuf_data_len(m_in) - in_offset; > > - /* Update offsets */ > + /* Update offsets. */ > if (total_left != in_length) { > op->status |= 1 << RTE_BBDEV_DATA_ERROR; > rte_bbdev_log(ERR, > @@ -2160,16 +2160,16 @@ enqueue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op *o > > mbuf_append(m_out_head, m_out, out_length); > > - /* Offset into the ring */ > + /* Offset into the ring. */ > ring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask); > > if (d->fpga_variant == VC_5GNR_FPGA_VARIANT) { > - /* Setup DMA Descriptor */ > + /* Setup DMA Descriptor. */ > vc_5gnr_desc = q->vc_5gnr_ring_addr + ring_offset; > ret = vc_5gnr_dma_desc_te_fill(op, &vc_5gnr_desc->vc_5gnr_enc_req, m_in, m_out, > k_, e, in_offset, out_offset, ring_offset, c); > } else { > - /* Setup DMA Descriptor */ > + /* Setup DMA Descriptor. */ > agx100_desc = q->agx100_ring_addr + ring_offset; > ret = agx100_dma_desc_le_fill(op, &agx100_desc->agx100_enc_req, m_in, m_out, > k_, e, in_offset, out_offset, ring_offset, c); > @@ -2178,7 +2178,7 @@ enqueue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op *o > if (unlikely(ret < 0)) > return ret; > > - /* Update lengths */ > + /* Update lengths. */ > total_left -= in_length; > op->ldpc_enc.output.length += out_length; > > @@ -2222,10 +2222,10 @@ vc_5gnr_enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_d > return -EINVAL; > } > > - /* Clear op status */ > + /* Clear op status. */ > op->status = 0; > > - /* Setup DMA Descriptor */ > + /* Setup DMA Descriptor. */ > ring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask); > vc_5gnr_desc = q->vc_5gnr_ring_addr + ring_offset; > > @@ -2252,16 +2252,16 @@ vc_5gnr_enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_d > ret = -1; > } > > - /* Set descriptor for dequeue */ > + /* Set descriptor for dequeue. */ > vc_5gnr_desc->vc_5gnr_dec_req.done = 1; > vc_5gnr_desc->vc_5gnr_dec_req.error = 0; > vc_5gnr_desc->vc_5gnr_dec_req.op_addr = op; > vc_5gnr_desc->vc_5gnr_dec_req.cbs_in_op = 1; > > - /* Mark this dummy descriptor to be dropped by HW */ > + /* Mark this dummy descriptor to be dropped by HW. */ > vc_5gnr_desc->vc_5gnr_dec_req.desc_idx = (ring_offset + 1) & q->sw_ring_wrap_mask; > > - return ret; /* Error or number of CB */ > + return ret; /* Error or number of CB. */ > } > > if (m_in == NULL || m_out == NULL) { > @@ -2316,7 +2316,7 @@ vc_5gnr_enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_d > > if (unlikely(ret < 0)) > return ret; > - /* Update lengths */ > + /* Update lengths. */ > seg_total_left -= in_length; > op->ldpc_dec.hard_output.length += out_length; > if (seg_total_left > 0) { > @@ -2353,10 +2353,10 @@ agx100_enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_de > uint32_t harq_in_offset = 0; > uint32_t harq_out_offset = 0; > > - /* Clear op status */ > + /* Clear op status. */ > op->status = 0; > > - /* Setup DMA Descriptor */ > + /* Setup DMA Descriptor. */ > ring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask); > desc = q->agx100_ring_addr + ring_offset; > > @@ -2382,17 +2382,17 @@ agx100_enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_de > ret = -1; > } > > - /* Set descriptor for dequeue */ > + /* Set descriptor for dequeue. */ > desc->agx100_dec_req.done = 1; > desc->agx100_dec_req.error_code = 0; > desc->agx100_dec_req.error_msg = 0; > desc->agx100_dec_req.op_addr = op; > desc->agx100_dec_req.cbs_in_op = 1; > > - /* Mark this dummy descriptor to be dropped by HW */ > + /* Mark this dummy descriptor to be dropped by HW. */ > desc->agx100_dec_req.desc_idx = (ring_offset + 1) & q->sw_ring_wrap_mask; > > - return ret; /* Error or number of CB */ > + return ret; /* Error or number of CB. */ > } > > if (m_in == NULL || m_out == NULL) { > @@ -2438,7 +2438,7 @@ agx100_enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_de > > if (unlikely(ret < 0)) > return ret; > - /* Update lengths */ > + /* Update lengths. */ > seg_total_left -= in_length; > op->ldpc_dec.hard_output.length += out_length; > if (seg_total_left > 0) { > @@ -2467,11 +2467,11 @@ fpga_5gnr_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data, > union agx100_dma_desc *agx100_desc; > struct fpga_5gnr_fec_device *d = q->d; > > - /* Check if queue is not full */ > + /* Check if queue is not full. */ > if (unlikely(((q->tail + 1) & q->sw_ring_wrap_mask) == q->head_free_desc)) > return 0; > > - /* Calculates available space */ > + /* Calculates available space. */ > avail = (q->head_free_desc > q->tail) ? > q->head_free_desc - q->tail - 1 : > q->ring_ctrl_reg.ring_size + q->head_free_desc - q->tail - 1; > @@ -2510,7 +2510,7 @@ fpga_5gnr_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data, > > fpga_5gnr_dma_enqueue(q, total_enqueued_cbs, &q_data->queue_stats); > > - /* Update stats */ > + /* Update stats. */ > q_data->queue_stats.enqueued_count += i; > q_data->queue_stats.enqueue_err_count += num - i; > > @@ -2529,11 +2529,11 @@ fpga_5gnr_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data, > union agx100_dma_desc *agx100_desc; > struct fpga_5gnr_fec_device *d = q->d; > > - /* Check if queue is not full */ > + /* Check if queue is not full. */ > if (unlikely(((q->tail + 1) & q->sw_ring_wrap_mask) == q->head_free_desc)) > return 0; > > - /* Calculates available space */ > + /* Calculates available space. */ > avail = (q->head_free_desc > q->tail) ? > q->head_free_desc - q->tail - 1 : > q->ring_ctrl_reg.ring_size + q->head_free_desc - q->tail - 1; > @@ -2564,7 +2564,7 @@ fpga_5gnr_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data, > q->head_free_desc, q->tail); > } > > - /* Update stats */ > + /* Update stats. */ > q_data->queue_stats.enqueued_count += i; > q_data->queue_stats.enqueue_err_count += num - i; > > @@ -2592,14 +2592,14 @@ vc_5gnr_dequeue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_e > { > union vc_5gnr_dma_desc *desc; > int desc_error; > - /* Set current desc */ > + /* Set current desc. */ > desc = q->vc_5gnr_ring_addr + ((q->head_free_desc + desc_offset) & q->sw_ring_wrap_mask); > > - /*check if done */ > + /*check if done. */ > if (desc->vc_5gnr_enc_req.done == 0) > return -1; > > - /* make sure the response is read atomically */ > + /* make sure the response is read atomically. */ > rte_smp_rmb(); > > rte_bbdev_log_debug("DMA response desc %p", desc); > @@ -2608,7 +2608,7 @@ vc_5gnr_dequeue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_e > vc_5gnr_print_dma_enc_desc_debug_info(desc); > #endif > *op = desc->vc_5gnr_enc_req.op_addr; > - /* Check the descriptor error field, return 1 on error */ > + /* Check the descriptor error field, return 1 on error. */ > desc_error = vc_5gnr_check_desc_error(desc->vc_5gnr_enc_req.error); > (*op)->status = desc_error << RTE_BBDEV_DATA_ERROR; > > @@ -2622,13 +2622,13 @@ agx100_dequeue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_en > union agx100_dma_desc *desc; > int desc_error; > > - /* Set current desc */ > + /* Set current desc. */ > desc = q->agx100_ring_addr + ((q->head_free_desc + desc_offset) & q->sw_ring_wrap_mask); > - /*check if done */ > + /*check if done. */ > if (desc->agx100_enc_req.done == 0) > return -1; > > - /* make sure the response is read atomically */ > + /* make sure the response is read atomically. */ > rte_smp_rmb(); > > rte_bbdev_log_debug("DMA response desc %p", desc); > @@ -2637,7 +2637,7 @@ agx100_dequeue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_en > agx100_print_dma_enc_desc_debug_info(desc); > #endif > *op = desc->agx100_enc_req.op_addr; > - /* Check the descriptor error field, return 1 on error */ > + /* Check the descriptor error field, return 1 on error. */ > desc_error = agx100_check_desc_error(desc->agx100_enc_req.error_code, > desc->agx100_enc_req.error_msg); > > @@ -2653,14 +2653,14 @@ vc_5gnr_dequeue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_d > union vc_5gnr_dma_desc *desc; > int desc_error; > > - /* Set descriptor */ > + /* Set descriptor. */ > desc = q->vc_5gnr_ring_addr + ((q->head_free_desc + desc_offset) & q->sw_ring_wrap_mask); > > - /* Verify done bit is set */ > + /* Verify done bit is set. */ > if (desc->vc_5gnr_dec_req.done == 0) > return -1; > > - /* make sure the response is read atomically */ > + /* make sure the response is read atomically. */ > rte_smp_rmb(); > > #ifdef RTE_LIBRTE_BBDEV_DEBUG > @@ -2675,17 +2675,17 @@ vc_5gnr_dequeue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_d > return 1; > } > > - /* FPGA reports iterations based on round-up minus 1 */ > + /* FPGA reports iterations based on round-up minus 1. */ > (*op)->ldpc_dec.iter_count = desc->vc_5gnr_dec_req.iter + 1; > > - /* CRC Check criteria */ > + /* CRC Check criteria. */ > if (desc->vc_5gnr_dec_req.crc24b_ind && !(desc->vc_5gnr_dec_req.crcb_pass)) > (*op)->status = 1 << RTE_BBDEV_CRC_ERROR; > > - /* et_pass = 0 when decoder fails */ > + /* et_pass = 0 when decoder fails. */ > (*op)->status |= !(desc->vc_5gnr_dec_req.et_pass) << RTE_BBDEV_SYNDROME_ERROR; > > - /* Check the descriptor error field, return 1 on error */ > + /* Check the descriptor error field, return 1 on error. */ > desc_error = vc_5gnr_check_desc_error(desc->vc_5gnr_dec_req.error); > > (*op)->status |= desc_error << RTE_BBDEV_DATA_ERROR; > @@ -2700,14 +2700,14 @@ agx100_dequeue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_de > union agx100_dma_desc *desc; > int desc_error; > > - /* Set descriptor */ > + /* Set descriptor. */ > desc = q->agx100_ring_addr + > ((q->head_free_desc + desc_offset) & q->sw_ring_wrap_mask); > - /* Verify done bit is set */ > + /* Verify done bit is set. */ > if (desc->agx100_dec_req.done == 0) > return -1; > > - /* make sure the response is read atomically */ > + /* make sure the response is read atomically. */ > rte_smp_rmb(); > > #ifdef RTE_LIBRTE_BBDEV_DEBUG > @@ -2721,17 +2721,17 @@ agx100_dequeue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_de > return 1; > } > > - /* FPGA reports iterations based on round-up minus 1 */ > + /* FPGA reports iterations based on round-up minus 1. */ > (*op)->ldpc_dec.iter_count = desc->agx100_dec_req.max_iter_ret + 1; > > - /* CRC Check criteria */ > + /* CRC Check criteria. */ > if (desc->agx100_dec_req.crc24b_ind && !(desc->agx100_dec_req.cb_crc_all_pass)) > (*op)->status = 1 << RTE_BBDEV_CRC_ERROR; > > - /* et_pass = 0 when decoder fails */ > + /* et_pass = 0 when decoder fails. */ > (*op)->status |= !(desc->agx100_dec_req.cb_all_et_pass) << RTE_BBDEV_SYNDROME_ERROR; > > - /* Check the descriptor error field, return 1 on error */ > + /* Check the descriptor error field, return 1 on error. */ > desc_error = agx100_check_desc_error(desc->agx100_dec_req.error_code, > desc->agx100_dec_req.error_msg); > > @@ -2764,11 +2764,11 @@ fpga_5gnr_dequeue_ldpc_enc(struct rte_bbdev_queue_data *q_data, > dequeued_cbs, num, q->head_free_desc, q->tail); > } > > - /* Update head */ > + /* Update head. */ > q->head_free_desc = (q->head_free_desc + dequeued_cbs) & > q->sw_ring_wrap_mask; > > - /* Update stats */ > + /* Update stats. */ > q_data->queue_stats.dequeued_count += i; > > return i; > @@ -2799,17 +2799,17 @@ fpga_5gnr_dequeue_ldpc_dec(struct rte_bbdev_queue_data *q_data, > dequeued_cbs, num, q->head_free_desc, q->tail); > } > > - /* Update head */ > + /* Update head. */ > q->head_free_desc = (q->head_free_desc + dequeued_cbs) & q->sw_ring_wrap_mask; > > - /* Update stats */ > + /* Update stats. */ > q_data->queue_stats.dequeued_count += i; > > return i; > } > > > -/* Initialization Function */ > +/* Initialization Function. */ > static void > fpga_5gnr_fec_init(struct rte_bbdev *dev, struct rte_pci_driver *drv) > { > @@ -2821,7 +2821,7 @@ fpga_5gnr_fec_init(struct rte_bbdev *dev, struct rte_pci_driver *drv) > dev->dequeue_ldpc_enc_ops = fpga_5gnr_dequeue_ldpc_enc; > dev->dequeue_ldpc_dec_ops = fpga_5gnr_dequeue_ldpc_dec; > > - /* Device variant specific handling */ > + /* Device variant specific handling. */ > if ((pci_dev->id.device_id == AGX100_PF_DEVICE_ID) || > (pci_dev->id.device_id == AGX100_VF_DEVICE_ID)) { > ((struct fpga_5gnr_fec_device *) dev->data->dev_private)->fpga_variant = > @@ -2830,7 +2830,7 @@ fpga_5gnr_fec_init(struct rte_bbdev *dev, struct rte_pci_driver *drv) > !strcmp(drv->driver.name, RTE_STR(FPGA_5GNR_FEC_PF_DRIVER_NAME)); > ((struct fpga_5gnr_fec_device *) dev->data->dev_private)->mmio_base = > pci_dev->mem_resource[0].addr; > - /* Maximum number of queues possible for this device */ > + /* Maximum number of queues possible for this device. */ > ((struct fpga_5gnr_fec_device *) dev->data->dev_private)->total_num_queues = > fpga_5gnr_reg_read_32(pci_dev->mem_resource[0].addr, > FPGA_5GNR_FEC_VERSION_ID) >> 24; > @@ -2867,12 +2867,12 @@ fpga_5gnr_fec_probe(struct rte_pci_driver *pci_drv, > > rte_pci_device_name(&pci_dev->addr, dev_name, sizeof(dev_name)); > > - /* Allocate memory to be used privately by drivers */ > + /* Allocate memory to be used privately by drivers. */ > bbdev = rte_bbdev_allocate(pci_dev->device.name); > if (bbdev == NULL) > return -ENODEV; > > - /* allocate device private memory */ > + /* allocate device private memory. */ > bbdev->data->dev_private = rte_zmalloc_socket(dev_name, > sizeof(struct fpga_5gnr_fec_device), > RTE_CACHE_LINE_SIZE, > @@ -2886,12 +2886,12 @@ fpga_5gnr_fec_probe(struct rte_pci_driver *pci_drv, > return -ENOMEM; > } > > - /* Fill HW specific part of device structure */ > + /* Fill HW specific part of device structure. */ > bbdev->device = &pci_dev->device; > bbdev->intr_handle = pci_dev->intr_handle; > bbdev->data->socket_id = pci_dev->device.numa_node; > > - /* Invoke FPGA 5GNR FEC device initialization function */ > + /* Invoke FPGA 5GNR FEC device initialization function. */ > fpga_5gnr_fec_init(bbdev, pci_drv); > > rte_bbdev_log_debug("bbdev id = %u [%s]", > @@ -2929,7 +2929,7 @@ fpga_5gnr_fec_remove(struct rte_pci_device *pci_dev) > if (pci_dev == NULL) > return -EINVAL; > > - /* Find device */ > + /* Find device. */ > bbdev = rte_bbdev_get_named_dev(pci_dev->device.name); > if (bbdev == NULL) { > rte_bbdev_log(CRIT, > @@ -2939,17 +2939,17 @@ fpga_5gnr_fec_remove(struct rte_pci_device *pci_dev) > } > dev_id = bbdev->data->dev_id; > > - /* free device private memory before close */ > + /* free device private memory before close. */ > rte_free(bbdev->data->dev_private); > > - /* Close device */ > + /* Close device. */ > ret = rte_bbdev_close(dev_id); > if (ret < 0) > rte_bbdev_log(ERR, > "Device %i failed to close during uninit: %i", > dev_id, ret); > > - /* release bbdev from library */ > + /* release bbdev from library. */ > ret = rte_bbdev_release(bbdev); > if (ret) > rte_bbdev_log(ERR, "Device %i failed to uninit: %i", dev_id, ret); > @@ -2962,16 +2962,16 @@ fpga_5gnr_fec_remove(struct rte_pci_device *pci_dev) > static inline void > fpga_5gnr_set_default_conf(struct rte_fpga_5gnr_fec_conf *def_conf) > { > - /* clear default configuration before initialization */ > + /* clear default configuration before initialization. */ > memset(def_conf, 0, sizeof(struct rte_fpga_5gnr_fec_conf)); > - /* Set pf mode to true */ > + /* Set pf mode to true. */ > def_conf->pf_mode_en = true; > > /* Set ratio between UL and DL to 1:1 (unit of weight is 3 CBs) */ > def_conf->ul_bandwidth = 3; > def_conf->dl_bandwidth = 3; > > - /* Set Load Balance Factor to 64 */ > + /* Set Load Balance Factor to 64. */ > def_conf->dl_load_balance = 64; > def_conf->ul_load_balance = 64; > } > @@ -3011,7 +3011,7 @@ static int vc_5gnr_configure(const char *dev_name, const struct rte_fpga_5gnr_fe > address = VC_5GNR_CONFIGURATION; > fpga_5gnr_reg_write_16(d->mmio_base, address, payload_16); > > - /* Clear all queues registers */ > + /* Clear all queues registers. */ > payload_32 = FPGA_5GNR_INVALID_HW_QUEUE_ID; > for (q_id = 0; q_id < d->total_num_queues; ++q_id) { > address = (q_id << 2) + VC_5GNR_QUEUE_MAP; > @@ -3079,7 +3079,7 @@ static int vc_5gnr_configure(const char *dev_name, const struct rte_fpga_5gnr_fe > fpga_5gnr_reg_write_32(d->mmio_base, address, payload_32); > } > } else { > - /* Calculate total number of UL and DL queues to configure */ > + /* Calculate total number of UL and DL queues to configure. */ > total_ul_q_id = total_dl_q_id = 0; > for (vf_id = 0; vf_id < FPGA_5GNR_FEC_NUM_VFS; ++vf_id) { > total_ul_q_id += conf->vf_ul_queues_number[vf_id]; > @@ -3122,17 +3122,17 @@ static int vc_5gnr_configure(const char *dev_name, const struct rte_fpga_5gnr_fe > } > } > > - /* Setting Load Balance Factor */ > + /* Setting Load Balance Factor. */ > payload_16 = (conf->dl_load_balance << 8) | (conf->ul_load_balance); > address = FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR; > fpga_5gnr_reg_write_16(d->mmio_base, address, payload_16); > > - /* Setting length of ring descriptor entry */ > + /* Setting length of ring descriptor entry. */ > payload_16 = FPGA_5GNR_RING_DESC_ENTRY_LENGTH; > address = FPGA_5GNR_FEC_RING_DESC_LEN; > fpga_5gnr_reg_write_16(d->mmio_base, address, payload_16); > > - /* Queue PF/VF mapping table is ready */ > + /* Queue PF/VF mapping table is ready. */ > payload_8 = 0x1; > address = FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE; > fpga_5gnr_reg_write_8(d->mmio_base, address, payload_8); > @@ -3145,7 +3145,7 @@ static int vc_5gnr_configure(const char *dev_name, const struct rte_fpga_5gnr_fe > return 0; > } > > -/* Initial configuration of AGX100 device */ > +/* Initial configuration of AGX100 device. */ > static int agx100_configure(const char *dev_name, const struct rte_fpga_5gnr_fec_conf *conf) > { > uint32_t payload_32, address; > @@ -3175,7 +3175,7 @@ static int agx100_configure(const char *dev_name, const struct rte_fpga_5gnr_fec > uint8_t num_ul_queues = total_num_queues >> 1; > uint8_t num_dl_queues = total_num_queues >> 1; > > - /* Clear all queues registers */ > + /* Clear all queues registers. */ > payload_32 = FPGA_5GNR_INVALID_HW_QUEUE_ID; > for (q_id = 0; q_id < total_num_queues; ++q_id) { > address = (q_id << 2) + AGX100_QUEUE_MAP; > @@ -3243,7 +3243,7 @@ static int agx100_configure(const char *dev_name, const struct rte_fpga_5gnr_fec > fpga_5gnr_reg_write_32(d->mmio_base, address, payload_32); > } > } else { > - /* Calculate total number of UL and DL queues to configure */ > + /* Calculate total number of UL and DL queues to configure. */ > total_ul_q_id = total_dl_q_id = 0; > for (vf_id = 0; vf_id < FPGA_5GNR_FEC_NUM_VFS; ++vf_id) { > total_ul_q_id += conf->vf_ul_queues_number[vf_id]; > @@ -3284,17 +3284,17 @@ static int agx100_configure(const char *dev_name, const struct rte_fpga_5gnr_fec > } > } > > - /* Setting Load Balance Factor */ > + /* Setting Load Balance Factor. */ > payload_16 = (conf->dl_load_balance << 8) | (conf->ul_load_balance); > address = FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR; > fpga_5gnr_reg_write_16(d->mmio_base, address, payload_16); > > - /* Setting length of ring descriptor entry */ > + /* Setting length of ring descriptor entry. */ > payload_16 = FPGA_5GNR_RING_DESC_ENTRY_LENGTH; > address = FPGA_5GNR_FEC_RING_DESC_LEN; > fpga_5gnr_reg_write_16(d->mmio_base, address, payload_16); > > - /* Queue PF/VF mapping table is ready */ > + /* Queue PF/VF mapping table is ready. */ > payload_8 = 0x1; > address = FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE; > fpga_5gnr_reg_write_8(d->mmio_base, address, payload_8); > @@ -3326,7 +3326,7 @@ int rte_fpga_5gnr_fec_configure(const char *dev_name, const struct rte_fpga_5gnr > return -ENODEV; > } > > -/* FPGA 5GNR FEC PCI PF address map */ > +/* FPGA 5GNR FEC PCI PF address map. */ > static struct rte_pci_id pci_id_fpga_5gnr_fec_pf_map[] = { > { > RTE_PCI_DEVICE(AGX100_VENDOR_ID, AGX100_PF_DEVICE_ID) > @@ -3344,7 +3344,7 @@ static struct rte_pci_driver fpga_5gnr_fec_pci_pf_driver = { > .drv_flags = RTE_PCI_DRV_NEED_MAPPING > }; > > -/* FPGA 5GNR FEC PCI VF address map */ > +/* FPGA 5GNR FEC PCI VF address map. */ > static struct rte_pci_id pci_id_fpga_5gnr_fec_vf_map[] = { > { > RTE_PCI_DEVICE(AGX100_VENDOR_ID, AGX100_VF_DEVICE_ID) > diff --git a/drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h b/drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h > index 894c218a5f7d..2bf87c197f54 100644 > --- a/drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h > +++ b/drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h > @@ -25,26 +25,26 @@ > extern "C" { > #endif > > -/** Number of Virtual Functions FPGA 5GNR FEC supports */ > +/** Number of Virtual Functions FPGA 5GNR FEC supports. */ > #define FPGA_5GNR_FEC_NUM_VFS 8 > > /** > * Structure to pass FPGA 5GNR FEC configuration. > */ > struct rte_fpga_5gnr_fec_conf { > - /** 1 if PF is used for dataplane, 0 for VFs */ > + /** 1 if PF is used for dataplane, 0 for VFs. */ > bool pf_mode_en; > - /** Number of UL queues per VF */ > + /** Number of UL queues per VF. */ > uint8_t vf_ul_queues_number[FPGA_5GNR_FEC_NUM_VFS]; > - /** Number of DL queues per VF */ > + /** Number of DL queues per VF. */ > uint8_t vf_dl_queues_number[FPGA_5GNR_FEC_NUM_VFS]; > - /** UL bandwidth. Needed only for VC schedule algorithm */ > + /** UL bandwidth. Needed only for VC schedule algorithm. */ > uint8_t ul_bandwidth; > - /** DL bandwidth. Needed only for VC schedule algorithm */ > + /** DL bandwidth. Needed only for VC schedule algorithm. */ > uint8_t dl_bandwidth; > - /** UL Load Balance */ > + /** UL Load Balance. */ > uint8_t ul_load_balance; > - /** DL Load Balance */ > + /** DL Load Balance. */ > uint8_t dl_load_balance; > }; >