From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id AA25DA04BC; Fri, 9 Oct 2020 05:03:05 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BE7A31BEA8; Fri, 9 Oct 2020 05:03:02 +0200 (CEST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id 06DF11BEA0 for ; Fri, 9 Oct 2020 05:03:00 +0200 (CEST) IronPort-SDR: JYIxam8ECCPrsaD+7yQcDq3IonamCW1cZwInY6+4maqelYgOAHAq15+B7X9ti86+jmXHX7KNzO Qw00SzHqGAHg== X-IronPort-AV: E=McAfee;i="6000,8403,9768"; a="162799180" X-IronPort-AV: E=Sophos;i="5.77,353,1596524400"; d="scan'208";a="162799180" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2020 20:02:58 -0700 IronPort-SDR: dOH6lTPVi+7oRyTcL+62QqBr8g3BJJK7PYRsVELH+QtjEfe7GfeCF2HgD/J9d9IuKHojEFCrmY G6kTM8WPg4Rg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,353,1596524400"; d="scan'208";a="462029674" Received: from fmsmsx603.amr.corp.intel.com ([10.18.126.83]) by orsmga004.jf.intel.com with ESMTP; 08 Oct 2020 20:02:58 -0700 Received: from shsmsx605.ccr.corp.intel.com (10.109.6.215) by fmsmsx603.amr.corp.intel.com (10.18.126.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Thu, 8 Oct 2020 20:02:57 -0700 Received: from shsmsx601.ccr.corp.intel.com (10.109.6.141) by SHSMSX605.ccr.corp.intel.com (10.109.6.215) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Fri, 9 Oct 2020 11:02:56 +0800 Received: from shsmsx601.ccr.corp.intel.com ([10.109.6.141]) by SHSMSX601.ccr.corp.intel.com ([10.109.6.141]) with mapi id 15.01.1713.004; Fri, 9 Oct 2020 11:02:56 +0800 From: "Guo, Jia" To: "Power, Ciara" , "dev@dpdk.org" CC: "Xing, Beilei" Thread-Topic: [PATCH v3 04/18] net/i40e: add checks for max SIMD bitwidth Thread-Index: AQHWlyq/s/PAY45siUqFzHD08Wiz0KmOnvgw Date: Fri, 9 Oct 2020 03:02:55 +0000 Message-ID: References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> <20200930130415.11211-5-ciara.power@intel.com> In-Reply-To: <20200930130415.11211-5-ciara.power@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v3 04/18] net/i40e: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi, power > -----Original Message----- > From: Power, Ciara > Sent: Wednesday, September 30, 2020 9:04 PM > To: dev@dpdk.org > Cc: Power, Ciara ; Xing, Beilei > ; Guo, Jia > Subject: [PATCH v3 04/18] net/i40e: add checks for max SIMD bitwidth >=20 > When choosing a vector path to take, an extra condition must be satisfied= to > ensure the max SIMD bitwidth allows for the CPU enabled path. >=20 > Cc: Beilei Xing > Cc: Jeff Guo >=20 > Signed-off-by: Ciara Power > --- > drivers/net/i40e/i40e_rxtx.c | 19 +++++++++++++------ > 1 file changed, 13 insertions(+), 6 deletions(-) >=20 > diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c = index > 60b33d20a1..9b535b52fa 100644 > --- a/drivers/net/i40e/i40e_rxtx.c > +++ b/drivers/net/i40e/i40e_rxtx.c > @@ -3098,7 +3098,8 @@ static eth_rx_burst_t i40e_get_latest_rx_vec(bool > scatter) { #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) > - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) > + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) && > + rte_get_max_simd_bitwidth() >=3D Nitpick: I think if consistent to keep alignment for open parenthesis in th= is patch set would be better. Do you think so? > RTE_MAX_256_SIMD) > return scatter ? i40e_recv_scattered_pkts_vec_avx2 : > i40e_recv_pkts_vec_avx2; > #endif > @@ -3115,7 +3116,8 @@ i40e_get_recommend_rx_vec(bool scatter) > * use of AVX2 version to later plaforms, not all those that could > * theoretically run it. > */ > - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F)) > + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) && > + rte_get_max_simd_bitwidth() >=3D > RTE_MAX_256_SIMD) > return scatter ? i40e_recv_scattered_pkts_vec_avx2 : > i40e_recv_pkts_vec_avx2; > #endif > @@ -3154,7 +3156,8 @@ i40e_set_rx_function(struct rte_eth_dev *dev) > } > } >=20 > - if (ad->rx_vec_allowed) { > + if (ad->rx_vec_allowed && rte_get_max_simd_bitwidth() > + >=3D RTE_MAX_128_SIMD) { > /* Vec Rx path */ > PMD_INIT_LOG(DEBUG, "Vector Rx path will be used on > port=3D%d.", > dev->data->port_id); > @@ -3268,7 +3271,8 @@ static eth_tx_burst_t > i40e_get_latest_tx_vec(void) > { > #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) > - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) > + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) && > + rte_get_max_simd_bitwidth() >=3D > RTE_MAX_256_SIMD) > return i40e_xmit_pkts_vec_avx2; > #endif > return i40e_xmit_pkts_vec; > @@ -3283,7 +3287,8 @@ i40e_get_recommend_tx_vec(void) > * use of AVX2 version to later plaforms, not all those that could > * theoretically run it. > */ > - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F)) > + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) && > + rte_get_max_simd_bitwidth() >=3D > RTE_MAX_256_SIMD) > return i40e_xmit_pkts_vec_avx2; > #endif > return i40e_xmit_pkts_vec; > @@ -3311,7 +3316,9 @@ i40e_set_tx_function(struct rte_eth_dev *dev) > } >=20 > if (ad->tx_simple_allowed) { > - if (ad->tx_vec_allowed) { > + if (ad->tx_vec_allowed && > + rte_get_max_simd_bitwidth() > + >=3D RTE_MAX_128_SIMD) { > PMD_INIT_LOG(DEBUG, "Vector tx finally be used."); > if (ad->use_latest_vec) > dev->tx_pkt_burst =3D > -- > 2.17.1