From mboxrd@z Thu Jan 1 00:00:00 1970
Return-Path: <dev-bounces@dpdk.org>
Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124])
by inbox.dpdk.org (Postfix) with ESMTP id 5FD2A4404F;
Wed, 12 Jun 2024 17:27:04 +0200 (CEST)
Received: from mails.dpdk.org (localhost [127.0.0.1])
by mails.dpdk.org (Postfix) with ESMTP id 6FF434331E;
Wed, 12 Jun 2024 17:07:22 +0200 (CEST)
Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10])
by mails.dpdk.org (Postfix) with ESMTP id 8545E432F4
for <dev@dpdk.org>; Wed, 12 Jun 2024 17:07:09 +0200 (CEST)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple;
d=intel.com; i=@intel.com; q=dns/txt; s=Intel;
t=1718204830; x=1749740830;
h=from:to:cc:subject:date:message-id:in-reply-to:
references:mime-version:content-transfer-encoding;
bh=HDSBJPn5m90ilf7lkwZv+iwYaUsOLmKSbGutWATrJFU=;
b=MCn9eXYHcNLg6fkB9SxBTJy+eCgH061aYm3Sa1vm+GyMjnLjztVb5qhQ
LE7hdpktPL5VBt13dYwc2bABFa0zawBfVYUCBvMPvhlYkLkjjuWVBX0If
cvmBxAR/39p8qKi2mekk6d6YS1V2O6W6jjVRGHcJ2XkjwDi5iUww4m2eB
9SgjUxgUQ+jBRJoe6iJly+LLkB7+9s112IQDpfjStgEPvUp6u2pOMj3/a
rN37F6wU5jmuIA2U40RrztftnTWe230CCJsh3yJS2f59bF0JmZmdeSf/M
x+8Htb+qg/nvfh5S4OvtZ1Kwxv5FvqtXX8m63uWQDBmdmCi9DFtSl/j9s w==;
X-CSE-ConnectionGUID: 2q+j5fm4SaqZkHJM6mDeWg==
X-CSE-MsgGUID: RDf9/klPRCKXnrqvkPgkdA==
X-IronPort-AV: E=McAfee;i="6700,10204,11101"; a="32460163"
X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="32460163"
Received: from orviesa009.jf.intel.com ([10.64.159.149])
by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;
12 Jun 2024 08:07:09 -0700
X-CSE-ConnectionGUID: Wk8SFTavTbC4sYbEfTfqrg==
X-CSE-MsgGUID: fN593lsBQZiHu8aZGe4Z1Q==
X-ExtLoop1: 1
X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="39926056"
Received: from silpixa00401119.ir.intel.com ([10.55.129.167])
by orviesa009.jf.intel.com with ESMTP; 12 Jun 2024 08:07:08 -0700
From: Anatoly Burakov <anatoly.burakov@intel.com>
To: dev@dpdk.org
Cc: Ian Stokes <ian.stokes@intel.com>,
bruce.richardson@intel.com
Subject: [PATCH v2 139/148] net/ice/base: clean up ice_lan_tx_rx
Date: Wed, 12 Jun 2024 16:02:13 +0100
Message-ID: <b12895ebb4dca8aaea85a03bb9aa417483e2fd4e.1718204529.git.anatoly.burakov@intel.com>
X-Mailer: git-send-email 2.43.0
In-Reply-To: <cover.1718204528.git.anatoly.burakov@intel.com>
References: <20240430154014.1026-1-ian.stokes@intel.com>
<cover.1718204528.git.anatoly.burakov@intel.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <https://mails.dpdk.org/options/dev>,
<mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://mails.dpdk.org/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <https://mails.dpdk.org/listinfo/dev>,
<mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org
From: Ian Stokes <ian.stokes@intel.com>
ice_lan_tx_rx currently is missing various defines and structs. These must be in
place to match sharedcode for ice devices. Add these defines which include
- TIMESYNC defines
- Doorbell CTX defines and struct
Signed-off-by: Ben Shelton <benjamin.h.shelton@intel.com
Signed-off-by: Ian Stokes <ian.stokes@intel.com>
---
drivers/net/ice/base/ice_lan_tx_rx.h | 28 ++++++++++++++++++++++++++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h
index 7be597a473..209b8e5c43 100644
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -162,7 +162,6 @@ struct ice_fltr_desc {
#define ICE_FXD_FLTR_QW1_FDID_PRI_S 25
#define ICE_FXD_FLTR_QW1_FDID_PRI_M (0x7ULL << ICE_FXD_FLTR_QW1_FDID_PRI_S)
-#define ICE_FXD_FLTR_QW1_FDID_PRI_ZERO 0x0ULL
#define ICE_FXD_FLTR_QW1_FDID_PRI_ONE 0x1ULL
#define ICE_FXD_FLTR_QW1_FDID_PRI_THREE 0x3ULL
@@ -284,6 +283,7 @@ enum ice_rx_desc_error_l3l4e_masks {
enum ice_rx_l2_ptype {
ICE_RX_PTYPE_L2_RESERVED = 0,
ICE_RX_PTYPE_L2_MAC_PAY2 = 1,
+ ICE_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
ICE_RX_PTYPE_L2_FIP_PAY2 = 3,
ICE_RX_PTYPE_L2_OUI_PAY2 = 4,
ICE_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
@@ -343,6 +343,7 @@ enum ice_rx_ptype_inner_prot {
ICE_RX_PTYPE_INNER_PROT_TCP = 2,
ICE_RX_PTYPE_INNER_PROT_SCTP = 3,
ICE_RX_PTYPE_INNER_PROT_ICMP = 4,
+ ICE_RX_PTYPE_INNER_PROT_TIMESYNC = 5,
};
enum ice_rx_ptype_payload_layer {
@@ -931,6 +932,8 @@ enum ice_rx_flex_desc_exstat_bits {
#define ICE_RXQ_CTX_SIZE_DWORDS 8
#define ICE_RXQ_CTX_SZ (ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32))
+#define ICE_TXQ_CTX_SIZE_DWORDS 10
+#define ICE_TXQ_CTX_SZ (ICE_TXQ_CTX_SIZE_DWORDS * sizeof(u32))
#define ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS 22
#define ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS 5
#define GLTCLAN_CQ_CNTX(i, CQ) (GLTCLAN_CQ_CNTX0(CQ) + ((i) * 0x0800))
@@ -1071,7 +1074,7 @@ enum ice_tx_desc_len_fields {
struct ice_tx_ctx_desc {
__le32 tunneling_params;
__le16 l2tag2;
- __le16 gsc;
+ __le16 gcs;
__le64 qw1;
};
@@ -1191,6 +1194,7 @@ struct ice_tlan_ctx {
u8 pkt_shaper_prof_idx;
u8 gsc_ena;
u8 int_q_state; /* width not needed - internal - DO NOT WRITE!!! */
+ u16 tail;
};
/* LAN Tx Completion Queue data */
@@ -1207,6 +1211,7 @@ struct ice_tx_cmpltnq {
#pragma pack(1)
struct ice_tx_cmpltnq_ctx {
u64 base;
+#define ICE_TX_CMPLTNQ_CTX_BASE_S 7
u32 q_len;
#define ICE_TX_CMPLTNQ_CTX_Q_LEN_S 4
u8 generation;
@@ -1214,6 +1219,9 @@ struct ice_tx_cmpltnq_ctx {
u8 pf_num;
u16 vmvf_num;
u8 vmvf_type;
+#define ICE_TX_CMPLTNQ_CTX_VMVF_TYPE_VF 0
+#define ICE_TX_CMPLTNQ_CTX_VMVF_TYPE_VMQ 1
+#define ICE_TX_CMPLTNQ_CTX_VMVF_TYPE_PF 2
u8 tph_desc_wr;
u8 cpuid;
u32 cmpltn_cache[16];
@@ -1228,15 +1236,30 @@ struct ice_tx_drbell_fmt {
u32 db;
};
+/* FIXME: move to a .c file that references this variable */
+/* LAN Tx Doorbell Descriptor format info */
+static const struct ice_ctx_ele ice_tx_drbell_fmt_info[] = {
+ /* Field Width LSB */
+ ICE_CTX_STORE(ice_tx_drbell_fmt, txq_id, 14, 0),
+ ICE_CTX_STORE(ice_tx_drbell_fmt, dd, 1, 14),
+ ICE_CTX_STORE(ice_tx_drbell_fmt, rs, 1, 15),
+ ICE_CTX_STORE(ice_tx_drbell_fmt, db, 32, 32),
+ { 0 }
+};
/* LAN Tx Doorbell Queue Context */
#pragma pack(1)
struct ice_tx_drbell_q_ctx {
u64 base;
+#define ICE_TX_DRBELL_Q_CTX_BASE_S 7
u16 ring_len;
+#define ICE_TX_DRBELL_Q_CTX_RING_LEN_S 4
u8 pf_num;
u16 vf_num;
u8 vmvf_type;
+#define ICE_TX_DRBELL_Q_CTX_VMVF_TYPE_VF 0
+#define ICE_TX_DRBELL_Q_CTX_VMVF_TYPE_VMQ 1
+#define ICE_TX_DRBELL_Q_CTX_VMVF_TYPE_PF 2
u8 cpuid;
u8 tph_desc_rd;
u8 tph_desc_wr;
@@ -1286,6 +1309,7 @@ struct ice_tx_drbell_q_ctx {
/* shorter macros makes the table fit but are terse */
#define ICE_RX_PTYPE_NOF ICE_RX_PTYPE_NOT_FRAG
#define ICE_RX_PTYPE_FRG ICE_RX_PTYPE_FRAG
+#define ICE_RX_PTYPE_INNER_PROT_TS ICE_RX_PTYPE_INNER_PROT_TIMESYNC
/* Lookup table mapping the 10-bit HW PTYPE to the bit field for decoding */
static const struct ice_rx_ptype_decoded ice_ptype_lkup[1024] = {
--
2.43.0