From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3BACEA0A0C; Tue, 29 Jun 2021 17:02:27 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 27159411B2; Tue, 29 Jun 2021 17:02:27 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id A16B8411A9 for ; Tue, 29 Jun 2021 17:02:25 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10029"; a="205155248" X-IronPort-AV: E=Sophos;i="5.83,309,1616482800"; d="scan'208";a="205155248" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2021 08:02:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,309,1616482800"; d="scan'208";a="558744931" Received: from fmsmsx606.amr.corp.intel.com ([10.18.126.86]) by fmsmga001.fm.intel.com with ESMTP; 29 Jun 2021 08:02:14 -0700 Received: from shsmsx603.ccr.corp.intel.com (10.109.6.143) by fmsmsx606.amr.corp.intel.com (10.18.126.86) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.4; Tue, 29 Jun 2021 08:02:13 -0700 Received: from shsmsx601.ccr.corp.intel.com (10.109.6.141) by SHSMSX603.ccr.corp.intel.com (10.109.6.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.4; Tue, 29 Jun 2021 23:02:11 +0800 Received: from shsmsx601.ccr.corp.intel.com ([10.109.6.141]) by SHSMSX601.ccr.corp.intel.com ([10.109.6.141]) with mapi id 15.01.2242.008; Tue, 29 Jun 2021 23:02:11 +0800 From: "Zhang, Qi Z" To: "Wang, Haiyue" , "dev@dpdk.org" CC: "david.marchand@redhat.com" , "Yang, Qiming" Thread-Topic: [PATCH v1] net/ice: enable to set HW debug mask Thread-Index: AQHXbO5yzpK8YqjRskS5CVi00z/0qasrFNfQ Date: Tue, 29 Jun 2021 15:02:11 +0000 Message-ID: References: <20210629133332.226897-1-haiyue.wang@intel.com> In-Reply-To: <20210629133332.226897-1-haiyue.wang@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.5.1.3 dlp-product: dlpe-windows x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v1] net/ice: enable to set HW debug mask X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Wang, Haiyue > Sent: Tuesday, June 29, 2021 9:34 PM > To: dev@dpdk.org > Cc: david.marchand@redhat.com; Wang, Haiyue ; > Yang, Qiming ; Zhang, Qi Z > Subject: [PATCH v1] net/ice: enable to set HW debug mask >=20 > The HW debug mask is always zero, so user can't enable the related debug > function like ICE_DBG_XXX etc. >=20 > Add the devarg 'hw_debug_mask' to set the function like for ICE_DBG_NVM: > -a 0000:88:00.0,hw_debug_mask=3D0x80 --log-level=3Dpmd.net.ice.driver:8 This looks good, please also update the document (ice.rst). >=20 > Signed-off-by: Haiyue Wang > --- > drivers/net/ice/ice_ethdev.c | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) >=20 > diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c = index > 09e38590e5..5a18663430 100644 > --- a/drivers/net/ice/ice_ethdev.c > +++ b/drivers/net/ice/ice_ethdev.c > @@ -26,11 +26,13 @@ > #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support" > #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support" > #define ICE_PROTO_XTR_ARG "proto_xtr" > +#define ICE_HW_DEBUG_MASK_ARG "hw_debug_mask" >=20 > static const char * const ice_valid_args[] =3D { > ICE_SAFE_MODE_SUPPORT_ARG, > ICE_PIPELINE_MODE_SUPPORT_ARG, > ICE_PROTO_XTR_ARG, > + ICE_HW_DEBUG_MASK_ARG, > NULL > }; >=20 > @@ -1836,6 +1838,25 @@ parse_bool(const char *key, const char *value, > void *args) > return 0; > } >=20 > +static int > +parse_u64(const char *key, const char *value, void *args) { > + u64 *num =3D (u64 *)args; > + u64 tmp; > + > + errno =3D 0; > + tmp =3D strtoull(value, NULL, 16); > + if (errno) { > + PMD_DRV_LOG(WARNING, "%s: \"%s\" is not a valid u64", > + key, value); > + return -1; > + } > + > + *num =3D tmp; > + > + return 0; > +} > + > static int ice_parse_devargs(struct rte_eth_dev *dev) { > struct ice_adapter *ad =3D > @@ -1872,6 +1893,11 @@ static int ice_parse_devargs(struct rte_eth_dev > *dev) > if (ret) > goto bail; >=20 > + ret =3D rte_kvargs_process(kvlist, ICE_HW_DEBUG_MASK_ARG, > + &parse_u64, &ad->hw.debug_mask); > + if (ret) > + goto bail; > + > bail: > rte_kvargs_free(kvlist); > return ret; > @@ -5306,6 +5332,7 @@ RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd); > RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map); > RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | > vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(net_ice, > + ICE_HW_DEBUG_MASK_ARG "=3D0xXXX" > ICE_PROTO_XTR_ARG > "=3D[queue:]" > ICE_SAFE_MODE_SUPPORT_ARG "=3D<0|1>" > ICE_PIPELINE_MODE_SUPPORT_ARG "=3D<0|1>"); > -- > 2.32.0