From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 763212B9A for ; Fri, 23 Dec 2016 16:39:31 +0100 (CET) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga102.fm.intel.com with ESMTP; 23 Dec 2016 07:39:30 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,393,1477983600"; d="scan'208";a="1075642558" Received: from fyigit-mobl1.ger.corp.intel.com (HELO [10.237.220.29]) ([10.237.220.29]) by orsmga001.jf.intel.com with ESMTP; 23 Dec 2016 07:39:29 -0800 To: Rasesh Mody , dev@dpdk.org References: <1480756289-11835-1-git-send-email-Rasesh.Mody@cavium.com> <1480756289-11835-21-git-send-email-Rasesh.Mody@cavium.com> Cc: Dept-EngDPDKDev@cavium.com From: Ferruh Yigit Message-ID: Date: Fri, 23 Dec 2016 15:39:28 +0000 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: <1480756289-11835-21-git-send-email-Rasesh.Mody@cavium.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [dpdk-dev] [PATCH 20/25] net/qede: add PCI ids for new chip variant X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 23 Dec 2016 15:39:31 -0000 On 12/3/2016 9:11 AM, Rasesh Mody wrote: > Add PCI IDs for new asic type (defined as CHIP_NUM_AH_xxx). > It supports 50G, 40G, 25G and 10G speeds. > > Signed-off-by: Rasesh Mody > --- > drivers/net/qede/base/ecore_dev.c | 7 +++++- > drivers/net/qede/qede_ethdev.c | 29 ++++++++++++++++++------ > drivers/net/qede/qede_ethdev.h | 47 ++++++++++++++++++++++++--------------- > 3 files changed, 57 insertions(+), 26 deletions(-) > > diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c > index 5a29c45b..03620d94 100644 > --- a/drivers/net/qede/base/ecore_dev.c > +++ b/drivers/net/qede/base/ecore_dev.c > @@ -2365,7 +2365,12 @@ static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn, > #endif > > for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) { > - rc = ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc); > + /* @@@TMP for AH: > + * Force the driver's default resource allocation in case there > + * is a diff with the MFW allocation value. > + */ > + rc = ecore_hw_set_resc_info(p_hwfn, res_id, > + b_ah || drv_resc_alloc); Just to double check, is above code piece is related to the "add PCI ids for new chip variant" ? > if (rc != ECORE_SUCCESS) > return rc; > } <...>