From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E801EA0A0A; Thu, 6 May 2021 04:06:32 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 70E7D410DB; Thu, 6 May 2021 04:06:32 +0200 (CEST) Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by mails.dpdk.org (Postfix) with ESMTP id BF85440040 for ; Thu, 6 May 2021 04:06:30 +0200 (CEST) Received: from dggeme765-chm.china.huawei.com (unknown [172.30.72.53]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4FbH1h2hcnz5vYC; Thu, 6 May 2021 10:03:52 +0800 (CST) Received: from [127.0.0.1] (10.69.27.114) by dggeme765-chm.china.huawei.com (10.3.19.111) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Thu, 6 May 2021 10:06:26 +0800 To: Thomas Monjalon , "Min Hu (Connor)" References: <1618470748-12369-1-git-send-email-humin29@huawei.com> <1986861.sBpPVbSSCl@thomas> CC: , , , From: Chengchang Tang Message-ID: Date: Thu, 6 May 2021 10:06:26 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.7.1 MIME-Version: 1.0 In-Reply-To: <1986861.sBpPVbSSCl@thomas> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.69.27.114] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggeme765-chm.china.huawei.com (10.3.19.111) X-CFilter-Loop: Reflected Subject: Re: [dpdk-dev] [PATCH] examples/timer: fix incorrect time interval X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 2021/5/6 5:37, Thomas Monjalon wrote: > 15/04/2021 09:12, Min Hu (Connor): >> From: Chengchang Tang >> >> Timer sample example assumes that the frequency of the timer is about >> 2Ghz to control the period of calling rte_timer_manage(). But this >> assumption is easy to fail. For example. the frequency of tsc on ARM64 >> is much less than 2Ghz. >> >> This patch uses the frequency of the current timer to calculate the >> correct time interval to ensure consistent result on all platforms. >> >> In addition, the rte_rdtsc() is replaced with the more recommended >> rte_get_timer_cycles function in this patch. >> >> Fixes: af75078fece3 ("first public release") >> Cc: stable@dpdk.org >> >> Signed-off-by: Chengchang Tang >> Signed-off-by: Min Hu (Connor) > [...] >> /* >> - * Call the timer handler on each core: as we don't >> - * need a very precise timer, so only call >> - * rte_timer_manage() every ~10ms (at 2Ghz). In a real >> - * application, this will enhance performances as >> - * reading the HPET timer is not efficient. >> + * Call the timer handler on each core: as we don't need a >> + * very precise timer, so only call rte_timer_manage() >> + * every ~10ms. since rte_eal_hpet_init() has not been >> + * called, the rte_rdtsc() will be used at runtime. > > I don't understand this last sentence. > This is explaining why we can use rte_get_timer_cycles() instead of rte_rdtsc(). In this example, we call tsc to improve its performance. So, we invoked rte_rdtsc() here. Now the function rte_get_timer_cycles() encapsulates these counters. It will invoke the corresponding counter according to the user's initialization of the counter. >> + * In a real application, this will enhance performances >> + * as reading the HPET timer is not efficient. >> */ >> - cur_tsc = rte_rdtsc(); >> + cur_tsc = rte_get_timer_cycles(); > > > > > . >