From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf0-f178.google.com (mail-pf0-f178.google.com [209.85.192.178]) by dpdk.org (Postfix) with ESMTP id 7A3D81B27E for ; Tue, 31 Oct 2017 03:55:29 +0100 (CET) Received: by mail-pf0-f178.google.com with SMTP id n89so12611058pfk.11 for ; Mon, 30 Oct 2017 19:55:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-transfer-encoding; bh=sDPsf5Ewxg4J49RcJDy39uW0x0I/Oyyb9BZmLWqXXVg=; b=WZPwpxgV1OMxqsC9RLm91s9PMULjNg2qSTcXUxWs5hKjc7lBc8fcVitJWptLfY07DY kVCEcQpgTFTBdHHIkmsisv2rOBnZUhkDi7sPsRXyS36n+5HzF+Y3tYz8aP2j69pzyRTP f/P+hRpK3nzUyLHHjv8tkBkExdnLucQu/GBHa5aI8Vc0ERyRc6Z99ZCxVYNhhFO7O/8k X4jXERUWPK4jSJr7mLTnYSJwIc6xIbtNkA0q4BXA6BgSevFpxz6BQqjPSuSb6N2nv/26 y3rEt3WBkUJuYjJh/lx8DAK5W9r8qTJLsZXPYNmnUos9HLVy9TzUCESy6+5ZhnsvIMYu pIfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-transfer-encoding; bh=sDPsf5Ewxg4J49RcJDy39uW0x0I/Oyyb9BZmLWqXXVg=; b=Io9VJ0suB7lqSp6/+qldmcG2T+LExATJLZBPVrSyrzrVIr7eH31Tl5Ofq1Gd7YsOuS koUtG7wEw7wckpC3BzW/kqOqr5fSZiMvs58wt+okoUKcSfdlI/qh02TuzpApe935i6sR IJvCXKLJNiHmrAN+iyxfJVgN2kgIS8ExRNAWH15hf+bNPc6HOBxcQnTOfdSkow2OrSny d+q1JjAzwfwClL0ZFrhB1gCEhTFGrKaogDqpSexXsy/MfmoELbpU43baMRI3XSmRQvFZ ioImXNB6r32HoGJxSgiO3u5MjrtSeJHHwNDhCCdynHSc59TwL6tc4aNHEijgN0KOzW7N BKpw== X-Gm-Message-State: AMCzsaXqCkqHsIssdVEwR9eOcqDBl5itSr68yU7084Jx059TmDR5swg8 49cijaSRk0tleF5whPDwNa4= X-Google-Smtp-Source: ABhQp+T1Mm2SuJxgWh08SXQ0tv2M6U5DegO0yaCkqT4KqlEiAz3+hyXozjT1eJWLWFD0+64vY6Np1A== X-Received: by 10.98.133.28 with SMTP id u28mr479561pfd.241.1509418528599; Mon, 30 Oct 2017 19:55:28 -0700 (PDT) Received: from [0.0.0.0] (67.209.179.165.16clouds.com. [67.209.179.165]) by smtp.gmail.com with ESMTPSA id g1sm454733pfg.111.2017.10.30.19.55.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 30 Oct 2017 19:55:27 -0700 (PDT) To: Jerin Jacob Cc: "Ananyev, Konstantin" , "Zhao, Bing" , Olivier MATZ , "dev@dpdk.org" , "jia.he@hxt-semitech.com" , "jie2.liu@hxt-semitech.com" , "bing.zhao@hxt-semitech.com" , "Richardson, Bruce" References: <2601191342CEEE43887BDE71AB9772585FAAB171@IRSMSX103.ger.corp.intel.com> <8806e2bd-c57b-03ff-a315-0a311690f1d9@163.com> <2601191342CEEE43887BDE71AB9772585FAAB404@IRSMSX103.ger.corp.intel.com> <2601191342CEEE43887BDE71AB9772585FAAB570@IRSMSX103.ger.corp.intel.com> <3e580cd7-2854-d855-be9c-7c4ce06e3ed5@gmail.com> <20171020054319.GA4249@jerin> <20171023100617.GA17957@jerin> <20171025132642.GA13977@jerin> From: Jia He Message-ID: Date: Tue, 31 Oct 2017 10:55:15 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.4.0 MIME-Version: 1.0 In-Reply-To: <20171025132642.GA13977@jerin> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH] ring: guarantee ordering of cons/prod loading when doing enqueue/dequeue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Oct 2017 02:55:29 -0000 Hi Jerin Do you think  next step whether I need to implement the load_acquire half barrier as per freebsd or find any other performance test case to compare the performance impact? Thanks for any suggestions. Cheers, Jia On 10/25/2017 9:26 PM, Jerin Jacob Wrote: > -----Original Message----- >> Date: Tue, 24 Oct 2017 10:04:26 +0800 >> From: Jia He >> To: Jerin Jacob >> Cc: "Ananyev, Konstantin" , "Zhao, Bing" >> , Olivier MATZ , >> "dev@dpdk.org" , "jia.he@hxt-semitech.com" >> , "jie2.liu@hxt-semitech.com" >> , "bing.zhao@hxt-semitech.com" >> , "Richardson, Bruce" >> >> Subject: Re: [dpdk-dev] [PATCH] ring: guarantee ordering of cons/prod >> loading when doing enqueue/dequeue >> User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 >> Thunderbird/52.4.0 >> >> Hi Jerin > Hi Jia, > > >>> example: >>> ./build/app/test -c 0xff -n 4 >>>>> ring_perf_autotest >> Seem in our arm64 server, the ring_perf_autotest will be finished in a few >> seconds: > Yes. It just need a few seconds. > >> Anything wrong about configuration or environment setup? > By default, arm64+dpdk will be using el0 counter to measure the cycles. I > think, in your SoC, it will be running at 50MHz or 100MHz.So, You can > follow the below scheme to get accurate cycle measurement scheme: > > See: http://dpdk.org/doc/guides/prog_guide/profile_app.html > check: 44.2.2. High-resolution cycle counter > >> root@ubuntu:/home/hj/dpdk/build/build/test/test# ./test -c 0xff -n 4 >> EAL: Detected 44 lcore(s) >> EAL: Probing VFIO support... >> APP: HPET is not enabled, using TSC as default timer >> RTE>>per_lcore_autotest >> RTE>>ring_perf_autotest >> ### Testing single element and burst enq/deq ### >> SP/SC single enq/dequeue: 0 >> MP/MC single enq/dequeue: 2 >> SP/SC burst enq/dequeue (size: 8): 0 > If you follow the above link, The value '0' will be replaced with more meaning full data. > >> MP/MC burst enq/dequeue (size: 8): 0 >> SP/SC burst enq/dequeue (size: 32): 0 >> MP/MC burst enq/dequeue (size: 32): 0 >> >> ### Testing empty dequeue ### >> SC empty dequeue: 0.02 >> MC empty dequeue: 0.04 >> >> ### Testing using a single lcore ### >> SP/SC bulk enq/dequeue (size: 8): 0.12 >> MP/MC bulk enq/dequeue (size: 8): 0.31 >> SP/SC bulk enq/dequeue (size: 32): 0.05 >> MP/MC bulk enq/dequeue (size: 32): 0.09 >> >> ### Testing using two hyperthreads ### >> SP/SC bulk enq/dequeue (size: 8): 0.12 >> MP/MC bulk enq/dequeue (size: 8): 0.39 >> SP/SC bulk enq/dequeue (size: 32): 0.04 >> MP/MC bulk enq/dequeue (size: 32): 0.12 >> >> ### Testing using two physical cores ### >> SP/SC bulk enq/dequeue (size: 8): 0.37 >> MP/MC bulk enq/dequeue (size: 8): 0.92 >> SP/SC bulk enq/dequeue (size: 32): 0.12 >> MP/MC bulk enq/dequeue (size: 32): 0.26 >> Test OK >> RTE>> >> >> Cheers, >> Jia >>> By default, arm64+dpdk will be using el0 counter to measure the cycles. I >>> think, in your SoC, it will be running at 50MHz or 100MHz.So, You can >>> follow the below scheme to get accurate cycle measurement scheme: >>> >>> See: http://dpdk.org/doc/guides/prog_guide/profile_app.html >>> check: 44.2.2. High-resolution cycle counter -- Cheers, Jia