From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0A4BCA052A; Tue, 26 Jan 2021 16:32:08 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EA02C140FB3; Tue, 26 Jan 2021 16:32:07 +0100 (CET) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 6FF16140F8C for ; Tue, 26 Jan 2021 16:32:06 +0100 (CET) IronPort-SDR: O515Ph3vARoSwMwKEQKN5VXXj0j57zi53GSe4zZnMWi4I3WnJkrrKBj6/Ek5Ux/lnSFavgWOao 22x/BDkaQK4g== X-IronPort-AV: E=McAfee;i="6000,8403,9876"; a="264740756" X-IronPort-AV: E=Sophos;i="5.79,375,1602572400"; d="scan'208";a="264740756" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2021 07:32:05 -0800 IronPort-SDR: 7j+P/B2sZtBck/4+6qKp6dMXi3vQrfC6XSj5ax9Dde+KEeoff4MzU5pkdJGXQV1SVmxS/C0OWe fbK/D7wlUPfg== X-IronPort-AV: E=Sophos;i="5.79,375,1602572400"; d="scan'208";a="362022430" Received: from fyigit-mobl1.ger.corp.intel.com (HELO [10.213.227.53]) ([10.213.227.53]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2021 07:32:04 -0800 To: Nalla Pradeep , Radha Mohan Chintakuntla , Veerasenareddy Burru Cc: jerinj@marvell.com, dev@dpdk.org, sburla@marvell.com References: <20210118093602.5449-1-pnalla@marvell.com> <20210118093602.5449-8-pnalla@marvell.com> From: Ferruh Yigit Message-ID: Date: Tue, 26 Jan 2021 15:32:03 +0000 MIME-Version: 1.0 In-Reply-To: <20210118093602.5449-8-pnalla@marvell.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH v2 08/11] net/octeontx_ep: Setting up iq and oq registers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 1/18/2021 9:35 AM, Nalla Pradeep wrote: > Configuring hardware registers with command queue(iq) and droq(oq) > parameters. > Can you please elaborate what functionalit is configured, registers setup is not clear on its own? > Signed-off-by: Nalla Pradeep <...> > +static void > +otx2_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no) > +{ > + volatile uint64_t reg_val = 0ull; > + uint64_t oq_ctl = 0ull; > + struct otx_ep_droq *droq = otx_ep->droq[oq_no]; > + > + /* Wait on IDLE to set to 1, supposed to configure BADDR > + * as log as IDLE is 0 > + */ > + reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no)); > + > + while (!(reg_val & SDP_VF_R_OUT_CTL_IDLE)) { > + reg_val = otx2_read64(otx_ep->hw_addr + > + SDP_VF_R_OUT_CONTROL(oq_no)); > + } > + > + otx2_write64(droq->desc_ring_dma, otx_ep->hw_addr + > + SDP_VF_R_OUT_SLIST_BADDR(oq_no)); > + otx2_write64(droq->nb_desc, otx_ep->hw_addr + > + SDP_VF_R_OUT_SLIST_RSIZE(oq_no)); > + > + oq_ctl = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no)); > + > + /* Clear the ISIZE and BSIZE (22-0) */ > + oq_ctl &= ~(0x7fffffull); > + > + /* Populate the BSIZE (15-0) */ > + oq_ctl |= (droq->buffer_size & 0xffff); > + > +#ifndef BUFPTR_ONLY_MODE > + /* Populate ISIZE(22-16) */ > + oq_ctl |= ((OTX_EP_RH_SIZE << 16) & 0x7fffff); > +#endif > + otx2_write64(oq_ctl, otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no)); > + > + /* Mapped address of the pkt_sent and pkts_credit regs */ > + droq->pkts_sent_reg = (uint8_t *)otx_ep->hw_addr + > + SDP_VF_R_OUT_CNTS(oq_no); > + droq->pkts_credit_reg = (uint8_t *)otx_ep->hw_addr + > + SDP_VF_R_OUT_SLIST_DBELL(oq_no); > + > + rte_write64(0x3FFFFFFFFFFFFFUL, > + otx_ep->hw_addr + SDP_VF_R_OUT_INT_LEVELS(oq_no)); > + > + /* Clear PKT_CNT register */ > + rte_write64(0xFFFFFFFFF, (uint8_t *)otx_ep->hw_addr + > + SDP_VF_R_OUT_PKT_CNT(oq_no)); > + > + /* Clear the OQ doorbell */ > + rte_write32(0xFFFFFFFF, droq->pkts_credit_reg); > + while ((rte_read32(droq->pkts_credit_reg) != 0ull)) { > + rte_write32(0xFFFFFFFF, droq->pkts_credit_reg); > + rte_delay_ms(1); There are multiple hardcoded values in this function, better to convert to defines as much as possible. <...> > @@ -4,13 +4,38 @@ > #ifndef _OTX_EP_VF_H_ > #define _OTX_EP_VF_H_ > > + > + > + > + extra space?