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To: Nalla Pradeep <pnalla@marvell.com>,
Radha Mohan Chintakuntla <radhac@marvell.com>,
Veerasenareddy Burru <vburru@marvell.com>
Cc: jerinj@marvell.com, dev@dpdk.org, sburla@marvell.com
References: <20210118093602.5449-1-pnalla@marvell.com>
<20210118093602.5449-8-pnalla@marvell.com>
From: Ferruh Yigit <ferruh.yigit@intel.com>
Message-ID: <b6d02564-1d7e-5e05-fe2e-0e9bcd8d1000@intel.com>
Date: Tue, 26 Jan 2021 15:32:03 +0000
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Subject: Re: [dpdk-dev] [PATCH v2 08/11] net/octeontx_ep: Setting up iq and
oq registers
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On 1/18/2021 9:35 AM, Nalla Pradeep wrote:
> Configuring hardware registers with command queue(iq) and droq(oq)
> parameters.
>
Can you please elaborate what functionalit is configured, registers setup is not
clear on its own?
> Signed-off-by: Nalla Pradeep <pnalla@marvell.com>
<...>
> +static void
> +otx2_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)
> +{
> + volatile uint64_t reg_val = 0ull;
> + uint64_t oq_ctl = 0ull;
> + struct otx_ep_droq *droq = otx_ep->droq[oq_no];
> +
> + /* Wait on IDLE to set to 1, supposed to configure BADDR
> + * as log as IDLE is 0
> + */
> + reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no));
> +
> + while (!(reg_val & SDP_VF_R_OUT_CTL_IDLE)) {
> + reg_val = otx2_read64(otx_ep->hw_addr +
> + SDP_VF_R_OUT_CONTROL(oq_no));
> + }
> +
> + otx2_write64(droq->desc_ring_dma, otx_ep->hw_addr +
> + SDP_VF_R_OUT_SLIST_BADDR(oq_no));
> + otx2_write64(droq->nb_desc, otx_ep->hw_addr +
> + SDP_VF_R_OUT_SLIST_RSIZE(oq_no));
> +
> + oq_ctl = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no));
> +
> + /* Clear the ISIZE and BSIZE (22-0) */
> + oq_ctl &= ~(0x7fffffull);
> +
> + /* Populate the BSIZE (15-0) */
> + oq_ctl |= (droq->buffer_size & 0xffff);
> +
> +#ifndef BUFPTR_ONLY_MODE
> + /* Populate ISIZE(22-16) */
> + oq_ctl |= ((OTX_EP_RH_SIZE << 16) & 0x7fffff);
> +#endif
> + otx2_write64(oq_ctl, otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no));
> +
> + /* Mapped address of the pkt_sent and pkts_credit regs */
> + droq->pkts_sent_reg = (uint8_t *)otx_ep->hw_addr +
> + SDP_VF_R_OUT_CNTS(oq_no);
> + droq->pkts_credit_reg = (uint8_t *)otx_ep->hw_addr +
> + SDP_VF_R_OUT_SLIST_DBELL(oq_no);
> +
> + rte_write64(0x3FFFFFFFFFFFFFUL,
> + otx_ep->hw_addr + SDP_VF_R_OUT_INT_LEVELS(oq_no));
> +
> + /* Clear PKT_CNT register */
> + rte_write64(0xFFFFFFFFF, (uint8_t *)otx_ep->hw_addr +
> + SDP_VF_R_OUT_PKT_CNT(oq_no));
> +
> + /* Clear the OQ doorbell */
> + rte_write32(0xFFFFFFFF, droq->pkts_credit_reg);
> + while ((rte_read32(droq->pkts_credit_reg) != 0ull)) {
> + rte_write32(0xFFFFFFFF, droq->pkts_credit_reg);
> + rte_delay_ms(1);
There are multiple hardcoded values in this function, better to convert to
defines as much as possible.
<...>
> @@ -4,13 +4,38 @@
> #ifndef _OTX_EP_VF_H_
> #define _OTX_EP_VF_H_
>
> +
> +
> +
> +
extra space?