From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id A0AA3A04DE; Fri, 23 Oct 2020 09:07:26 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id AED386CBF; Fri, 23 Oct 2020 09:07:24 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 4F22C6C98; Fri, 23 Oct 2020 09:07:21 +0200 (CEST) IronPort-SDR: H4R0VV0skFeVhbUKry7pidhz0VeGElVqFiBQSr90yM34tTL72vzI/9O9ZclPdXbWQnOLX7SMt4 YqBIdKxAhIBw== X-IronPort-AV: E=McAfee;i="6000,8403,9782"; a="185333807" X-IronPort-AV: E=Sophos;i="5.77,407,1596524400"; d="scan'208";a="185333807" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2020 00:07:11 -0700 IronPort-SDR: VuQKQEoZlwQPY95keXGAhBAZGbTFeoVpnqQbVVi4pN85gEr7UQQSR9qaQSZA2akcCmxxsNu1jh x68ryHZG0SNg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,407,1596524400"; d="scan'208";a="316996975" Received: from fmsmsx602.amr.corp.intel.com ([10.18.126.82]) by orsmga003.jf.intel.com with ESMTP; 23 Oct 2020 00:07:09 -0700 Received: from shsmsx606.ccr.corp.intel.com (10.109.6.216) by fmsmsx602.amr.corp.intel.com (10.18.126.82) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Fri, 23 Oct 2020 00:07:07 -0700 Received: from shsmsx601.ccr.corp.intel.com (10.109.6.141) by SHSMSX606.ccr.corp.intel.com (10.109.6.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Fri, 23 Oct 2020 15:07:05 +0800 Received: from shsmsx601.ccr.corp.intel.com ([10.109.6.141]) by SHSMSX601.ccr.corp.intel.com ([10.109.6.141]) with mapi id 15.01.1713.004; Fri, 23 Oct 2020 15:07:05 +0800 From: "Guo, Jia" To: "Xing, Beilei" , "dev@dpdk.org" CC: "stable@dpdk.org" Thread-Topic: [PATCH] net/i40e: fix FDIR issue for ETH + VLAN pattern Thread-Index: AQHWqEw1yWhQm5Bes02Jhj06cXvuP6mkxAgw Date: Fri, 23 Oct 2020 07:07:05 +0000 Message-ID: References: <20201023081509.13087-1-beilei.xing@intel.com> In-Reply-To: <20201023081509.13087-1-beilei.xing@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] net/i40e: fix FDIR issue for ETH + VLAN pattern X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Xing, Beilei > Sent: Friday, October 23, 2020 4:15 PM > To: dev@dpdk.org > Cc: Guo, Jia ; Xing, Beilei ; > stable@dpdk.org > Subject: [PATCH] net/i40e: fix FDIR issue for ETH + VLAN pattern >=20 > From: Beilei Xing >=20 > Currently, can't create more than one following flow for ETH + VLAN patte= rn: >=20 > > flow create 0 ingress pattern eth / vlan vid is 350 / end > actions queue index 2 / end >=20 > The root cause is the keys of all such flows are the same. >=20 Create more same flow or different flow? Why the same key relate with below= code change. Suggest better to make it more clear for readable. Thanks. > Fixes: 42044b69c67d ("net/i40e: support input set selection for FDIR") > Cc: stable@dpdk.org >=20 > Signed-off-by: Beilei Xing > --- > drivers/net/i40e/i40e_flow.c | 23 ++++++++++++++++++----- > 1 file changed, 18 insertions(+), 5 deletions(-) >=20 > diff --git a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.c > index adc5da1c53..60043322a1 100644 > --- a/drivers/net/i40e/i40e_flow.c > +++ b/drivers/net/i40e/i40e_flow.c > @@ -28,6 +28,9 @@ > #define I40E_IPV6_FRAG_HEADER 44 > #define I40E_TENANT_ARRAY_NUM 3 > #define I40E_TCI_MASK 0xFFFF > +#define I40E_PRI_MASK 0xE000 > +#define I40E_CFI_MASK 0x1000 > +#define I40E_VID_MASK 0x0FFF >=20 Should below are better to show that tci involve the others when use these = mask? +#define I40E_TCI_PRI_MASK 0xE000 +#define I40E_TCI_CFI_MASK 0x1000 +#define I40E_TCI_VID_MASK 0x0FFF > static int i40e_flow_validate(struct rte_eth_dev *dev, > const struct rte_flow_attr *attr, @@ -2705,12 > +2708,22 @@ i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev, >=20 > RTE_ASSERT(!(input_set & > I40E_INSET_LAST_ETHER_TYPE)); > if (vlan_spec && vlan_mask) { > - if (vlan_mask->tci =3D=3D > - rte_cpu_to_be_16(I40E_TCI_MASK)) { > - input_set |=3D > I40E_INSET_VLAN_INNER; > - filter->input.flow_ext.vlan_tci =3D > - vlan_spec->tci; > + if (vlan_mask->tci !=3D > + rte_cpu_to_be_16(I40E_TCI_MASK) && > + vlan_mask->tci !=3D > + rte_cpu_to_be_16(I40E_PRI_MASK) && > + vlan_mask->tci !=3D > + rte_cpu_to_be_16(I40E_CFI_MASK) && > + vlan_mask->tci !=3D > + rte_cpu_to_be_16(I40E_VID_MASK)) { > + rte_flow_error_set(error, EINVAL, > + > RTE_FLOW_ERROR_TYPE_ITEM, > + item, > + "Unsupported TCI mask."); > } > + input_set |=3D I40E_INSET_VLAN_INNER; > + filter->input.flow_ext.vlan_tci =3D > + vlan_spec->tci; > } > if (vlan_spec && vlan_mask && vlan_mask- > >inner_type) { > if (vlan_mask->inner_type !=3D > RTE_BE16(0xffff)) { > -- > 2.26.2