[PATCH v4 097/103] net/ice/base: add missing defines and misc cleanup

[Anatoly Burakov <anatoly.burakov@intel.com>]

From: Ian Stokes <ian.stokes@intel.com>

Add various missing defines and definitions that are currently not present in
DPDK but are present in upstream code.

Signed-off-by: Ian Stokes <ian.stokes@intel.com>
Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
---
 drivers/net/ice/base/ice_adminq_cmd.h | 84 +++++++++++++++------------
 drivers/net/ice/base/ice_lan_tx_rx.h  | 28 ++++++++-
 drivers/net/ice/base/ice_type.h       | 30 ++++++++++
 3 files changed, 103 insertions(+), 39 deletions(-)

diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index 96ba19f94a..daa5dedb41 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -109,7 +109,6 @@ struct ice_aqc_list_caps {
 struct ice_aqc_list_caps_elem {
 	__le16 cap;
 #define ICE_AQC_CAPS_VALID_FUNCTIONS			0x0005
-#define ICE_AQC_MAX_VALID_FUNCTIONS			0x8
 #define ICE_AQC_CAPS_VSI				0x0017
 #define ICE_AQC_CAPS_DCB				0x0018
 #define ICE_AQC_CAPS_RSS				0x0040
@@ -132,6 +131,8 @@ struct ice_aqc_list_caps_elem {
 #define ICE_AQC_CAPS_NAC_TOPOLOGY			0x0087
 #define ICE_AQC_CAPS_OROM_RECOVERY_UPDATE		0x0090
 #define ICE_AQC_CAPS_ROCEV2_LAG				0x0092
+#define ICE_AQC_BIT_ROCEV2_LAG				0x01
+#define ICE_AQC_BIT_SRIOV_LAG				0x02
 #define ICE_AQC_CAPS_NEXT_CLUSTER_ID			0x0096
 	u8 major_ver;
 	u8 minor_ver;
@@ -493,6 +494,7 @@ struct ice_aqc_vsi_props {
 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S	0
 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M	(0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA	BIT(0)
+#define ICE_AQ_VSI_SW_FLAG_RX_PASS_PRUNE_ENA	BIT(3)
 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA		BIT(4)
 	u8 veb_stat_id;
 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S		0
@@ -891,6 +893,8 @@ struct ice_sw_rule_lkup_rx_tx {
 #define ICE_SINGLE_ACT_PTR		0x2
 #define ICE_SINGLE_ACT_PTR_VAL_S	4
 #define ICE_SINGLE_ACT_PTR_VAL_M	(0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
+	/* Bit 17 should be set if pointed action includes a FWD cmd */
+#define ICE_SINGLE_ACT_PTR_HAS_FWD	BIT(17)
 	/* Bit 18 should be set to 1 */
 #define ICE_SINGLE_ACT_PTR_BIT		BIT(18)
 
@@ -1001,25 +1005,6 @@ struct ice_sw_rule_vsi_list {
 };
 #pragma pack()
 
-#pragma pack(1)
-/* Query VSI list command/response entry */
-struct ice_sw_rule_vsi_list_query {
-	__le16 index;
-	u8 vsi_list[DIVIDE_AND_ROUND_UP(ICE_MAX_VSI, BITS_PER_BYTE)];
-};
-#pragma pack()
-
-/* PFC Ignore (direct 0x0301)
- * The command and response use the same descriptor structure
- */
-struct ice_aqc_pfc_ignore {
-	u8	tc_bitmap;
-	u8	cmd_flags; /* unused in response */
-#define ICE_AQC_PFC_IGNORE_SET		BIT(7)
-#define ICE_AQC_PFC_IGNORE_CLEAR	0
-	u8	reserved[14];
-};
-
 /* Query PFC Mode (direct 0x0302)
  * Set PFC Mode (direct 0x0303)
  */
@@ -1034,17 +1019,6 @@ struct ice_aqc_set_query_pfc_mode {
 	u8	rsvd[15];
 };
 
-/* Set DCB Parameters (direct 0x0306) */
-struct ice_aqc_set_dcb_params {
-	u8 cmd_flags; /* unused in response */
-#define ICE_AQC_LINK_UP_DCB_CFG    BIT(0)
-#define ICE_AQC_PERSIST_DCB_CFG    BIT(1)
-	u8 valid_flags; /* unused in response */
-#define ICE_AQC_LINK_UP_DCB_CFG_VALID    BIT(0)
-#define ICE_AQC_PERSIST_DCB_CFG_VALID    BIT(1)
-	u8 rsvd[14];
-};
-
 /* Get Default Topology (indirect 0x0400) */
 struct ice_aqc_get_topo {
 	u8 port_num;
@@ -1708,6 +1682,7 @@ struct ice_aqc_set_event_mask {
 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED	BIT(9)
 #define ICE_AQ_LINK_EVENT_TOPO_CONFLICT		BIT(10)
 #define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT	BIT(11)
+#define ICE_AQ_LINK_EVENT_PHY_FW_LOAD_FAIL	BIT(12)
 	u8	reserved1[6];
 };
 
@@ -2048,10 +2023,17 @@ struct ice_aqc_nvm {
 #define ICE_AQC_NVM_REVERT_LAST_ACTIV	BIT(6) /* Write Activate only */
 #define ICE_AQC_NVM_ACTIV_SEL_MASK	MAKEMASK(0x7, 3)
 #define ICE_AQC_NVM_FLASH_ONLY		BIT(7)
-#define ICE_AQC_NVM_POR_FLAG	0	/* Used by NVM Write completion on ARQ */
-#define ICE_AQC_NVM_PERST_FLAG	1
-#define ICE_AQC_NVM_EMPR_FLAG	2
-#define ICE_AQC_NVM_EMPR_ENA		BIT(0)
+#define ICE_AQC_NVM_RESET_LVL_M		MAKEMASK(0x3, 0) /* Write reply only */
+#define ICE_AQC_NVM_POR_FLAG		0
+#define ICE_AQC_NVM_PERST_FLAG		1
+#define ICE_AQC_NVM_EMPR_FLAG		2
+#define ICE_AQC_NVM_EMPR_ENA		BIT(0) /* Write Activate reply only */
+	/* For Write Activate, several flags are sent as part of a separate
+	 * flags2 field using a separate byte. For simplicity of the software
+	 * interface, we pass the flags as a 16 bit value so these flags are
+	 * all offset by 8 bits
+	 */
+#define ICE_AQC_NVM_ACTIV_REQ_EMPR	BIT(8) /* NVM Write Activate only */
 	__le16 module_typeid;
 	__le16 length;
 #define ICE_AQC_NVM_ERASE_LEN	0xFFFF
@@ -2104,6 +2086,7 @@ struct ice_aqc_nvm {
 					     ICE_AQC_NVM_SDP_CFG_SDP_NUM_OFFSET)
 #define ICE_AQC_NVM_SDP_CFG_NA_PIN_MASK		MAKEMASK(0x1, 15)
 
+#define ICE_AQC_NVM_MINSREV_MOD_ID		0x130
 #define ICE_AQC_NVM_TX_TOPO_MOD_ID		0x14B
 #define ICE_AQC_NVM_CMPO_MOD_ID			0x153
 
@@ -2114,6 +2097,21 @@ struct ice_aqc_nvm_cmpo {
 	__le16 cages_cfg[8];
 };
 
+/* Used for reading and writing MinSRev using 0x0701 and 0x0703. Note that the
+ * type field is excluded from the section when reading and writing from
+ * a module using the module_typeid field with these AQ commands.
+ */
+struct ice_aqc_nvm_minsrev {
+	__le16 length;
+	__le16 validity;
+#define ICE_AQC_NVM_MINSREV_NVM_VALID		BIT(0)
+#define ICE_AQC_NVM_MINSREV_OROM_VALID		BIT(1)
+	__le16 nvm_minsrev_l;
+	__le16 nvm_minsrev_h;
+	__le16 orom_minsrev_l;
+	__le16 orom_minsrev_h;
+};
+
 struct ice_aqc_nvm_tx_topo_user_sel {
 	__le16 length;
 	u8 data;
@@ -2431,6 +2429,15 @@ struct ice_aqc_clear_fd_table {
 	u8 reserved[12];
 };
 
+/* Sideband Control Interface Commands */
+/* Neighbor Device Request (indirect 0x0C00); also used for the response. */
+struct ice_aqc_neigh_dev_req {
+	__le16 sb_data_len;
+	u8 reserved[6];
+	__le32 addr_high;
+	__le32 addr_low;
+};
+
 /* Allocate ACL table (indirect 0x0C10) */
 #define ICE_AQC_ACL_KEY_WIDTH		40
 #define ICE_AQC_ACL_KEY_WIDTH_BYTES	5
@@ -3260,10 +3267,8 @@ struct ice_aq_desc {
 		struct ice_aqc_nvm nvm;
 		struct ice_aqc_nvm_cfg nvm_cfg;
 		struct ice_aqc_nvm_checksum nvm_checksum;
-		struct ice_aqc_pfc_ignore pfc_ignore;
 		struct ice_aqc_nvm_sanitization sanitization;
 		struct ice_aqc_set_query_pfc_mode set_query_pfc_mode;
-		struct ice_aqc_set_dcb_params set_dcb_params;
 		struct ice_aqc_lldp_get_mib lldp_get_mib;
 		struct ice_aqc_lldp_set_mib_change lldp_set_event;
 		struct ice_aqc_lldp_add_delete_tlv lldp_add_delete_tlv;
@@ -3276,6 +3281,7 @@ struct ice_aq_desc {
 		struct ice_aqc_get_set_rss_lut get_set_rss_lut;
 		struct ice_aqc_get_set_rss_key get_set_rss_key;
 		struct ice_aqc_clear_fd_table clear_fd_table;
+		struct ice_aqc_neigh_dev_req neigh_dev;
 		struct ice_aqc_acl_alloc_table alloc_table;
 		struct ice_aqc_acl_tbl_actpair tbl_actpair;
 		struct ice_aqc_acl_alloc_scen alloc_scen;
@@ -3516,6 +3522,8 @@ enum ice_adminq_opc {
 	ice_aqc_opc_nvm_sr_dump				= 0x0707,
 	ice_aqc_opc_nvm_save_factory_settings		= 0x0708,
 	ice_aqc_opc_nvm_update_empr			= 0x0709,
+	ice_aqc_opc_nvm_pkg_data			= 0x070A,
+	ice_aqc_opc_nvm_pass_component_tbl		= 0x070B,
 	ice_aqc_opc_nvm_sanitization			= 0x070C,
 
 	/* LLDP commands */
@@ -3538,6 +3546,8 @@ enum ice_adminq_opc {
 	ice_aqc_opc_get_rss_key				= 0x0B04,
 	ice_aqc_opc_get_rss_lut				= 0x0B05,
 	ice_aqc_opc_clear_fd_table			= 0x0B06,
+	/* Sideband Control Interface commands */
+	ice_aqc_opc_neighbour_device_request		= 0x0C00,
 	/* ACL commands */
 	ice_aqc_opc_alloc_acl_tbl			= 0x0C10,
 	ice_aqc_opc_dealloc_acl_tbl			= 0x0C11,
diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h
index a28345c2c4..a4eb6e45ed 100644
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -162,7 +162,6 @@ struct ice_fltr_desc {
 
 #define ICE_FXD_FLTR_QW1_FDID_PRI_S	25
 #define ICE_FXD_FLTR_QW1_FDID_PRI_M	(0x7ULL << ICE_FXD_FLTR_QW1_FDID_PRI_S)
-#define ICE_FXD_FLTR_QW1_FDID_PRI_ZERO	0x0ULL
 #define ICE_FXD_FLTR_QW1_FDID_PRI_ONE	0x1ULL
 #define ICE_FXD_FLTR_QW1_FDID_PRI_THREE	0x3ULL
 
@@ -284,6 +283,7 @@ enum ice_rx_desc_error_l3l4e_masks {
 enum ice_rx_l2_ptype {
 	ICE_RX_PTYPE_L2_RESERVED	= 0,
 	ICE_RX_PTYPE_L2_MAC_PAY2	= 1,
+	ICE_RX_PTYPE_L2_TIMESYNC_PAY2	= 2,
 	ICE_RX_PTYPE_L2_FIP_PAY2	= 3,
 	ICE_RX_PTYPE_L2_OUI_PAY2	= 4,
 	ICE_RX_PTYPE_L2_MACCNTRL_PAY2	= 5,
@@ -343,6 +343,7 @@ enum ice_rx_ptype_inner_prot {
 	ICE_RX_PTYPE_INNER_PROT_TCP		= 2,
 	ICE_RX_PTYPE_INNER_PROT_SCTP		= 3,
 	ICE_RX_PTYPE_INNER_PROT_ICMP		= 4,
+	ICE_RX_PTYPE_INNER_PROT_TIMESYNC	= 5,
 };
 
 enum ice_rx_ptype_payload_layer {
@@ -930,6 +931,8 @@ enum ice_rx_flex_desc_exstat_bits {
 
 #define ICE_RXQ_CTX_SIZE_DWORDS		8
 #define ICE_RXQ_CTX_SZ			(ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32))
+#define ICE_TXQ_CTX_SIZE_DWORDS		10
+#define ICE_TXQ_CTX_SZ			(ICE_TXQ_CTX_SIZE_DWORDS * sizeof(u32))
 #define ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS	22
 #define ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS	5
 #define GLTCLAN_CQ_CNTX(i, CQ)		(GLTCLAN_CQ_CNTX0(CQ) + ((i) * 0x0800))
@@ -1070,7 +1073,7 @@ enum ice_tx_desc_len_fields {
 struct ice_tx_ctx_desc {
 	__le32 tunneling_params;
 	__le16 l2tag2;
-	__le16 gsc;
+	__le16 gcs;
 	__le64 qw1;
 };
 
@@ -1190,6 +1193,7 @@ struct ice_tlan_ctx {
 	u8 pkt_shaper_prof_idx;
 	u8 gsc_ena;
 	u8 int_q_state;	/* width not needed - internal - DO NOT WRITE!!! */
+	u16 tail;
 };
 
 /* LAN Tx Completion Queue data */
@@ -1206,6 +1210,7 @@ struct ice_tx_cmpltnq {
 #pragma pack(1)
 struct ice_tx_cmpltnq_ctx {
 	u64 base;
+#define ICE_TX_CMPLTNQ_CTX_BASE_S	7
 	u32 q_len;
 #define ICE_TX_CMPLTNQ_CTX_Q_LEN_S	4
 	u8 generation;
@@ -1213,6 +1218,9 @@ struct ice_tx_cmpltnq_ctx {
 	u8 pf_num;
 	u16 vmvf_num;
 	u8 vmvf_type;
+#define ICE_TX_CMPLTNQ_CTX_VMVF_TYPE_VF		0
+#define ICE_TX_CMPLTNQ_CTX_VMVF_TYPE_VMQ	1
+#define ICE_TX_CMPLTNQ_CTX_VMVF_TYPE_PF		2
 	u8 tph_desc_wr;
 	u8 cpuid;
 	u32 cmpltn_cache[16];
@@ -1227,15 +1235,30 @@ struct ice_tx_drbell_fmt {
 	u32 db;
 };
 
+/* FIXME: move to a .c file that references this variable */
+/* LAN Tx Doorbell Descriptor format info */
+static const struct ice_ctx_ele ice_tx_drbell_fmt_info[] = {
+					 /* Field		Width	LSB */
+	ICE_CTX_STORE(ice_tx_drbell_fmt, txq_id,		14,	0),
+	ICE_CTX_STORE(ice_tx_drbell_fmt, dd,			1,	14),
+	ICE_CTX_STORE(ice_tx_drbell_fmt, rs,			1,	15),
+	ICE_CTX_STORE(ice_tx_drbell_fmt, db,			32,	32),
+	{ 0 }
+};
 
 /* LAN Tx Doorbell Queue Context */
 #pragma pack(1)
 struct ice_tx_drbell_q_ctx {
 	u64 base;
+#define ICE_TX_DRBELL_Q_CTX_BASE_S	7
 	u16 ring_len;
+#define ICE_TX_DRBELL_Q_CTX_RING_LEN_S	4
 	u8 pf_num;
 	u16 vf_num;
 	u8 vmvf_type;
+#define ICE_TX_DRBELL_Q_CTX_VMVF_TYPE_VF	0
+#define ICE_TX_DRBELL_Q_CTX_VMVF_TYPE_VMQ	1
+#define ICE_TX_DRBELL_Q_CTX_VMVF_TYPE_PF	2
 	u8 cpuid;
 	u8 tph_desc_rd;
 	u8 tph_desc_wr;
@@ -1285,6 +1308,7 @@ struct ice_tx_drbell_q_ctx {
 /* shorter macros makes the table fit but are terse */
 #define ICE_RX_PTYPE_NOF		ICE_RX_PTYPE_NOT_FRAG
 #define ICE_RX_PTYPE_FRG		ICE_RX_PTYPE_FRAG
+#define ICE_RX_PTYPE_INNER_PROT_TS	ICE_RX_PTYPE_INNER_PROT_TIMESYNC
 
 /* Lookup table mapping the 10-bit HW PTYPE to the bit field for decoding */
 static const struct ice_rx_ptype_decoded ice_ptype_lkup[1024] = {
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index e199868326..4fea771ebe 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -43,6 +43,24 @@ static inline int ice_ilog2(u64 n)
 	return -1;
 }
 
+/**
+ * ice_fls - find the most significant bit set in a u64
+ * @n: u64 value to scan for a bit
+ *
+ * Returns: 0 if no bits found, otherwise the index of the highest bit that was
+ * set, like ice_fls(0x20) == 6. This means this is returning a *1 based*
+ * count, and that the maximum largest value returned is 64!
+ */
+static inline unsigned int ice_fls(u64 n)
+{
+	int ret;
+
+	ret = ice_ilog2(n);
+
+	/* add one to turn to the ilog2 value into a 1 based index */
+	return ret >= 0 ? ret + 1 : 0;
+}
+
 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)
 {
 	return ice_is_bit_set(&bitmap, tc);
@@ -98,6 +116,8 @@ static inline u32 ice_round_to_num(u32 N, u32 R)
 #define ICE_LO_DWORD(x)		((u32)((x) & 0xFFFFFFFF))
 #define ICE_HI_WORD(x)		((u16)(((x) >> 16) & 0xFFFF))
 #define ICE_LO_WORD(x)		((u16)((x) & 0xFFFF))
+#define ICE_HI_BYTE(x)		((u8)(((x) >> 8) & 0xFF))
+#define ICE_LO_BYTE(x)		((u8)((x) & 0xFF))
 
 /* debug masks - set these bits in hw->debug_mask to control output */
 #define ICE_DBG_TRACE		BIT_ULL(0) /* for function-trace only */
@@ -918,6 +938,14 @@ struct ice_nvm_info {
 	u8 minor;
 };
 
+/* Minimum Security Revision information */
+struct ice_minsrev_info {
+	u32 nvm;
+	u32 orom;
+	u8 nvm_valid : 1;
+	u8 orom_valid : 1;
+};
+
 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules
  * of the flash image.
  */
@@ -1231,6 +1259,7 @@ struct ice_port_info {
 	struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
 	struct ice_qos_cfg qos_cfg;
 	u8 is_vf:1;
+	u8 is_custom_tx_enabled:1;
 };
 
 struct ice_switch_info {
@@ -1511,6 +1540,7 @@ enum ice_sw_fwd_act_type {
 	ICE_FWD_TO_QGRP,
 	ICE_SET_MARK,
 	ICE_DROP_PACKET,
+	ICE_LG_ACTION,
 	ICE_INVAL_ACT
 };
 
-- 
2.43.0