DPDK patches and discussions
 help / color / mirror / Atom feed
* [dpdk-dev] [PATCH] net/i40e: fix X722 FDIR field mask
@ 2021-01-29  2:09 Zhang,Alvin
  2021-01-29  3:34 ` Xing, Beilei
                   ` (2 more replies)
  0 siblings, 3 replies; 11+ messages in thread
From: Zhang,Alvin @ 2021-01-29  2:09 UTC (permalink / raw)
  To: jia.guo, beilei.xing, qi.z.zhang; +Cc: dev

From: Alvin Zhang <alvinx.zhang@intel.com>

The absolute field offsets of IPv4 or IPv6 header are related to
hardware configuration. The X710 and X722 have different hardware
configurations, and users can even modify the hardware configuration.
Therefore, The default values cannot be used when calculating mask
offset.

commands and packets as below:
  flow create 0 ingress pattern eth / ipv4 proto is 255  / end
  actions queue index 2 / end
  pkt = Ether()/IP(ttl=63, proto=255)/Raw('X'*40)

  flow create 0 ingress pattern eth / ipv4 tos is 50 / udp / end
  actions queue index 2 / end
  pkt = Ether()/IP(tos=50)/UDP()/Raw('X'*40)

  flow create 0 ingress pattern eth / ipv6 tc is 12 / udp / end
  actions queue index 3 / end
  pkt = Ether()/IPv6(tc=12,hlim=34,fl=0x98765)/UDP()/Raw('X'*40)

  flow create 0 ingress pattern eth / ipv6 hop is 34 / end actions
  queue index 3 / end
  pkt = Ether()/IPv6(tc=12,hlim=34,fl=0x98765)/Raw('X'*40)

This patch read the field offsets from the NIC and return the
mask register value.

Fixes: 98f055707685 ("i40e: configure input fields for RSS or flow director")
Fixes: 92cf7f8ec082 ("i40e: allow filtering on more IP header fields")
Cc: stable@dpdk.org

Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com>
---
 drivers/net/i40e/i40e_ethdev.c | 158 +++++++++++++++++++++++++++++++----------
 drivers/net/i40e/i40e_ethdev.h |   4 +-
 drivers/net/i40e/i40e_flow.c   |   2 +-
 3 files changed, 125 insertions(+), 39 deletions(-)

diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 946994b..e21c125 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -202,12 +202,12 @@
 #define I40E_TRANSLATE_INSET 0
 #define I40E_TRANSLATE_REG   1
 
-#define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
-#define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
-#define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
-#define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
-#define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
-#define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
+#define I40E_INSET_IPV4_TOS_MASK        0x0000FF00UL
+#define I40E_INSET_IPV4_TTL_MASK        0x000000FFUL
+#define I40E_INSET_IPV4_PROTO_MASK      0x0000FF00UL
+#define I40E_INSET_IPV6_TC_MASK         0x0000F00FUL
+#define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x0000FF00UL
+#define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000000FFUL
 
 /* PCI offset for querying capability */
 #define PCI_DEV_CAP_REG            0xA4
@@ -220,6 +220,25 @@
 /* Bit mask of Extended Tag enable/disable */
 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 
+#define I40E_GLQF_PIT_IPV4_START	2
+#define I40E_GLQF_PIT_IPV4_COUNT	2
+#define I40E_GLQF_PIT_IPV6_START	4
+#define I40E_GLQF_PIT_IPV6_COUNT	2
+
+#define I40E_GLQF_PIT_SOURCE_OFF_GET(a)	\
+				(((a) & I40E_GLQF_PIT_SOURCE_OFF_MASK) >> \
+				 I40E_GLQF_PIT_SOURCE_OFF_SHIFT)
+
+#define I40E_GLQF_PIT_DEST_OFF_GET(a) \
+				(((a) & I40E_GLQF_PIT_DEST_OFF_MASK) >> \
+				 I40E_GLQF_PIT_DEST_OFF_SHIFT)
+
+#define I40E_GLQF_PIT_FSIZE_GET(a)	(((a) & I40E_GLQF_PIT_FSIZE_MASK) >> \
+					 I40E_GLQF_PIT_FSIZE_SHIFT)
+
+#define I40E_GLQF_PIT_BUILD(off, mask)	(((off) << 16) | (mask))
+#define I40E_FDIR_FIELD_OFFSET(a)	((a) >> 1)
+
 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 static int i40e_dev_configure(struct rte_eth_dev *dev);
@@ -9417,49 +9436,116 @@ i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
 	return val;
 }
 
+static int
+i40e_fd_get_field_offset(struct i40e_hw *hw, uint32_t pit_reg_start,
+			      uint32_t pit_reg_count, uint32_t hdr_off)
+{
+	const uint32_t pit_reg_end = pit_reg_start + pit_reg_count;
+	uint32_t field_off = I40E_FDIR_FIELD_OFFSET(hdr_off);
+	uint32_t i, reg_val, src_off, count;
+
+	for (i = pit_reg_start; i < pit_reg_end; i++) {
+		reg_val = i40e_read_rx_ctl(hw, I40E_GLQF_PIT(i));
+
+		src_off = I40E_GLQF_PIT_SOURCE_OFF_GET(reg_val);
+		count = I40E_GLQF_PIT_FSIZE_GET(reg_val);
+
+		if (src_off <= field_off && (src_off + count) > field_off)
+			break;
+	}
+
+	if (i >= pit_reg_end) {
+		PMD_DRV_LOG(ERR,
+			    "Hardware GLQF_PIT configuration does not support this field mask");
+		return -1;
+	}
+
+	return I40E_GLQF_PIT_DEST_OFF_GET(reg_val) + field_off - src_off;
+}
+
 int
-i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
+i40e_generate_inset_mask_reg(struct i40e_hw *hw, uint64_t inset,
+			     uint32_t *mask, uint8_t nb_elem)
 {
-	uint8_t i, idx = 0;
-	uint64_t inset_need_mask = inset;
+	static const uint64_t mask_inset[] = {
+		I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL,
+		I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT };
 
 	static const struct {
 		uint64_t inset;
 		uint32_t mask;
-	} inset_mask_map[] = {
-		{I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
-		{I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
-		{I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
-		{I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
-		{I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
-		{I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
-		{I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
-		{I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
+		uint32_t offset;
+	} inset_mask_offset_map[] = {
+		{ I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK,
+		  offsetof(struct rte_ipv4_hdr, type_of_service) },
+
+		{ I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK,
+		  offsetof(struct rte_ipv4_hdr, next_proto_id) },
+
+		{ I40E_INSET_IPV4_TTL, I40E_INSET_IPV4_TTL_MASK,
+		  offsetof(struct rte_ipv4_hdr, time_to_live) },
+
+		{ I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK,
+		  offsetof(struct rte_ipv6_hdr, vtc_flow) },
+
+		{ I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK,
+		  offsetof(struct rte_ipv6_hdr, proto) },
+
+		{ I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK,
+		  offsetof(struct rte_ipv6_hdr, hop_limits) },
 	};
 
-	if (!inset || !mask || !nb_elem)
+	uint32_t i;
+	int idx = 0;
+
+	assert(mask);
+	if (!inset)
 		return 0;
 
-	for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
+	for (i = 0; i < RTE_DIM(mask_inset); i++) {
 		/* Clear the inset bit, if no MASK is required,
 		 * for example proto + ttl
 		 */
-		if ((inset & inset_mask_map[i].inset) ==
-		     inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
-			inset_need_mask &= ~inset_mask_map[i].inset;
-		if (!inset_need_mask)
-			return 0;
+		if ((mask_inset[i] & inset) == mask_inset[i]) {
+			inset &= ~mask_inset[i];
+			if (!inset)
+				return 0;
+		}
 	}
-	for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
-		if ((inset_need_mask & inset_mask_map[i].inset) ==
-		    inset_mask_map[i].inset) {
-			if (idx >= nb_elem) {
-				PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
-				return -EINVAL;
-			}
-			mask[idx] = inset_mask_map[i].mask;
-			idx++;
+
+	for (i = 0; i < RTE_DIM(inset_mask_offset_map); i++) {
+		int offset, pit_start, pit_count;
+
+		if (!(inset_mask_offset_map[i].inset & inset))
+			continue;
+
+		if (inset_mask_offset_map[i].inset &
+		    (I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
+		     I40E_INSET_IPV4_TTL)) {
+			pit_start = I40E_GLQF_PIT_IPV4_START;
+			pit_count = I40E_GLQF_PIT_IPV4_COUNT;
+		} else {
+			pit_start = I40E_GLQF_PIT_IPV6_START;
+			pit_count = I40E_GLQF_PIT_IPV6_COUNT;
+		}
+
+		offset = inset_mask_offset_map[i].offset;
+		offset = i40e_fd_get_field_offset(hw, pit_start, pit_count,
+						  offset);
+
+		if (offset < 0)
+			return -EINVAL;
+
+		if (idx >= nb_elem) {
+			PMD_DRV_LOG(ERR,
+				    "FD_MASK configuration out of range %u",
+				    nb_elem);
+			return -ERANGE;
 		}
+
+		mask[idx] = I40E_GLQF_PIT_BUILD(offset,
+						inset_mask_offset_map[i].mask);
+		idx++;
 	}
 
 	return idx;
@@ -9513,7 +9599,7 @@ i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
 
 		input_set = i40e_get_default_input_set(pctype);
 
-		num = i40e_generate_inset_mask_reg(input_set, mask_reg,
+		num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
 						   I40E_INSET_MASK_NUM_REG);
 		if (num < 0)
 			return;
@@ -9593,7 +9679,7 @@ i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
 		inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
 		input_set |= pf->hash_input_set[pctype];
 	}
-	num = i40e_generate_inset_mask_reg(input_set, mask_reg,
+	num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
 					   I40E_INSET_MASK_NUM_REG);
 	if (num < 0)
 		return -EINVAL;
diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h
index 1e8f5d3..faf6896 100644
--- a/drivers/net/i40e/i40e_ethdev.h
+++ b/drivers/net/i40e/i40e_ethdev.h
@@ -1458,8 +1458,8 @@ void i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw,
 					     uint8_t enable);
 int i40e_validate_input_set(enum i40e_filter_pctype pctype,
 			    enum rte_filter_type filter, uint64_t inset);
-int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask,
-				 uint8_t nb_elem);
+int i40e_generate_inset_mask_reg(struct i40e_hw *hw, uint64_t inset,
+				 uint32_t *mask, uint8_t nb_elem);
 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input);
 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val);
 void i40e_check_write_global_reg(struct i40e_hw *hw,
diff --git a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.c
index 7fe760d..ac77cc3 100644
--- a/drivers/net/i40e/i40e_flow.c
+++ b/drivers/net/i40e/i40e_flow.c
@@ -2269,7 +2269,7 @@ static int i40e_flow_parse_l4_cloud_filter(struct rte_eth_dev *dev,
 	    !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
 		return 0;
 
-	num = i40e_generate_inset_mask_reg(input_set, mask_reg,
+	num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
 					   I40E_INSET_MASK_NUM_REG);
 	if (num < 0)
 		return -EINVAL;
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [dpdk-dev] [PATCH] net/i40e: fix X722 FDIR field mask
  2021-01-29  2:09 [dpdk-dev] [PATCH] net/i40e: fix X722 FDIR field mask Zhang,Alvin
@ 2021-01-29  3:34 ` Xing, Beilei
  2021-01-29  3:46   ` Zhang, AlvinX
  2021-01-29  5:11   ` Zhang, AlvinX
  2021-01-29  3:54 ` Zhou, JunX W
  2021-02-01  2:40 ` [dpdk-dev] [PATCH v2] net/i40e: fix inputset " Zhang,Alvin
  2 siblings, 2 replies; 11+ messages in thread
From: Xing, Beilei @ 2021-01-29  3:34 UTC (permalink / raw)
  To: Zhang, AlvinX, Guo, Jia, Zhang, Qi Z; +Cc: dev



> -----Original Message-----
> From: Zhang,Alvin <alvinx.zhang@intel.com>
> Sent: Friday, January 29, 2021 10:09 AM
> To: Guo, Jia <jia.guo@intel.com>; Xing, Beilei <beilei.xing@intel.com>; Zhang,
> Qi Z <qi.z.zhang@intel.com>
> Cc: dev@dpdk.org
> Subject: [PATCH] net/i40e: fix X722 FDIR field mask
> 
> From: Alvin Zhang <alvinx.zhang@intel.com>
> 
> The absolute field offsets of IPv4 or IPv6 header are related to hardware
> configuration. The X710 and X722 have different hardware configurations, and
> users can even modify the hardware configuration.
> Therefore, The default values cannot be used when calculating mask offset.
> 
> commands and packets as below:
>   flow create 0 ingress pattern eth / ipv4 proto is 255  / end
>   actions queue index 2 / end
>   pkt = Ether()/IP(ttl=63, proto=255)/Raw('X'*40)
> 
>   flow create 0 ingress pattern eth / ipv4 tos is 50 / udp / end
>   actions queue index 2 / end
>   pkt = Ether()/IP(tos=50)/UDP()/Raw('X'*40)
> 
>   flow create 0 ingress pattern eth / ipv6 tc is 12 / udp / end
>   actions queue index 3 / end
>   pkt = Ether()/IPv6(tc=12,hlim=34,fl=0x98765)/UDP()/Raw('X'*40)
> 
>   flow create 0 ingress pattern eth / ipv6 hop is 34 / end actions
>   queue index 3 / end
>   pkt = Ether()/IPv6(tc=12,hlim=34,fl=0x98765)/Raw('X'*40)

Not very clear about the issue, the above flows will fail to be created with X722?
And you fix is for FDIR, does RSS have similar issue?

Beilei



^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [dpdk-dev] [PATCH] net/i40e: fix X722 FDIR field mask
  2021-01-29  3:34 ` Xing, Beilei
@ 2021-01-29  3:46   ` Zhang, AlvinX
  2021-01-29  5:11   ` Zhang, AlvinX
  1 sibling, 0 replies; 11+ messages in thread
From: Zhang, AlvinX @ 2021-01-29  3:46 UTC (permalink / raw)
  To: Xing, Beilei, Guo, Jia, Zhang, Qi Z; +Cc: dev

Hi Beilei,

Thanks for your review.

In theory, RSS does have the same issue, 
but in fact, there is no command to set the mask bit of these field when configuring RSS.

BR,
Alvin

> -----Original Message-----
> From: Xing, Beilei <beilei.xing@intel.com>
> Sent: Friday, January 29, 2021 11:34 AM
> To: Zhang, AlvinX <alvinx.zhang@intel.com>; Guo, Jia <jia.guo@intel.com>;
> Zhang, Qi Z <qi.z.zhang@intel.com>
> Cc: dev@dpdk.org
> Subject: RE: [PATCH] net/i40e: fix X722 FDIR field mask
> 
> 
> 
> > -----Original Message-----
> > From: Zhang,Alvin <alvinx.zhang@intel.com>
> > Sent: Friday, January 29, 2021 10:09 AM
> > To: Guo, Jia <jia.guo@intel.com>; Xing, Beilei
> > <beilei.xing@intel.com>; Zhang, Qi Z <qi.z.zhang@intel.com>
> > Cc: dev@dpdk.org
> > Subject: [PATCH] net/i40e: fix X722 FDIR field mask
> >
> > From: Alvin Zhang <alvinx.zhang@intel.com>
> >
> > The absolute field offsets of IPv4 or IPv6 header are related to
> > hardware configuration. The X710 and X722 have different hardware
> > configurations, and users can even modify the hardware configuration.
> > Therefore, The default values cannot be used when calculating mask offset.
> >
> > commands and packets as below:
> >   flow create 0 ingress pattern eth / ipv4 proto is 255  / end
> >   actions queue index 2 / end
> >   pkt = Ether()/IP(ttl=63, proto=255)/Raw('X'*40)
> >
> >   flow create 0 ingress pattern eth / ipv4 tos is 50 / udp / end
> >   actions queue index 2 / end
> >   pkt = Ether()/IP(tos=50)/UDP()/Raw('X'*40)
> >
> >   flow create 0 ingress pattern eth / ipv6 tc is 12 / udp / end
> >   actions queue index 3 / end
> >   pkt = Ether()/IPv6(tc=12,hlim=34,fl=0x98765)/UDP()/Raw('X'*40)
> >
> >   flow create 0 ingress pattern eth / ipv6 hop is 34 / end actions
> >   queue index 3 / end
> >   pkt = Ether()/IPv6(tc=12,hlim=34,fl=0x98765)/Raw('X'*40)
> 
> Not very clear about the issue, the above flows will fail to be created with X722?
> And you fix is for FDIR, does RSS have similar issue?
> 
> Beilei
> 


^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [dpdk-dev] [PATCH] net/i40e: fix X722 FDIR field mask
  2021-01-29  2:09 [dpdk-dev] [PATCH] net/i40e: fix X722 FDIR field mask Zhang,Alvin
  2021-01-29  3:34 ` Xing, Beilei
@ 2021-01-29  3:54 ` Zhou, JunX W
  2021-02-01  2:40 ` [dpdk-dev] [PATCH v2] net/i40e: fix inputset " Zhang,Alvin
  2 siblings, 0 replies; 11+ messages in thread
From: Zhou, JunX W @ 2021-01-29  3:54 UTC (permalink / raw)
  To: Zhang, AlvinX, Guo, Jia, Xing, Beilei, Zhang, Qi Z; +Cc: dev

Tested-by: Zhou, Jun <junx.w.zhou@intel.com>

-----Original Message-----
From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Zhang,Alvin
Sent: Friday, January 29, 2021 10:09 AM
To: Guo, Jia <jia.guo@intel.com>; Xing, Beilei <beilei.xing@intel.com>; Zhang, Qi Z <qi.z.zhang@intel.com>
Cc: dev@dpdk.org
Subject: [dpdk-dev] [PATCH] net/i40e: fix X722 FDIR field mask

From: Alvin Zhang <alvinx.zhang@intel.com>

The absolute field offsets of IPv4 or IPv6 header are related to hardware configuration. The X710 and X722 have different hardware configurations, and users can even modify the hardware configuration.
Therefore, The default values cannot be used when calculating mask offset.

commands and packets as below:
  flow create 0 ingress pattern eth / ipv4 proto is 255  / end
  actions queue index 2 / end
  pkt = Ether()/IP(ttl=63, proto=255)/Raw('X'*40)

  flow create 0 ingress pattern eth / ipv4 tos is 50 / udp / end
  actions queue index 2 / end
  pkt = Ether()/IP(tos=50)/UDP()/Raw('X'*40)

  flow create 0 ingress pattern eth / ipv6 tc is 12 / udp / end
  actions queue index 3 / end
  pkt = Ether()/IPv6(tc=12,hlim=34,fl=0x98765)/UDP()/Raw('X'*40)

  flow create 0 ingress pattern eth / ipv6 hop is 34 / end actions
  queue index 3 / end
  pkt = Ether()/IPv6(tc=12,hlim=34,fl=0x98765)/Raw('X'*40)

This patch read the field offsets from the NIC and return the mask register value.

Fixes: 98f055707685 ("i40e: configure input fields for RSS or flow director")
Fixes: 92cf7f8ec082 ("i40e: allow filtering on more IP header fields")
Cc: stable@dpdk.org

Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com>
---
 drivers/net/i40e/i40e_ethdev.c | 158 +++++++++++++++++++++++++++++++----------
 drivers/net/i40e/i40e_ethdev.h |   4 +-
 drivers/net/i40e/i40e_flow.c   |   2 +-
 3 files changed, 125 insertions(+), 39 deletions(-)

diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 946994b..e21c125 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -202,12 +202,12 @@
 #define I40E_TRANSLATE_INSET 0
 #define I40E_TRANSLATE_REG   1
 
-#define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
-#define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
-#define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
-#define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
-#define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
-#define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
+#define I40E_INSET_IPV4_TOS_MASK        0x0000FF00UL
+#define I40E_INSET_IPV4_TTL_MASK        0x000000FFUL
+#define I40E_INSET_IPV4_PROTO_MASK      0x0000FF00UL
+#define I40E_INSET_IPV6_TC_MASK         0x0000F00FUL
+#define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x0000FF00UL
+#define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000000FFUL
 
 /* PCI offset for querying capability */
 #define PCI_DEV_CAP_REG            0xA4
@@ -220,6 +220,25 @@
 /* Bit mask of Extended Tag enable/disable */  #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 
+#define I40E_GLQF_PIT_IPV4_START	2
+#define I40E_GLQF_PIT_IPV4_COUNT	2
+#define I40E_GLQF_PIT_IPV6_START	4
+#define I40E_GLQF_PIT_IPV6_COUNT	2
+
+#define I40E_GLQF_PIT_SOURCE_OFF_GET(a)	\
+				(((a) & I40E_GLQF_PIT_SOURCE_OFF_MASK) >> \
+				 I40E_GLQF_PIT_SOURCE_OFF_SHIFT)
+
+#define I40E_GLQF_PIT_DEST_OFF_GET(a) \
+				(((a) & I40E_GLQF_PIT_DEST_OFF_MASK) >> \
+				 I40E_GLQF_PIT_DEST_OFF_SHIFT)
+
+#define I40E_GLQF_PIT_FSIZE_GET(a)	(((a) & I40E_GLQF_PIT_FSIZE_MASK) >> \
+					 I40E_GLQF_PIT_FSIZE_SHIFT)
+
+#define I40E_GLQF_PIT_BUILD(off, mask)	(((off) << 16) | (mask))
+#define I40E_FDIR_FIELD_OFFSET(a)	((a) >> 1)
+
 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);  static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);  static int i40e_dev_configure(struct rte_eth_dev *dev); @@ -9417,49 +9436,116 @@ i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
 	return val;
 }
 
+static int
+i40e_fd_get_field_offset(struct i40e_hw *hw, uint32_t pit_reg_start,
+			      uint32_t pit_reg_count, uint32_t hdr_off) {
+	const uint32_t pit_reg_end = pit_reg_start + pit_reg_count;
+	uint32_t field_off = I40E_FDIR_FIELD_OFFSET(hdr_off);
+	uint32_t i, reg_val, src_off, count;
+
+	for (i = pit_reg_start; i < pit_reg_end; i++) {
+		reg_val = i40e_read_rx_ctl(hw, I40E_GLQF_PIT(i));
+
+		src_off = I40E_GLQF_PIT_SOURCE_OFF_GET(reg_val);
+		count = I40E_GLQF_PIT_FSIZE_GET(reg_val);
+
+		if (src_off <= field_off && (src_off + count) > field_off)
+			break;
+	}
+
+	if (i >= pit_reg_end) {
+		PMD_DRV_LOG(ERR,
+			    "Hardware GLQF_PIT configuration does not support this field mask");
+		return -1;
+	}
+
+	return I40E_GLQF_PIT_DEST_OFF_GET(reg_val) + field_off - src_off; }
+
 int
-i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
+i40e_generate_inset_mask_reg(struct i40e_hw *hw, uint64_t inset,
+			     uint32_t *mask, uint8_t nb_elem)
 {
-	uint8_t i, idx = 0;
-	uint64_t inset_need_mask = inset;
+	static const uint64_t mask_inset[] = {
+		I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL,
+		I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT };
 
 	static const struct {
 		uint64_t inset;
 		uint32_t mask;
-	} inset_mask_map[] = {
-		{I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
-		{I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
-		{I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
-		{I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
-		{I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
-		{I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
-		{I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
-		{I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
+		uint32_t offset;
+	} inset_mask_offset_map[] = {
+		{ I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK,
+		  offsetof(struct rte_ipv4_hdr, type_of_service) },
+
+		{ I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK,
+		  offsetof(struct rte_ipv4_hdr, next_proto_id) },
+
+		{ I40E_INSET_IPV4_TTL, I40E_INSET_IPV4_TTL_MASK,
+		  offsetof(struct rte_ipv4_hdr, time_to_live) },
+
+		{ I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK,
+		  offsetof(struct rte_ipv6_hdr, vtc_flow) },
+
+		{ I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK,
+		  offsetof(struct rte_ipv6_hdr, proto) },
+
+		{ I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK,
+		  offsetof(struct rte_ipv6_hdr, hop_limits) },
 	};
 
-	if (!inset || !mask || !nb_elem)
+	uint32_t i;
+	int idx = 0;
+
+	assert(mask);
+	if (!inset)
 		return 0;
 
-	for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
+	for (i = 0; i < RTE_DIM(mask_inset); i++) {
 		/* Clear the inset bit, if no MASK is required,
 		 * for example proto + ttl
 		 */
-		if ((inset & inset_mask_map[i].inset) ==
-		     inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
-			inset_need_mask &= ~inset_mask_map[i].inset;
-		if (!inset_need_mask)
-			return 0;
+		if ((mask_inset[i] & inset) == mask_inset[i]) {
+			inset &= ~mask_inset[i];
+			if (!inset)
+				return 0;
+		}
 	}
-	for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
-		if ((inset_need_mask & inset_mask_map[i].inset) ==
-		    inset_mask_map[i].inset) {
-			if (idx >= nb_elem) {
-				PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
-				return -EINVAL;
-			}
-			mask[idx] = inset_mask_map[i].mask;
-			idx++;
+
+	for (i = 0; i < RTE_DIM(inset_mask_offset_map); i++) {
+		int offset, pit_start, pit_count;
+
+		if (!(inset_mask_offset_map[i].inset & inset))
+			continue;
+
+		if (inset_mask_offset_map[i].inset &
+		    (I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
+		     I40E_INSET_IPV4_TTL)) {
+			pit_start = I40E_GLQF_PIT_IPV4_START;
+			pit_count = I40E_GLQF_PIT_IPV4_COUNT;
+		} else {
+			pit_start = I40E_GLQF_PIT_IPV6_START;
+			pit_count = I40E_GLQF_PIT_IPV6_COUNT;
+		}
+
+		offset = inset_mask_offset_map[i].offset;
+		offset = i40e_fd_get_field_offset(hw, pit_start, pit_count,
+						  offset);
+
+		if (offset < 0)
+			return -EINVAL;
+
+		if (idx >= nb_elem) {
+			PMD_DRV_LOG(ERR,
+				    "FD_MASK configuration out of range %u",
+				    nb_elem);
+			return -ERANGE;
 		}
+
+		mask[idx] = I40E_GLQF_PIT_BUILD(offset,
+						inset_mask_offset_map[i].mask);
+		idx++;
 	}
 
 	return idx;
@@ -9513,7 +9599,7 @@ i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
 
 		input_set = i40e_get_default_input_set(pctype);
 
-		num = i40e_generate_inset_mask_reg(input_set, mask_reg,
+		num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
 						   I40E_INSET_MASK_NUM_REG);
 		if (num < 0)
 			return;
@@ -9593,7 +9679,7 @@ i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
 		inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
 		input_set |= pf->hash_input_set[pctype];
 	}
-	num = i40e_generate_inset_mask_reg(input_set, mask_reg,
+	num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
 					   I40E_INSET_MASK_NUM_REG);
 	if (num < 0)
 		return -EINVAL;
diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h index 1e8f5d3..faf6896 100644
--- a/drivers/net/i40e/i40e_ethdev.h
+++ b/drivers/net/i40e/i40e_ethdev.h
@@ -1458,8 +1458,8 @@ void i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw,
 					     uint8_t enable);
 int i40e_validate_input_set(enum i40e_filter_pctype pctype,
 			    enum rte_filter_type filter, uint64_t inset); -int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask,
-				 uint8_t nb_elem);
+int i40e_generate_inset_mask_reg(struct i40e_hw *hw, uint64_t inset,
+				 uint32_t *mask, uint8_t nb_elem);
 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input);  void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val);  void i40e_check_write_global_reg(struct i40e_hw *hw, diff --git a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.c index 7fe760d..ac77cc3 100644
--- a/drivers/net/i40e/i40e_flow.c
+++ b/drivers/net/i40e/i40e_flow.c
@@ -2269,7 +2269,7 @@ static int i40e_flow_parse_l4_cloud_filter(struct rte_eth_dev *dev,
 	    !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
 		return 0;
 
-	num = i40e_generate_inset_mask_reg(input_set, mask_reg,
+	num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
 					   I40E_INSET_MASK_NUM_REG);
 	if (num < 0)
 		return -EINVAL;
--
1.8.3.1


^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [dpdk-dev] [PATCH] net/i40e: fix X722 FDIR field mask
  2021-01-29  3:34 ` Xing, Beilei
  2021-01-29  3:46   ` Zhang, AlvinX
@ 2021-01-29  5:11   ` Zhang, AlvinX
  1 sibling, 0 replies; 11+ messages in thread
From: Zhang, AlvinX @ 2021-01-29  5:11 UTC (permalink / raw)
  To: Xing, Beilei, Guo, Jia, Zhang, Qi Z; +Cc: dev

Hi Beilei,

> -----Original Message-----
> From: Xing, Beilei <beilei.xing@intel.com>
> Sent: Friday, January 29, 2021 11:34 AM
> To: Zhang, AlvinX <alvinx.zhang@intel.com>; Guo, Jia <jia.guo@intel.com>;
> Zhang, Qi Z <qi.z.zhang@intel.com>
> Cc: dev@dpdk.org
> Subject: RE: [PATCH] net/i40e: fix X722 FDIR field mask
> 
> 
> 
> > -----Original Message-----
> > From: Zhang,Alvin <alvinx.zhang@intel.com>
> > Sent: Friday, January 29, 2021 10:09 AM
> > To: Guo, Jia <jia.guo@intel.com>; Xing, Beilei
> > <beilei.xing@intel.com>; Zhang, Qi Z <qi.z.zhang@intel.com>
> > Cc: dev@dpdk.org
> > Subject: [PATCH] net/i40e: fix X722 FDIR field mask
> >
> > From: Alvin Zhang <alvinx.zhang@intel.com>
> >
> > The absolute field offsets of IPv4 or IPv6 header are related to
> > hardware configuration. The X710 and X722 have different hardware
> > configurations, and users can even modify the hardware configuration.
> > Therefore, The default values cannot be used when calculating mask offset.
> >
> > commands and packets as below:
> >   flow create 0 ingress pattern eth / ipv4 proto is 255  / end
> >   actions queue index 2 / end
> >   pkt = Ether()/IP(ttl=63, proto=255)/Raw('X'*40)
> >
> >   flow create 0 ingress pattern eth / ipv4 tos is 50 / udp / end
> >   actions queue index 2 / end
> >   pkt = Ether()/IP(tos=50)/UDP()/Raw('X'*40)
> >
> >   flow create 0 ingress pattern eth / ipv6 tc is 12 / udp / end
> >   actions queue index 3 / end
> >   pkt = Ether()/IPv6(tc=12,hlim=34,fl=0x98765)/UDP()/Raw('X'*40)
> >
> >   flow create 0 ingress pattern eth / ipv6 hop is 34 / end actions
> >   queue index 3 / end
> >   pkt = Ether()/IPv6(tc=12,hlim=34,fl=0x98765)/Raw('X'*40)
> 
> Not very clear about the issue, the above flows will fail to be created with X722?
> And you fix is for FDIR, does RSS have similar issue?

Above flows created succeed, but they can not take effect.

> 
> Beilei
> 


^ permalink raw reply	[flat|nested] 11+ messages in thread

* [dpdk-dev] [PATCH v2] net/i40e: fix inputset field mask
  2021-01-29  2:09 [dpdk-dev] [PATCH] net/i40e: fix X722 FDIR field mask Zhang,Alvin
  2021-01-29  3:34 ` Xing, Beilei
  2021-01-29  3:54 ` Zhou, JunX W
@ 2021-02-01  2:40 ` Zhang,Alvin
  2021-02-01  3:26   ` Xing, Beilei
  2021-03-01  7:06   ` [dpdk-dev] [PATCH v3] " Alvin Zhang
  2 siblings, 2 replies; 11+ messages in thread
From: Zhang,Alvin @ 2021-02-01  2:40 UTC (permalink / raw)
  To: jia.guo, beilei.xing, qi.z.zhang; +Cc: dev

From: Alvin Zhang <alvinx.zhang@intel.com>

The absolute field offsets of IPv4 or IPv6 header are related to
hardware configuration. The X710 and X722 have different hardware
configurations, and users can even modify the hardware configuration.
Therefore, The default values cannot be used when calculating mask
offset.

The following flows can be created on X722 NIC, but the packet will
not enter the queue 3:
  flow create 0 ingress pattern eth / ipv4 proto is 255  / end
  actions queue index 3 / end
  pkt = Ether()/IP(ttl=63, proto=255)/Raw('X'*40)

  flow create 0 ingress pattern eth / ipv4 tos is 50 / udp / end
  actions queue index 3 / end
  pkt = Ether()/IP(tos=50)/UDP()/Raw('X'*40)

  flow create 0 ingress pattern eth / ipv6 tc is 12 / udp / end
  actions queue index 3 / end
  pkt = Ether()/IPv6(tc=12,hlim=34,fl=0x98765)/UDP()/Raw('X'*40)

  flow create 0 ingress pattern eth / ipv6 hop is 34 / end actions
  queue index 3 / end
  pkt = Ether()/IPv6(tc=12,hlim=34,fl=0x98765)/Raw('X'*40)

This patch read the field offsets from the NIC and return the mask
register value.

Fixes: 98f055707685 ("i40e: configure input fields for RSS or flow director")
Fixes: 92cf7f8ec082 ("i40e: allow filtering on more IP header fields")
Cc: stable@dpdk.org

Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com>
---

v2: Update commit log
---
 drivers/net/i40e/i40e_ethdev.c | 158 +++++++++++++++++++++++++++++++----------
 drivers/net/i40e/i40e_ethdev.h |   4 +-
 drivers/net/i40e/i40e_flow.c   |   2 +-
 3 files changed, 125 insertions(+), 39 deletions(-)

diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 946994b..f167b5f 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -202,12 +202,12 @@
 #define I40E_TRANSLATE_INSET 0
 #define I40E_TRANSLATE_REG   1
 
-#define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
-#define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
-#define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
-#define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
-#define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
-#define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
+#define I40E_INSET_IPV4_TOS_MASK        0x0000FF00UL
+#define I40E_INSET_IPV4_TTL_MASK        0x000000FFUL
+#define I40E_INSET_IPV4_PROTO_MASK      0x0000FF00UL
+#define I40E_INSET_IPV6_TC_MASK         0x0000F00FUL
+#define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x0000FF00UL
+#define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000000FFUL
 
 /* PCI offset for querying capability */
 #define PCI_DEV_CAP_REG            0xA4
@@ -220,6 +220,25 @@
 /* Bit mask of Extended Tag enable/disable */
 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 
+#define I40E_GLQF_PIT_IPV4_START	2
+#define I40E_GLQF_PIT_IPV4_COUNT	2
+#define I40E_GLQF_PIT_IPV6_START	4
+#define I40E_GLQF_PIT_IPV6_COUNT	2
+
+#define I40E_GLQF_PIT_SOURCE_OFF_GET(a)	\
+				(((a) & I40E_GLQF_PIT_SOURCE_OFF_MASK) >> \
+				 I40E_GLQF_PIT_SOURCE_OFF_SHIFT)
+
+#define I40E_GLQF_PIT_DEST_OFF_GET(a) \
+				(((a) & I40E_GLQF_PIT_DEST_OFF_MASK) >> \
+				 I40E_GLQF_PIT_DEST_OFF_SHIFT)
+
+#define I40E_GLQF_PIT_FSIZE_GET(a)	(((a) & I40E_GLQF_PIT_FSIZE_MASK) >> \
+					 I40E_GLQF_PIT_FSIZE_SHIFT)
+
+#define I40E_GLQF_PIT_BUILD(off, mask)	(((off) << 16) | (mask))
+#define I40E_FDIR_FIELD_OFFSET(a)	((a) >> 1)
+
 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 static int i40e_dev_configure(struct rte_eth_dev *dev);
@@ -9417,49 +9436,116 @@ i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
 	return val;
 }
 
+static int
+i40e_fd_get_field_offset(struct i40e_hw *hw, uint32_t pit_reg_start,
+			 uint32_t pit_reg_count, uint32_t hdr_off)
+{
+	const uint32_t pit_reg_end = pit_reg_start + pit_reg_count;
+	uint32_t field_off = I40E_FDIR_FIELD_OFFSET(hdr_off);
+	uint32_t i, reg_val, src_off, count;
+
+	for (i = pit_reg_start; i < pit_reg_end; i++) {
+		reg_val = i40e_read_rx_ctl(hw, I40E_GLQF_PIT(i));
+
+		src_off = I40E_GLQF_PIT_SOURCE_OFF_GET(reg_val);
+		count = I40E_GLQF_PIT_FSIZE_GET(reg_val);
+
+		if (src_off <= field_off && (src_off + count) > field_off)
+			break;
+	}
+
+	if (i >= pit_reg_end) {
+		PMD_DRV_LOG(ERR,
+			    "Hardware GLQF_PIT configuration does not support this field mask");
+		return -1;
+	}
+
+	return I40E_GLQF_PIT_DEST_OFF_GET(reg_val) + field_off - src_off;
+}
+
 int
-i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
+i40e_generate_inset_mask_reg(struct i40e_hw *hw, uint64_t inset,
+			     uint32_t *mask, uint8_t nb_elem)
 {
-	uint8_t i, idx = 0;
-	uint64_t inset_need_mask = inset;
+	static const uint64_t mask_inset[] = {
+		I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL,
+		I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT };
 
 	static const struct {
 		uint64_t inset;
 		uint32_t mask;
-	} inset_mask_map[] = {
-		{I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
-		{I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
-		{I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
-		{I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
-		{I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
-		{I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
-		{I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
-		{I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
+		uint32_t offset;
+	} inset_mask_offset_map[] = {
+		{ I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK,
+		  offsetof(struct rte_ipv4_hdr, type_of_service) },
+
+		{ I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK,
+		  offsetof(struct rte_ipv4_hdr, next_proto_id) },
+
+		{ I40E_INSET_IPV4_TTL, I40E_INSET_IPV4_TTL_MASK,
+		  offsetof(struct rte_ipv4_hdr, time_to_live) },
+
+		{ I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK,
+		  offsetof(struct rte_ipv6_hdr, vtc_flow) },
+
+		{ I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK,
+		  offsetof(struct rte_ipv6_hdr, proto) },
+
+		{ I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK,
+		  offsetof(struct rte_ipv6_hdr, hop_limits) },
 	};
 
-	if (!inset || !mask || !nb_elem)
+	uint32_t i;
+	int idx = 0;
+
+	assert(mask);
+	if (!inset)
 		return 0;
 
-	for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
+	for (i = 0; i < RTE_DIM(mask_inset); i++) {
 		/* Clear the inset bit, if no MASK is required,
 		 * for example proto + ttl
 		 */
-		if ((inset & inset_mask_map[i].inset) ==
-		     inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
-			inset_need_mask &= ~inset_mask_map[i].inset;
-		if (!inset_need_mask)
-			return 0;
+		if ((mask_inset[i] & inset) == mask_inset[i]) {
+			inset &= ~mask_inset[i];
+			if (!inset)
+				return 0;
+		}
 	}
-	for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
-		if ((inset_need_mask & inset_mask_map[i].inset) ==
-		    inset_mask_map[i].inset) {
-			if (idx >= nb_elem) {
-				PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
-				return -EINVAL;
-			}
-			mask[idx] = inset_mask_map[i].mask;
-			idx++;
+
+	for (i = 0; i < RTE_DIM(inset_mask_offset_map); i++) {
+		int offset, pit_start, pit_count;
+
+		if (!(inset_mask_offset_map[i].inset & inset))
+			continue;
+
+		if (inset_mask_offset_map[i].inset &
+		    (I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
+		     I40E_INSET_IPV4_TTL)) {
+			pit_start = I40E_GLQF_PIT_IPV4_START;
+			pit_count = I40E_GLQF_PIT_IPV4_COUNT;
+		} else {
+			pit_start = I40E_GLQF_PIT_IPV6_START;
+			pit_count = I40E_GLQF_PIT_IPV6_COUNT;
+		}
+
+		offset = inset_mask_offset_map[i].offset;
+		offset = i40e_fd_get_field_offset(hw, pit_start, pit_count,
+						  offset);
+
+		if (offset < 0)
+			return -EINVAL;
+
+		if (idx >= nb_elem) {
+			PMD_DRV_LOG(ERR,
+				    "FD_MASK configuration out of range %u",
+				    nb_elem);
+			return -ERANGE;
 		}
+
+		mask[idx] = I40E_GLQF_PIT_BUILD(offset,
+						inset_mask_offset_map[i].mask);
+		idx++;
 	}
 
 	return idx;
@@ -9513,7 +9599,7 @@ i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
 
 		input_set = i40e_get_default_input_set(pctype);
 
-		num = i40e_generate_inset_mask_reg(input_set, mask_reg,
+		num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
 						   I40E_INSET_MASK_NUM_REG);
 		if (num < 0)
 			return;
@@ -9593,7 +9679,7 @@ i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
 		inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
 		input_set |= pf->hash_input_set[pctype];
 	}
-	num = i40e_generate_inset_mask_reg(input_set, mask_reg,
+	num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
 					   I40E_INSET_MASK_NUM_REG);
 	if (num < 0)
 		return -EINVAL;
diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h
index 1e8f5d3..faf6896 100644
--- a/drivers/net/i40e/i40e_ethdev.h
+++ b/drivers/net/i40e/i40e_ethdev.h
@@ -1458,8 +1458,8 @@ void i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw,
 					     uint8_t enable);
 int i40e_validate_input_set(enum i40e_filter_pctype pctype,
 			    enum rte_filter_type filter, uint64_t inset);
-int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask,
-				 uint8_t nb_elem);
+int i40e_generate_inset_mask_reg(struct i40e_hw *hw, uint64_t inset,
+				 uint32_t *mask, uint8_t nb_elem);
 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input);
 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val);
 void i40e_check_write_global_reg(struct i40e_hw *hw,
diff --git a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.c
index 7fe760d..ac77cc3 100644
--- a/drivers/net/i40e/i40e_flow.c
+++ b/drivers/net/i40e/i40e_flow.c
@@ -2269,7 +2269,7 @@ static int i40e_flow_parse_l4_cloud_filter(struct rte_eth_dev *dev,
 	    !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
 		return 0;
 
-	num = i40e_generate_inset_mask_reg(input_set, mask_reg,
+	num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
 					   I40E_INSET_MASK_NUM_REG);
 	if (num < 0)
 		return -EINVAL;
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [dpdk-dev] [PATCH v2] net/i40e: fix inputset field mask
  2021-02-01  2:40 ` [dpdk-dev] [PATCH v2] net/i40e: fix inputset " Zhang,Alvin
@ 2021-02-01  3:26   ` Xing, Beilei
  2021-03-01  7:06   ` [dpdk-dev] [PATCH v3] " Alvin Zhang
  1 sibling, 0 replies; 11+ messages in thread
From: Xing, Beilei @ 2021-02-01  3:26 UTC (permalink / raw)
  To: Zhang, AlvinX, Guo, Jia, Zhang, Qi Z; +Cc: dev



> -----Original Message-----
> From: dev <dev-bounces@dpdk.org> On Behalf Of Zhang,Alvin
> Sent: Monday, February 1, 2021 10:41 AM
> To: Guo, Jia <jia.guo@intel.com>; Xing, Beilei <beilei.xing@intel.com>; Zhang,
> Qi Z <qi.z.zhang@intel.com>
> Cc: dev@dpdk.org
> Subject: [dpdk-dev] [PATCH v2] net/i40e: fix inputset field mask
> 
> From: Alvin Zhang <alvinx.zhang@intel.com>
> 
> The absolute field offsets of IPv4 or IPv6 header are related to hardware
> configuration. The X710 and X722 have different hardware configurations,
> and users can even modify the hardware configuration.
> Therefore, The default values cannot be used when calculating mask offset.
> 
> The following flows can be created on X722 NIC, but the packet will not enter
> the queue 3:
>   flow create 0 ingress pattern eth / ipv4 proto is 255  / end
>   actions queue index 3 / end
>   pkt = Ether()/IP(ttl=63, proto=255)/Raw('X'*40)
> 
>   flow create 0 ingress pattern eth / ipv4 tos is 50 / udp / end
>   actions queue index 3 / end
>   pkt = Ether()/IP(tos=50)/UDP()/Raw('X'*40)
> 
>   flow create 0 ingress pattern eth / ipv6 tc is 12 / udp / end
>   actions queue index 3 / end
>   pkt = Ether()/IPv6(tc=12,hlim=34,fl=0x98765)/UDP()/Raw('X'*40)
> 
>   flow create 0 ingress pattern eth / ipv6 hop is 34 / end actions
>   queue index 3 / end
>   pkt = Ether()/IPv6(tc=12,hlim=34,fl=0x98765)/Raw('X'*40)
> 
> This patch read the field offsets from the NIC and return the mask register
> value.
> 
> Fixes: 98f055707685 ("i40e: configure input fields for RSS or flow director")
> Fixes: 92cf7f8ec082 ("i40e: allow filtering on more IP header fields")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com>
> ---
> 
> v2: Update commit log
> ---
> 
> +static int
> +i40e_fd_get_field_offset(struct i40e_hw *hw, uint32_t pit_reg_start,
It's not only for fdir, but also for RSS, so better to remove '_fd' in the function name. 

> +			 uint32_t pit_reg_count, uint32_t hdr_off) {

Besides, since this patch is too HW specific and large, I suggest we need:
1) regression test first. 
2) verify RSS with private API.
But RC3 is coming, we may have no much time for all tests, so can you submit the patch after 21.02 release?

BR,
Beilei

^ permalink raw reply	[flat|nested] 11+ messages in thread

* [dpdk-dev] [PATCH v3] net/i40e: fix inputset field mask
  2021-02-01  2:40 ` [dpdk-dev] [PATCH v2] net/i40e: fix inputset " Zhang,Alvin
  2021-02-01  3:26   ` Xing, Beilei
@ 2021-03-01  7:06   ` Alvin Zhang
  2021-03-09  2:56     ` Chen, LingliX
  1 sibling, 1 reply; 11+ messages in thread
From: Alvin Zhang @ 2021-03-01  7:06 UTC (permalink / raw)
  To: jia.guo, beilei.xing, qi.z.zhang, junx.w.zhou; +Cc: dev, Alvin Zhang, stable

The absolute field offsets of IPv4 or IPv6 header are related to
hardware configuration. The X710 and X722 have different hardware
configurations, and users can even modify the hardware configuration.
Therefore, The default values cannot be used when calculating mask
offset.

The following flows can be created on X722 NIC, but the packet will
not enter the queue 3:
  flow create 0 ingress pattern eth / ipv4 proto is 255  / end
  actions queue index 3 / end
  pkt = Ether()/IP(ttl=63, proto=255)/Raw('X'*40)

  flow create 0 ingress pattern eth / ipv4 tos is 50 / udp / end
  actions queue index 3 / end
  pkt = Ether()/IP(tos=50)/UDP()/Raw('X'*40)

  flow create 0 ingress pattern eth / ipv6 tc is 12 / udp / end
  actions queue index 3 / end
  pkt = Ether()/IPv6(tc=12,hlim=34,fl=0x98765)/UDP()/Raw('X'*40)

  flow create 0 ingress pattern eth / ipv6 hop is 34 / end actions
  queue index 3 / end
  pkt = Ether()/IPv6(tc=12,hlim=34,fl=0x98765)/Raw('X'*40)

This patch read the field offsets from the NIC and return the mask
register value.

Fixes: 98f055707685 ("i40e: configure input fields for RSS or flow director")
Fixes: 92cf7f8ec082 ("i40e: allow filtering on more IP header fields")
Cc: stable@dpdk.org

Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com>
---

v2: Update commit log
v3: Rename 'i40e_fd_get_field_offset' to
    'i40e_get_inset_field_offset'
---
 drivers/net/i40e/i40e_ethdev.c | 158 +++++++++++++++++++++++++++++++----------
 drivers/net/i40e/i40e_ethdev.h |   4 +-
 drivers/net/i40e/i40e_flow.c   |   2 +-
 3 files changed, 125 insertions(+), 39 deletions(-)

diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index d7cd049..18217b8 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -202,12 +202,12 @@
 #define I40E_TRANSLATE_INSET 0
 #define I40E_TRANSLATE_REG   1
 
-#define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
-#define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
-#define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
-#define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
-#define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
-#define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
+#define I40E_INSET_IPV4_TOS_MASK        0x0000FF00UL
+#define I40E_INSET_IPV4_TTL_MASK        0x000000FFUL
+#define I40E_INSET_IPV4_PROTO_MASK      0x0000FF00UL
+#define I40E_INSET_IPV6_TC_MASK         0x0000F00FUL
+#define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x0000FF00UL
+#define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000000FFUL
 
 /* PCI offset for querying capability */
 #define PCI_DEV_CAP_REG            0xA4
@@ -220,6 +220,25 @@
 /* Bit mask of Extended Tag enable/disable */
 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 
+#define I40E_GLQF_PIT_IPV4_START	2
+#define I40E_GLQF_PIT_IPV4_COUNT	2
+#define I40E_GLQF_PIT_IPV6_START	4
+#define I40E_GLQF_PIT_IPV6_COUNT	2
+
+#define I40E_GLQF_PIT_SOURCE_OFF_GET(a)	\
+				(((a) & I40E_GLQF_PIT_SOURCE_OFF_MASK) >> \
+				 I40E_GLQF_PIT_SOURCE_OFF_SHIFT)
+
+#define I40E_GLQF_PIT_DEST_OFF_GET(a) \
+				(((a) & I40E_GLQF_PIT_DEST_OFF_MASK) >> \
+				 I40E_GLQF_PIT_DEST_OFF_SHIFT)
+
+#define I40E_GLQF_PIT_FSIZE_GET(a)	(((a) & I40E_GLQF_PIT_FSIZE_MASK) >> \
+					 I40E_GLQF_PIT_FSIZE_SHIFT)
+
+#define I40E_GLQF_PIT_BUILD(off, mask)	(((off) << 16) | (mask))
+#define I40E_FDIR_FIELD_OFFSET(a)	((a) >> 1)
+
 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 static int i40e_dev_configure(struct rte_eth_dev *dev);
@@ -9417,49 +9436,116 @@ i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
 	return val;
 }
 
+static int
+i40e_get_inset_field_offset(struct i40e_hw *hw, uint32_t pit_reg_start,
+			    uint32_t pit_reg_count, uint32_t hdr_off)
+{
+	const uint32_t pit_reg_end = pit_reg_start + pit_reg_count;
+	uint32_t field_off = I40E_FDIR_FIELD_OFFSET(hdr_off);
+	uint32_t i, reg_val, src_off, count;
+
+	for (i = pit_reg_start; i < pit_reg_end; i++) {
+		reg_val = i40e_read_rx_ctl(hw, I40E_GLQF_PIT(i));
+
+		src_off = I40E_GLQF_PIT_SOURCE_OFF_GET(reg_val);
+		count = I40E_GLQF_PIT_FSIZE_GET(reg_val);
+
+		if (src_off <= field_off && (src_off + count) > field_off)
+			break;
+	}
+
+	if (i >= pit_reg_end) {
+		PMD_DRV_LOG(ERR,
+			    "Hardware GLQF_PIT configuration does not support this field mask");
+		return -1;
+	}
+
+	return I40E_GLQF_PIT_DEST_OFF_GET(reg_val) + field_off - src_off;
+}
+
 int
-i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
+i40e_generate_inset_mask_reg(struct i40e_hw *hw, uint64_t inset,
+			     uint32_t *mask, uint8_t nb_elem)
 {
-	uint8_t i, idx = 0;
-	uint64_t inset_need_mask = inset;
+	static const uint64_t mask_inset[] = {
+		I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL,
+		I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT };
 
 	static const struct {
 		uint64_t inset;
 		uint32_t mask;
-	} inset_mask_map[] = {
-		{I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
-		{I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
-		{I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
-		{I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
-		{I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
-		{I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
-		{I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
-		{I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
+		uint32_t offset;
+	} inset_mask_offset_map[] = {
+		{ I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK,
+		  offsetof(struct rte_ipv4_hdr, type_of_service) },
+
+		{ I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK,
+		  offsetof(struct rte_ipv4_hdr, next_proto_id) },
+
+		{ I40E_INSET_IPV4_TTL, I40E_INSET_IPV4_TTL_MASK,
+		  offsetof(struct rte_ipv4_hdr, time_to_live) },
+
+		{ I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK,
+		  offsetof(struct rte_ipv6_hdr, vtc_flow) },
+
+		{ I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK,
+		  offsetof(struct rte_ipv6_hdr, proto) },
+
+		{ I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK,
+		  offsetof(struct rte_ipv6_hdr, hop_limits) },
 	};
 
-	if (!inset || !mask || !nb_elem)
+	uint32_t i;
+	int idx = 0;
+
+	assert(mask);
+	if (!inset)
 		return 0;
 
-	for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
+	for (i = 0; i < RTE_DIM(mask_inset); i++) {
 		/* Clear the inset bit, if no MASK is required,
 		 * for example proto + ttl
 		 */
-		if ((inset & inset_mask_map[i].inset) ==
-		     inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
-			inset_need_mask &= ~inset_mask_map[i].inset;
-		if (!inset_need_mask)
-			return 0;
+		if ((mask_inset[i] & inset) == mask_inset[i]) {
+			inset &= ~mask_inset[i];
+			if (!inset)
+				return 0;
+		}
 	}
-	for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
-		if ((inset_need_mask & inset_mask_map[i].inset) ==
-		    inset_mask_map[i].inset) {
-			if (idx >= nb_elem) {
-				PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
-				return -EINVAL;
-			}
-			mask[idx] = inset_mask_map[i].mask;
-			idx++;
+
+	for (i = 0; i < RTE_DIM(inset_mask_offset_map); i++) {
+		uint32_t pit_start, pit_count;
+		int offset;
+
+		if (!(inset_mask_offset_map[i].inset & inset))
+			continue;
+
+		if (inset_mask_offset_map[i].inset &
+		    (I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
+		     I40E_INSET_IPV4_TTL)) {
+			pit_start = I40E_GLQF_PIT_IPV4_START;
+			pit_count = I40E_GLQF_PIT_IPV4_COUNT;
+		} else {
+			pit_start = I40E_GLQF_PIT_IPV6_START;
+			pit_count = I40E_GLQF_PIT_IPV6_COUNT;
+		}
+
+		offset = i40e_get_inset_field_offset(hw, pit_start, pit_count,
+				inset_mask_offset_map[i].offset);
+
+		if (offset < 0)
+			return -EINVAL;
+
+		if (idx >= nb_elem) {
+			PMD_DRV_LOG(ERR,
+				    "Configuration of inset mask out of range %u",
+				    nb_elem);
+			return -ERANGE;
 		}
+
+		mask[idx] = I40E_GLQF_PIT_BUILD((uint32_t)offset,
+						inset_mask_offset_map[i].mask);
+		idx++;
 	}
 
 	return idx;
@@ -9513,7 +9599,7 @@ i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
 
 		input_set = i40e_get_default_input_set(pctype);
 
-		num = i40e_generate_inset_mask_reg(input_set, mask_reg,
+		num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
 						   I40E_INSET_MASK_NUM_REG);
 		if (num < 0)
 			return;
@@ -9593,7 +9679,7 @@ i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
 		inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
 		input_set |= pf->hash_input_set[pctype];
 	}
-	num = i40e_generate_inset_mask_reg(input_set, mask_reg,
+	num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
 					   I40E_INSET_MASK_NUM_REG);
 	if (num < 0)
 		return -EINVAL;
diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h
index 1e8f5d3..faf6896 100644
--- a/drivers/net/i40e/i40e_ethdev.h
+++ b/drivers/net/i40e/i40e_ethdev.h
@@ -1458,8 +1458,8 @@ void i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw,
 					     uint8_t enable);
 int i40e_validate_input_set(enum i40e_filter_pctype pctype,
 			    enum rte_filter_type filter, uint64_t inset);
-int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask,
-				 uint8_t nb_elem);
+int i40e_generate_inset_mask_reg(struct i40e_hw *hw, uint64_t inset,
+				 uint32_t *mask, uint8_t nb_elem);
 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input);
 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val);
 void i40e_check_write_global_reg(struct i40e_hw *hw,
diff --git a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.c
index 4d44282..05842bb 100644
--- a/drivers/net/i40e/i40e_flow.c
+++ b/drivers/net/i40e/i40e_flow.c
@@ -2269,7 +2269,7 @@ static int i40e_flow_parse_l4_cloud_filter(struct rte_eth_dev *dev,
 	    !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
 		return 0;
 
-	num = i40e_generate_inset_mask_reg(input_set, mask_reg,
+	num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
 					   I40E_INSET_MASK_NUM_REG);
 	if (num < 0)
 		return -EINVAL;
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [dpdk-dev] [PATCH v3] net/i40e: fix inputset field mask
  2021-03-01  7:06   ` [dpdk-dev] [PATCH v3] " Alvin Zhang
@ 2021-03-09  2:56     ` Chen, LingliX
  2021-03-24 11:38       ` Zhang, Qi Z
  0 siblings, 1 reply; 11+ messages in thread
From: Chen, LingliX @ 2021-03-09  2:56 UTC (permalink / raw)
  To: Zhang, AlvinX, Guo, Jia, Xing, Beilei, Zhang, Qi Z, Zhou, JunX W
  Cc: dev, Zhang, AlvinX, stable

> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Alvin Zhang
> Sent: Monday, March 1, 2021 3:06 PM
> To: Guo, Jia <jia.guo@intel.com>; Xing, Beilei <beilei.xing@intel.com>; Zhang,
> Qi Z <qi.z.zhang@intel.com>; Zhou, JunX W <junx.w.zhou@intel.com>
> Cc: dev@dpdk.org; Zhang, AlvinX <alvinx.zhang@intel.com>;
> stable@dpdk.org
> Subject: [dpdk-dev] [PATCH v3] net/i40e: fix inputset field mask
> 
> The absolute field offsets of IPv4 or IPv6 header are related to hardware
> configuration. The X710 and X722 have different hardware configurations,
> and users can even modify the hardware configuration.
> Therefore, The default values cannot be used when calculating mask offset.
> 
> The following flows can be created on X722 NIC, but the packet will not enter
> the queue 3:
>   flow create 0 ingress pattern eth / ipv4 proto is 255  / end
>   actions queue index 3 / end
>   pkt = Ether()/IP(ttl=63, proto=255)/Raw('X'*40)
> 
>   flow create 0 ingress pattern eth / ipv4 tos is 50 / udp / end
>   actions queue index 3 / end
>   pkt = Ether()/IP(tos=50)/UDP()/Raw('X'*40)
> 
>   flow create 0 ingress pattern eth / ipv6 tc is 12 / udp / end
>   actions queue index 3 / end
>   pkt = Ether()/IPv6(tc=12,hlim=34,fl=0x98765)/UDP()/Raw('X'*40)
> 
>   flow create 0 ingress pattern eth / ipv6 hop is 34 / end actions
>   queue index 3 / end
>   pkt = Ether()/IPv6(tc=12,hlim=34,fl=0x98765)/Raw('X'*40)
> 
> This patch read the field offsets from the NIC and return the mask register
> value.
> 
> Fixes: 98f055707685 ("i40e: configure input fields for RSS or flow director")
> Fixes: 92cf7f8ec082 ("i40e: allow filtering on more IP header fields")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com>

all regression cases passed.
Tested-by: Chen Lingli <linglix.chen@intel.com>
 

^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [dpdk-dev] [PATCH v3] net/i40e: fix inputset field mask
  2021-03-09  2:56     ` Chen, LingliX
@ 2021-03-24 11:38       ` Zhang, Qi Z
  0 siblings, 0 replies; 11+ messages in thread
From: Zhang, Qi Z @ 2021-03-24 11:38 UTC (permalink / raw)
  To: Chen, LingliX, Zhang, AlvinX, Guo, Jia, Xing, Beilei, Zhou, JunX W
  Cc: dev, Zhang, AlvinX, stable



> -----Original Message-----
> From: Chen, LingliX <linglix.chen@intel.com>
> Sent: Tuesday, March 9, 2021 10:57 AM
> To: Zhang, AlvinX <alvinx.zhang@intel.com>; Guo, Jia <jia.guo@intel.com>;
> Xing, Beilei <beilei.xing@intel.com>; Zhang, Qi Z <qi.z.zhang@intel.com>; Zhou,
> JunX W <junx.w.zhou@intel.com>
> Cc: dev@dpdk.org; Zhang, AlvinX <alvinx.zhang@intel.com>; stable@dpdk.org
> Subject: RE: [dpdk-dev] [PATCH v3] net/i40e: fix inputset field mask
> 
> > -----Original Message-----
> > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Alvin Zhang
> > Sent: Monday, March 1, 2021 3:06 PM
> > To: Guo, Jia <jia.guo@intel.com>; Xing, Beilei
> > <beilei.xing@intel.com>; Zhang, Qi Z <qi.z.zhang@intel.com>; Zhou,
> > JunX W <junx.w.zhou@intel.com>
> > Cc: dev@dpdk.org; Zhang, AlvinX <alvinx.zhang@intel.com>;
> > stable@dpdk.org
> > Subject: [dpdk-dev] [PATCH v3] net/i40e: fix inputset field mask
> >
> > The absolute field offsets of IPv4 or IPv6 header are related to
> > hardware configuration. The X710 and X722 have different hardware
> > configurations, and users can even modify the hardware configuration.
> > Therefore, The default values cannot be used when calculating mask offset.
> >
> > The following flows can be created on X722 NIC, but the packet will
> > not enter the queue 3:
> >   flow create 0 ingress pattern eth / ipv4 proto is 255  / end
> >   actions queue index 3 / end
> >   pkt = Ether()/IP(ttl=63, proto=255)/Raw('X'*40)
> >
> >   flow create 0 ingress pattern eth / ipv4 tos is 50 / udp / end
> >   actions queue index 3 / end
> >   pkt = Ether()/IP(tos=50)/UDP()/Raw('X'*40)
> >
> >   flow create 0 ingress pattern eth / ipv6 tc is 12 / udp / end
> >   actions queue index 3 / end
> >   pkt = Ether()/IPv6(tc=12,hlim=34,fl=0x98765)/UDP()/Raw('X'*40)
> >
> >   flow create 0 ingress pattern eth / ipv6 hop is 34 / end actions
> >   queue index 3 / end
> >   pkt = Ether()/IPv6(tc=12,hlim=34,fl=0x98765)/Raw('X'*40)
> >
> > This patch read the field offsets from the NIC and return the mask
> > register value.
> >
> > Fixes: 98f055707685 ("i40e: configure input fields for RSS or flow
> > director")
> > Fixes: 92cf7f8ec082 ("i40e: allow filtering on more IP header fields")
> > Cc: stable@dpdk.org
> >
> > Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com>
> 
> all regression cases passed.
> Tested-by: Chen Lingli <linglix.chen@intel.com>

Should be:
 
Lingli Chen <lingli.chen@intel.com>

Applied to dpdk-next-net-intel.

Thanks
Qi


^ permalink raw reply	[flat|nested] 11+ messages in thread

* [dpdk-dev] [PATCH] net/i40e: fix X722 FDIR field mask
@ 2021-01-29  1:56 Zhang,Alvin
  0 siblings, 0 replies; 11+ messages in thread
From: Zhang,Alvin @ 2021-01-29  1:56 UTC (permalink / raw)
  To: jia.guo, beilei.xing, qi.z.zhang; +Cc: dev

From: Alvin Zhang <alvinx.zhang@intel.com>

The absolute field offsets of IPv4 or IPv6 header are related to
hardware configuration. The X710 and X722 have different hardware
configurations, and users can even modify the hardware configuration.
Therefore, The default values cannot be used when calculating mask
offset.

commands and packets as below:
  flow create 0 ingress pattern eth / ipv4 proto is 255  / end
  actions queue index 2 / end
  pkt = Ether()/IP(ttl=63, proto=255)/Raw('X'*40)

  flow create 0 ingress pattern eth / ipv4 tos is 50 / udp / end
  actions queue index 2 / end
  pkt = Ether()/IP(tos=50)/UDP()/Raw('X'*40)

  flow create 0 ingress pattern eth / ipv6 tc is 12 / udp / end
  actions queue index 3 / end
  pkt = Ether()/IPv6(tc=12,hlim=34,fl=0x98765)/UDP()/Raw('X'*40)

  flow create 0 ingress pattern eth / ipv6 hop is 34 / end actions
  queue index 3 / end
  pkt = Ether()/IPv6(tc=12,hlim=34,fl=0x98765)/Raw('X'*40)

This patch read the field offsets from the NIC and return the
mask register value.

Fixes: 98f055707685 ("i40e: configure input fields for RSS or flow director")
Fixes: 92cf7f8ec082 ("i40e: allow filtering on more IP header fields")
Cc: stable@dpdk.org

Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com>
---
 drivers/net/i40e/i40e_ethdev.c | 158 +++++++++++++++++++++++++++++++----------
 drivers/net/i40e/i40e_ethdev.h |   4 +-
 drivers/net/i40e/i40e_flow.c   |   2 +-
 3 files changed, 125 insertions(+), 39 deletions(-)

diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 946994b..fedbcc9 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -202,12 +202,12 @@
 #define I40E_TRANSLATE_INSET 0
 #define I40E_TRANSLATE_REG   1
 
-#define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
-#define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
-#define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
-#define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
-#define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
-#define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
+#define I40E_INSET_IPV4_TOS_MASK        0x0000FF00UL
+#define I40E_INSET_IPv4_TTL_MASK        0x000000FFUL
+#define I40E_INSET_IPV4_PROTO_MASK      0x0000FF00UL
+#define I40E_INSET_IPV6_TC_MASK         0x0000F00FUL
+#define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x0000FF00UL
+#define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000000FFUL
 
 /* PCI offset for querying capability */
 #define PCI_DEV_CAP_REG            0xA4
@@ -220,6 +220,25 @@
 /* Bit mask of Extended Tag enable/disable */
 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 
+#define I40E_GLQF_PIT_IPV4_START	2
+#define I40E_GLQF_PIT_IPV4_COUNT	2
+#define I40E_GLQF_PIT_IPV6_START	4
+#define I40E_GLQF_PIT_IPV6_COUNT	2
+
+#define I40E_GLQF_PIT_SOURCE_OFF_GET(a)	\
+				(((a) & I40E_GLQF_PIT_SOURCE_OFF_MASK) >> \
+				 I40E_GLQF_PIT_SOURCE_OFF_SHIFT)
+
+#define I40E_GLQF_PIT_DEST_OFF_GET(a) \
+				(((a) & I40E_GLQF_PIT_DEST_OFF_MASK) >> \
+				 I40E_GLQF_PIT_DEST_OFF_SHIFT)
+
+#define I40E_GLQF_PIT_FSIZE_GET(a)	(((a) & I40E_GLQF_PIT_FSIZE_MASK) >> \
+					 I40E_GLQF_PIT_FSIZE_SHIFT)
+
+#define I40E_GLQF_PIT_BUILD(off, mask)	(((off) << 16) | (mask))
+#define I40E_FDIR_FIELD_OFFSET(a)	((a) >> 1)
+
 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 static int i40e_dev_configure(struct rte_eth_dev *dev);
@@ -9417,49 +9436,116 @@ i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
 	return val;
 }
 
+static int
+i40e_fd_get_field_offset(struct i40e_hw *hw, uint32_t pit_reg_start,
+			      uint32_t pit_reg_count, uint32_t hdr_off)
+{
+	const uint32_t pit_reg_end = pit_reg_start + pit_reg_count;
+	uint32_t field_off = I40E_FDIR_FIELD_OFFSET(hdr_off);
+	uint32_t i, reg_val, src_off, count;
+
+	for (i = pit_reg_start; i < pit_reg_end; i++) {
+		reg_val = i40e_read_rx_ctl(hw, I40E_GLQF_PIT(i));
+
+		src_off = I40E_GLQF_PIT_SOURCE_OFF_GET(reg_val);
+		count = I40E_GLQF_PIT_FSIZE_GET(reg_val);
+
+		if (src_off <= field_off && (src_off + count) > field_off)
+			break;
+	}
+
+	if (i >= pit_reg_end) {
+		PMD_DRV_LOG(ERR,
+			    "Hardware GLQF_PIT configuration does not support this field mask");
+		return -1;
+	}
+
+	return I40E_GLQF_PIT_DEST_OFF_GET(reg_val) + field_off - src_off;
+}
+
 int
-i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
+i40e_generate_inset_mask_reg(struct i40e_hw *hw, uint64_t inset,
+			     uint32_t *mask, uint8_t nb_elem)
 {
-	uint8_t i, idx = 0;
-	uint64_t inset_need_mask = inset;
+	static const uint64_t mask_inset[] = {
+		I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL,
+		I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT };
 
 	static const struct {
 		uint64_t inset;
 		uint32_t mask;
-	} inset_mask_map[] = {
-		{I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
-		{I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
-		{I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
-		{I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
-		{I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
-		{I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
-		{I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
-		{I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
+		uint32_t offset;
+	} inset_mask_offset_map[] = {
+		{ I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK,
+		  offsetof(struct rte_ipv4_hdr, type_of_service) },
+
+		{ I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK,
+		  offsetof(struct rte_ipv4_hdr, next_proto_id) },
+
+		{ I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK,
+		  offsetof(struct rte_ipv4_hdr, time_to_live) },
+
+		{ I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK,
+		  offsetof(struct rte_ipv6_hdr, vtc_flow) },
+
+		{ I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK,
+		  offsetof(struct rte_ipv6_hdr, proto) },
+
+		{ I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK,
+		  offsetof(struct rte_ipv6_hdr, hop_limits) },
 	};
 
-	if (!inset || !mask || !nb_elem)
+	uint32_t i;
+	int idx = 0;
+
+	assert(mask);
+	if (!inset)
 		return 0;
 
-	for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
+	for (i = 0; i < RTE_DIM(mask_inset); i++) {
 		/* Clear the inset bit, if no MASK is required,
 		 * for example proto + ttl
 		 */
-		if ((inset & inset_mask_map[i].inset) ==
-		     inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
-			inset_need_mask &= ~inset_mask_map[i].inset;
-		if (!inset_need_mask)
-			return 0;
+		if ((mask_inset[i] & inset) == mask_inset[i]) {
+			inset &= ~mask_inset[i];
+			if (!inset)
+				return 0;
+		}
 	}
-	for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
-		if ((inset_need_mask & inset_mask_map[i].inset) ==
-		    inset_mask_map[i].inset) {
-			if (idx >= nb_elem) {
-				PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
-				return -EINVAL;
-			}
-			mask[idx] = inset_mask_map[i].mask;
-			idx++;
+
+	for (i = 0; i < RTE_DIM(inset_mask_offset_map); i++) {
+		int offset, pit_start, pit_count;
+
+		if (!(inset_mask_offset_map[i].inset & inset))
+			continue;
+
+		if (inset_mask_offset_map[i].inset &
+		    (I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
+		     I40E_INSET_IPV4_TTL)) {
+			pit_start = I40E_GLQF_PIT_IPV4_START;
+			pit_count = I40E_GLQF_PIT_IPV4_COUNT;
+		} else {
+			pit_start = I40E_GLQF_PIT_IPV6_START;
+			pit_count = I40E_GLQF_PIT_IPV6_COUNT;
+		}
+
+		offset = inset_mask_offset_map[i].offset;
+		offset = i40e_fd_get_field_offset(hw, pit_start, pit_count,
+						  offset);
+
+		if (offset < 0)
+			return -EINVAL;
+
+		if (idx >= nb_elem) {
+			PMD_DRV_LOG(ERR,
+				    "FD_MASK configuration out of range %u",
+				    nb_elem);
+			return -ERANGE;
 		}
+
+		mask[idx] = I40E_GLQF_PIT_BUILD(offset,
+						inset_mask_offset_map[i].mask);
+		idx++;
 	}
 
 	return idx;
@@ -9513,7 +9599,7 @@ i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
 
 		input_set = i40e_get_default_input_set(pctype);
 
-		num = i40e_generate_inset_mask_reg(input_set, mask_reg,
+		num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
 						   I40E_INSET_MASK_NUM_REG);
 		if (num < 0)
 			return;
@@ -9593,7 +9679,7 @@ i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
 		inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
 		input_set |= pf->hash_input_set[pctype];
 	}
-	num = i40e_generate_inset_mask_reg(input_set, mask_reg,
+	num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
 					   I40E_INSET_MASK_NUM_REG);
 	if (num < 0)
 		return -EINVAL;
diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h
index 1e8f5d3..faf6896 100644
--- a/drivers/net/i40e/i40e_ethdev.h
+++ b/drivers/net/i40e/i40e_ethdev.h
@@ -1458,8 +1458,8 @@ void i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw,
 					     uint8_t enable);
 int i40e_validate_input_set(enum i40e_filter_pctype pctype,
 			    enum rte_filter_type filter, uint64_t inset);
-int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask,
-				 uint8_t nb_elem);
+int i40e_generate_inset_mask_reg(struct i40e_hw *hw, uint64_t inset,
+				 uint32_t *mask, uint8_t nb_elem);
 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input);
 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val);
 void i40e_check_write_global_reg(struct i40e_hw *hw,
diff --git a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.c
index 7fe760d..ac77cc3 100644
--- a/drivers/net/i40e/i40e_flow.c
+++ b/drivers/net/i40e/i40e_flow.c
@@ -2269,7 +2269,7 @@ static int i40e_flow_parse_l4_cloud_filter(struct rte_eth_dev *dev,
 	    !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
 		return 0;
 
-	num = i40e_generate_inset_mask_reg(input_set, mask_reg,
+	num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
 					   I40E_INSET_MASK_NUM_REG);
 	if (num < 0)
 		return -EINVAL;
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 11+ messages in thread

end of thread, other threads:[~2021-03-24 11:38 UTC | newest]

Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-01-29  2:09 [dpdk-dev] [PATCH] net/i40e: fix X722 FDIR field mask Zhang,Alvin
2021-01-29  3:34 ` Xing, Beilei
2021-01-29  3:46   ` Zhang, AlvinX
2021-01-29  5:11   ` Zhang, AlvinX
2021-01-29  3:54 ` Zhou, JunX W
2021-02-01  2:40 ` [dpdk-dev] [PATCH v2] net/i40e: fix inputset " Zhang,Alvin
2021-02-01  3:26   ` Xing, Beilei
2021-03-01  7:06   ` [dpdk-dev] [PATCH v3] " Alvin Zhang
2021-03-09  2:56     ` Chen, LingliX
2021-03-24 11:38       ` Zhang, Qi Z
  -- strict thread matches above, loose matches on Subject: below --
2021-01-29  1:56 [dpdk-dev] [PATCH] net/i40e: fix X722 FDIR " Zhang,Alvin

DPDK patches and discussions

This inbox may be cloned and mirrored by anyone:

	git clone --mirror https://inbox.dpdk.org/dev/0 dev/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 dev dev/ https://inbox.dpdk.org/dev \
		dev@dpdk.org
	public-inbox-index dev

Example config snippet for mirrors.
Newsgroup available over NNTP:
	nntp://inbox.dpdk.org/inbox.dpdk.dev


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git