From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1A0CD4404F; Wed, 12 Jun 2024 17:19:45 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8042142F1D; Wed, 12 Jun 2024 17:06:08 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mails.dpdk.org (Postfix) with ESMTP id A64C842F51 for ; Wed, 12 Jun 2024 17:06:06 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718204767; x=1749740767; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=t94qSLKHO2fGhTD7xhLfRfc46DYchuiE7OSlQLglCKQ=; b=fiNcNAM169cPHTD4FRY8nMhnSMxZ8sN5abu0S5+dlSXYulSE7lHSkWWn /RiusaPNSsbDT/KkA1TMJjkL8EZ4x0M2JE5UN3gAZIdYCRqGMHECdi5Ej m4x/llnuOJDr3yrrdKUuiMmWdNd8/Nc7Pdy+Xuh1I5RyNX60WxC2RB0nG Vsz+QeUhDfEdHOxYmsW+9ZmjYDRzWrP+k0k+FKZBq9aQ+72+XxdvMHnVu dkFqb3xZv8PgzI58UpVOR/EP0PN3nkSOD5BcoOcKRyx15kXzokbD5XzIh 2AQGG3iiujkpB42c/asSWi0S2ULgSKF9OiHH89JBBZbfoq8MzkNCNIZPH g==; X-CSE-ConnectionGUID: XwM9jQH2Tce3lBLfpxNK+g== X-CSE-MsgGUID: hhwZsZ2dSi2s9deog098yg== X-IronPort-AV: E=McAfee;i="6700,10204,11101"; a="32459848" X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="32459848" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2024 08:06:05 -0700 X-CSE-ConnectionGUID: Wg8jChaJReucPGYQXACIKQ== X-CSE-MsgGUID: dhRQH+jRSS2PBr9GoVeIlQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="39925797" Received: from silpixa00401119.ir.intel.com ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 12 Jun 2024 08:06:04 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Ian Stokes , bruce.richardson@intel.com, Sergey Temerkhanov Subject: [PATCH v2 102/148] net/ice/base: enable SB access explicitly before 1st PHY access Date: Wed, 12 Jun 2024 16:01:36 +0100 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: <20240430154014.1026-1-ian.stokes@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Ian Stokes Explicitly enable sideband device access before the first PHY access to avoid possible errors for ETH56G. Signed-off-by: Sergey Temerkhanov Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_ptp_hw.c | 38 +++++++++++++++++++++++-------- 1 file changed, 29 insertions(+), 9 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 645d47098d..1b4534d127 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -2227,6 +2227,33 @@ ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool bypass) return 0; } +/** + * ice_sb_access_ena_eth56g - Enable SB devices (PHY and others) access + * @hw: pointer to HW struct + * @enable: Enable or disable access + * + * Enable sideband devices (PHY and others) access. + */ +static void ice_sb_access_ena_eth56g(struct ice_hw *hw, bool enable) +{ + u32 regval; + + /* Enable reading and writing switch and PHY registers over the + * sideband queue. + */ +#define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1) +#define PF_SB_REM_DEV_CTL_PHY0 BIT(2) + regval = rd32(hw, PF_SB_REM_DEV_CTL); + if (enable) + regval |= (PF_SB_REM_DEV_CTL_SWITCH_READ | + PF_SB_REM_DEV_CTL_PHY0); + else + regval &= ~(PF_SB_REM_DEV_CTL_SWITCH_READ | + PF_SB_REM_DEV_CTL_PHY0); + + wr32(hw, PF_SB_REM_DEV_CTL, regval); +} + /** * ice_ptp_init_phc_eth56g - Perform E822 specific PHC initialization * @hw: pointer to HW struct @@ -2236,15 +2263,6 @@ ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool bypass) static int ice_ptp_init_phc_eth56g(struct ice_hw *hw) { int err = 0; - u32 regval; - - /* Enable reading switch and PHY registers over the sideband queue */ -#define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1) -#define PF_SB_REM_DEV_CTL_PHY0 BIT(2) - regval = rd32(hw, PF_SB_REM_DEV_CTL); - regval |= (PF_SB_REM_DEV_CTL_SWITCH_READ | - PF_SB_REM_DEV_CTL_PHY0); - wr32(hw, PF_SB_REM_DEV_CTL, regval); /* Initialize the Clock Generation Unit */ err = ice_init_cgu_e82x(hw); @@ -2285,6 +2303,8 @@ int ice_ptp_init_phy_model(struct ice_hw *hw) int err; u32 phy_rev; + ice_sb_access_ena_eth56g(hw, true); + err = ice_read_phy_eth56g_raw_lp(hw, PHY_REG_REVISION, &phy_rev, true); if (err) -- 2.43.0