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From: Anatoly Burakov <anatoly.burakov@intel.com>
To: dev@dpdk.org
Cc: Ian Stokes <ian.stokes@intel.com>, bruce.richardson@intel.com,
Sergey Temerkhanov <sergey.temerkhanov@intel.com>
Subject: [PATCH v2 102/148] net/ice/base: enable SB access explicitly before
1st PHY access
Date: Wed, 12 Jun 2024 16:01:36 +0100
Message-ID: <c31d50debe28cfbbcafb8196d558d401c61f77e3.1718204529.git.anatoly.burakov@intel.com>
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From: Ian Stokes <ian.stokes@intel.com>
Explicitly enable sideband device access before the first PHY access to avoid
possible errors for ETH56G.
Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
Signed-off-by: Ian Stokes <ian.stokes@intel.com>
---
drivers/net/ice/base/ice_ptp_hw.c | 38 +++++++++++++++++++++++--------
1 file changed, 29 insertions(+), 9 deletions(-)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c
index 645d47098d..1b4534d127 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -2227,6 +2227,33 @@ ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool bypass)
return 0;
}
+/**
+ * ice_sb_access_ena_eth56g - Enable SB devices (PHY and others) access
+ * @hw: pointer to HW struct
+ * @enable: Enable or disable access
+ *
+ * Enable sideband devices (PHY and others) access.
+ */
+static void ice_sb_access_ena_eth56g(struct ice_hw *hw, bool enable)
+{
+ u32 regval;
+
+ /* Enable reading and writing switch and PHY registers over the
+ * sideband queue.
+ */
+#define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1)
+#define PF_SB_REM_DEV_CTL_PHY0 BIT(2)
+ regval = rd32(hw, PF_SB_REM_DEV_CTL);
+ if (enable)
+ regval |= (PF_SB_REM_DEV_CTL_SWITCH_READ |
+ PF_SB_REM_DEV_CTL_PHY0);
+ else
+ regval &= ~(PF_SB_REM_DEV_CTL_SWITCH_READ |
+ PF_SB_REM_DEV_CTL_PHY0);
+
+ wr32(hw, PF_SB_REM_DEV_CTL, regval);
+}
+
/**
* ice_ptp_init_phc_eth56g - Perform E822 specific PHC initialization
* @hw: pointer to HW struct
@@ -2236,15 +2263,6 @@ ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool bypass)
static int ice_ptp_init_phc_eth56g(struct ice_hw *hw)
{
int err = 0;
- u32 regval;
-
- /* Enable reading switch and PHY registers over the sideband queue */
-#define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1)
-#define PF_SB_REM_DEV_CTL_PHY0 BIT(2)
- regval = rd32(hw, PF_SB_REM_DEV_CTL);
- regval |= (PF_SB_REM_DEV_CTL_SWITCH_READ |
- PF_SB_REM_DEV_CTL_PHY0);
- wr32(hw, PF_SB_REM_DEV_CTL, regval);
/* Initialize the Clock Generation Unit */
err = ice_init_cgu_e82x(hw);
@@ -2285,6 +2303,8 @@ int ice_ptp_init_phy_model(struct ice_hw *hw)
int err;
u32 phy_rev;
+ ice_sb_access_ena_eth56g(hw, true);
+
err = ice_read_phy_eth56g_raw_lp(hw, PHY_REG_REVISION, &phy_rev,
true);
if (err)
--
2.43.0