From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8DBADA04BC; Fri, 9 Oct 2020 02:05:08 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1CE141BCE5; Fri, 9 Oct 2020 02:05:07 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id E4DCE1BCDE for ; Fri, 9 Oct 2020 02:05:03 +0200 (CEST) IronPort-SDR: J8dBaBj/TWJGrNU+Ht03hzGX6V9SrLYlqg3/lAYUXr+mOhWHIWI+1Yi4zjVn3B1JIkqo/slTwo sJF0uCO6cQnw== X-IronPort-AV: E=McAfee;i="6000,8403,9768"; a="144744577" X-IronPort-AV: E=Sophos;i="5.77,352,1596524400"; d="scan'208";a="144744577" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2020 17:05:01 -0700 IronPort-SDR: WNGfpI4gaYmjORwGtLA3uaaeX/GvQlwUetQZjZXlROKVSR0fd72vM2hmAQpTGeX6PckP1gBilI t6HoHB1KBDgg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,352,1596524400"; d="scan'208";a="355567164" Received: from fmsmsx602.amr.corp.intel.com ([10.18.126.82]) by orsmga007.jf.intel.com with ESMTP; 08 Oct 2020 17:05:01 -0700 Received: from shsmsx601.ccr.corp.intel.com (10.109.6.141) by fmsmsx602.amr.corp.intel.com (10.18.126.82) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Thu, 8 Oct 2020 17:05:00 -0700 Received: from shsmsx601.ccr.corp.intel.com (10.109.6.141) by SHSMSX601.ccr.corp.intel.com (10.109.6.141) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Fri, 9 Oct 2020 08:04:59 +0800 Received: from shsmsx601.ccr.corp.intel.com ([10.109.6.141]) by SHSMSX601.ccr.corp.intel.com ([10.109.6.141]) with mapi id 15.01.1713.004; Fri, 9 Oct 2020 08:04:59 +0800 From: "Zhang, Qi Z" To: "Power, Ciara" , "dev@dpdk.org" CC: "Yang, Qiming" Thread-Topic: [PATCH v3 10/18] net/ice: add checks for max SIMD bitwidth Thread-Index: AQHWlyrEMh6r5Yv8/EW6fika74lUNamOcMJg Date: Fri, 9 Oct 2020 00:04:59 +0000 Message-ID: References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> <20200930130415.11211-11-ciara.power@intel.com> In-Reply-To: <20200930130415.11211-11-ciara.power@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.5.1.3 dlp-product: dlpe-windows x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v3 10/18] net/ice: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Power, Ciara > Sent: Wednesday, September 30, 2020 9:04 PM > To: dev@dpdk.org > Cc: Power, Ciara ; Yang, Qiming > ; Zhang, Qi Z > Subject: [PATCH v3 10/18] net/ice: add checks for max SIMD bitwidth >=20 > When choosing a vector path to take, an extra condition must be satisfied= to > ensure the max SIMD bitwidth allows for the CPU enabled path. >=20 > Cc: Qiming Yang > Cc: Qi Zhang >=20 > Signed-off-by: Ciara Power Acked-by: Qi Zhang > --- > drivers/net/ice/ice_rxtx.c | 20 ++++++++++++++------ > 1 file changed, 14 insertions(+), 6 deletions(-) >=20 > diff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c inde= x > fef6ad4544..5a29af743c 100644 > --- a/drivers/net/ice/ice_rxtx.c > +++ b/drivers/net/ice/ice_rxtx.c > @@ -2936,7 +2936,9 @@ ice_set_rx_function(struct rte_eth_dev *dev) > bool use_avx2 =3D false; >=20 > if (rte_eal_process_type() =3D=3D RTE_PROC_PRIMARY) { > - if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed) { > + if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed && > + rte_get_max_simd_bitwidth() > + >=3D RTE_MAX_128_SIMD) { > ad->rx_vec_allowed =3D true; > for (i =3D 0; i < dev->data->nb_rx_queues; i++) { > rxq =3D dev->data->rx_queues[i]; > @@ -2946,8 +2948,10 @@ ice_set_rx_function(struct rte_eth_dev *dev) > } > } >=20 > - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) =3D=3D 1 || > - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) =3D=3D 1) > + if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) =3D=3D 1 || > + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) =3D=3D 1) && > + rte_get_max_simd_bitwidth() > + >=3D RTE_MAX_256_SIMD) > use_avx2 =3D true; >=20 > } else { > @@ -3114,7 +3118,9 @@ ice_set_tx_function(struct rte_eth_dev *dev) > bool use_avx2 =3D false; >=20 > if (rte_eal_process_type() =3D=3D RTE_PROC_PRIMARY) { > - if (!ice_tx_vec_dev_check(dev)) { > + if (!ice_tx_vec_dev_check(dev) && > + rte_get_max_simd_bitwidth() > + >=3D RTE_MAX_128_SIMD) { > ad->tx_vec_allowed =3D true; > for (i =3D 0; i < dev->data->nb_tx_queues; i++) { > txq =3D dev->data->tx_queues[i]; > @@ -3124,8 +3130,10 @@ ice_set_tx_function(struct rte_eth_dev *dev) > } > } >=20 > - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) =3D=3D 1 || > - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) =3D=3D 1) > + if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) =3D=3D 1 || > + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) =3D=3D 1) && > + rte_get_max_simd_bitwidth() > + >=3D RTE_MAX_256_SIMD) > use_avx2 =3D true; >=20 > } else { > -- > 2.17.1