From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 702F9A0C45; Thu, 13 May 2021 02:51:58 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E45484067E; Thu, 13 May 2021 02:51:57 +0200 (CEST) Received: from szxga03-in.huawei.com (szxga03-in.huawei.com [45.249.212.189]) by mails.dpdk.org (Postfix) with ESMTP id A3CA84003F for ; Thu, 13 May 2021 02:51:56 +0200 (CEST) Received: from dggeml703-chm.china.huawei.com (unknown [172.30.72.56]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4FgY1V3c1Tz60L5; Thu, 13 May 2021 08:48:30 +0800 (CST) Received: from dggpeml500024.china.huawei.com (7.185.36.10) by dggeml703-chm.china.huawei.com (10.3.17.136) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Thu, 13 May 2021 08:51:53 +0800 Received: from [127.0.0.1] (10.40.190.165) by dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 13 May 2021 08:51:53 +0800 To: Honnappa Nagarahalli , "thomas@monjalon.net" , "ferruh.yigit@intel.com" CC: "dev@dpdk.org" , "jerinj@marvell.com" , Ruifeng Wang , "viktorin@rehivetech.com" , "bruce.richardson@intel.com" , nd References: <1620808126-18876-1-git-send-email-fengchengwen@huawei.com> <1620808126-18876-3-git-send-email-fengchengwen@huawei.com> From: fengchengwen Message-ID: Date: Thu, 13 May 2021 08:51:52 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.40.190.165] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggpeml500024.china.huawei.com (7.185.36.10) X-CFilter-Loop: Reflected Subject: Re: [dpdk-dev] [PATCH 2/2] net/hns3: refactor SVE code compile method X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 2021/5/13 7:21, Honnappa Nagarahalli wrote: > > >> >>> >>> Currently, the SVE code is compiled only when -march supports SVE >>> (e.g. '- march=armv8.2a+sve'), there maybe some problem[1] with this >> approach. >>> >>> The solution: >>> a. If the minimum instruction set support SVE then compiles it. >>> b. Else if the compiler support SVE then compiles it. >>> c. Otherwise don't compile it. >>> >>> [1] https://mails.dpdk.org/archives/dev/2021-April/208189.html >>> >>> Fixes: 8c25b02b082a ("net/hns3: fix enabling SVE Rx/Tx") >>> Fixes: 952ebacce4f2 ("net/hns3: support SVE Rx") >>> Cc: stable@dpdk.org >>> >>> Signed-off-by: Chengwen Feng >>> --- >>> drivers/net/hns3/hns3_rxtx.c | 2 +- >>> drivers/net/hns3/meson.build | 13 +++++++++++++ >>> 2 files changed, 14 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/net/hns3/hns3_rxtx.c >>> b/drivers/net/hns3/hns3_rxtx.c index >>> 1d7a769..4ef20c6 100644 >>> --- a/drivers/net/hns3/hns3_rxtx.c >>> +++ b/drivers/net/hns3/hns3_rxtx.c >>> @@ -2808,7 +2808,7 @@ hns3_get_default_vec_support(void) >>> static bool >>> hns3_get_sve_support(void) >>> { >>> -#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_SVE) >>> +#if defined(CC_SVE_SUPPORT) >>> if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_256) >>> return false; >>> if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE)) >>> diff --git a/drivers/net/hns3/meson.build >>> b/drivers/net/hns3/meson.build index >>> 53c7df7..8563d70 100644 >>> --- a/drivers/net/hns3/meson.build >>> +++ b/drivers/net/hns3/meson.build >>> @@ -35,7 +35,20 @@ deps += ['hash'] >>> >>> if arch_subdir == 'arm' and dpdk_conf.get('RTE_ARCH_64') >>> sources += files('hns3_rxtx_vec.c') >>> + >>> + # compile SVE when: >>> + # a. support SVE in minimum instruction set baseline >>> + # b. it's not minimum instruction set, but compiler support >>> if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' >>> + cflags += ['-DCC_SVE_SUPPORT'] >> Why is the CC_SVE_SUPPORT flag needed? The compiler has >> __ARM_FEATURE_SVE flag already which gets defined when '+sve" is added to >> '-march'. >> The CC_SVE_SUPPORT is used to implement the hns3_get_sve_support API (below), this API located in another file which is hns3_rxtx.c, and this file was compiled with default machine_args. static bool hns3_get_sve_support(void) { #if defined(CC_SVE_SUPPORT) if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_256) return false; if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE)) return true; #endif return false; } If the machine_args doesn't support SVE but compiler support, we will compile SVE code too, so in this case we need define CC_SVE_SUPPORT, so that in runtime we could try judge whether support SVE. In this case, __ARM_FEATURE_SVE was not defined because it is in hns3_rxtx.c which use default machine_args. If the machine_args supports SVE we sure compile SVE code, in this case, to maintain consistency, we also define this macro. >>> sources += files('hns3_rxtx_vec_sve.c') >>> + elif cc.has_argument('-march=armv8.2-a+sve') >> I think this check and the above check do the same thing. i.e. both of them >> check if +sve flag is passed to the compiler. >> Yes it is. >>> + cflags += ['-DCC_SVE_SUPPORT'] >>> + hns3_sve_lib = static_library('hns3_sve_lib', >>> + 'hns3_rxtx_vec_sve.c', >>> + dependencies: [static_rte_ethdev], >>> + include_directories: includes, >>> + c_args: [cflags, '-march=armv8.2-a+sve']) >>> + objs += hns3_sve_lib.extract_objects('hns3_rxtx_vec_sve.c') > I do not understand the need of this block of code, appreciate if you could explain why this is required. > This is typical usage for compiling some soure file with custom flags (here is '-march=armv8.2-a+sve') Please ref [1] with keyword 'extract_objects' [1] https://mesonbuild.com/Reference-manual.html >>> endif >>> endif >>> -- >>> 2.8.1 > > > . >