From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 61783A04B5; Mon, 26 Oct 2020 08:14:43 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2BF2B1E2B; Mon, 26 Oct 2020 08:14:42 +0100 (CET) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id 758021D9E; Mon, 26 Oct 2020 08:14:39 +0100 (CET) IronPort-SDR: fivmvg0TL7mT31jVEvSJyujz93X137Q7imZFzp3gS9EKco68WQsh+6hP7SpfflC+IM2TsEbVdX ezYg7Rl1hvng== X-IronPort-AV: E=McAfee;i="6000,8403,9785"; a="147742800" X-IronPort-AV: E=Sophos;i="5.77,417,1596524400"; d="scan'208";a="147742800" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Oct 2020 00:14:34 -0700 IronPort-SDR: TOHqvj5QtCN+eICrQ13IfT2TM4D5GbEsDcDk4k0MQFSRtG+kxPBx0kjYeUkfZWZkV6MJWa2aUA hWMc4t4hFJrg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,417,1596524400"; d="scan'208";a="303326757" Received: from fmsmsx603.amr.corp.intel.com ([10.18.126.83]) by fmsmga008.fm.intel.com with ESMTP; 26 Oct 2020 00:14:34 -0700 Received: from shsmsx606.ccr.corp.intel.com (10.109.6.216) by fmsmsx603.amr.corp.intel.com (10.18.126.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Mon, 26 Oct 2020 00:14:33 -0700 Received: from shsmsx601.ccr.corp.intel.com (10.109.6.141) by SHSMSX606.ccr.corp.intel.com (10.109.6.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Mon, 26 Oct 2020 15:14:32 +0800 Received: from shsmsx601.ccr.corp.intel.com ([10.109.6.141]) by SHSMSX601.ccr.corp.intel.com ([10.109.6.141]) with mapi id 15.01.1713.004; Mon, 26 Oct 2020 15:14:32 +0800 From: "Guo, Jia" To: "Xing, Beilei" , "dev@dpdk.org" CC: "stable@dpdk.org" Thread-Topic: [PATCH] net/i40e: fix FDIR issue for ETH + VLAN pattern Thread-Index: AQHWqEw1yWhQm5Bes02Jhj06cXvuP6mqfDCA//8CetA= Date: Mon, 26 Oct 2020 07:14:32 +0000 Message-ID: References: <20201023081509.13087-1-beilei.xing@intel.com> <20201027062147.100445-1-beilei.xing@intel.com> In-Reply-To: <20201027062147.100445-1-beilei.xing@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] net/i40e: fix FDIR issue for ETH + VLAN pattern X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Acked-by: Jeff Guo > -----Original Message----- > From: Xing, Beilei > Sent: Tuesday, October 27, 2020 2:22 PM > To: dev@dpdk.org > Cc: Guo, Jia ; Xing, Beilei ; > stable@dpdk.org > Subject: [PATCH] net/i40e: fix FDIR issue for ETH + VLAN pattern >=20 > From: Beilei Xing >=20 > Currently, can't create more than one following flow for ETH + VLAN patte= rn. >=20 > 1. flow create 0 ingress pattern eth / vlan vid is 350 / end > actions queue index 2 / end > 2. flow create 0 ingress pattern eth / vlan vid is 351 / end > actions queue index 3 / end >=20 > The root cause is the vlan_tci is not set correctly, it will cause the k= eys of > both of the two flows are the same. >=20 > Fixes: 42044b69c67d ("net/i40e: support input set selection for FDIR") > Cc: stable@dpdk.org >=20 > Signed-off-by: Beilei Xing > --- > drivers/net/i40e/i40e_flow.c | 35 ++++++++++++++++++++++++----------- > 1 file changed, 24 insertions(+), 11 deletions(-) >=20 > diff --git a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.c > index 8e7a9989b3..5bec0c7a84 100644 > --- a/drivers/net/i40e/i40e_flow.c > +++ b/drivers/net/i40e/i40e_flow.c > @@ -27,7 +27,10 @@ > #define I40E_IPV6_TC_MASK (0xFF << I40E_FDIR_IPv6_TC_OFFSET) > #define I40E_IPV6_FRAG_HEADER 44 > #define I40E_TENANT_ARRAY_NUM 3 > -#define I40E_TCI_MASK 0xFFFF > +#define I40E_VLAN_TCI_MASK 0xFFFF > +#define I40E_VLAN_PRI_MASK 0xE000 > +#define I40E_VLAN_CFI_MASK 0x1000 > +#define I40E_VLAN_VID_MASK 0x0FFF >=20 > static int i40e_flow_validate(struct rte_eth_dev *dev, > const struct rte_flow_attr *attr, @@ -2705,12 > +2708,22 @@ i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev, >=20 > RTE_ASSERT(!(input_set & > I40E_INSET_LAST_ETHER_TYPE)); > if (vlan_spec && vlan_mask) { > - if (vlan_mask->tci =3D=3D > - rte_cpu_to_be_16(I40E_TCI_MASK)) { > - input_set |=3D > I40E_INSET_VLAN_INNER; > - filter->input.flow_ext.vlan_tci =3D > - vlan_spec->tci; > + if (vlan_mask->tci !=3D > + rte_cpu_to_be_16(I40E_VLAN_TCI_MASK) > && > + vlan_mask->tci !=3D > + rte_cpu_to_be_16(I40E_VLAN_PRI_MASK) > && > + vlan_mask->tci !=3D > + rte_cpu_to_be_16(I40E_VLAN_CFI_MASK) > && > + vlan_mask->tci !=3D > + > rte_cpu_to_be_16(I40E_VLAN_VID_MASK)) { > + rte_flow_error_set(error, EINVAL, > + > RTE_FLOW_ERROR_TYPE_ITEM, > + item, > + "Unsupported TCI mask."); > } > + input_set |=3D I40E_INSET_VLAN_INNER; > + filter->input.flow_ext.vlan_tci =3D > + vlan_spec->tci; > } > if (vlan_spec && vlan_mask && vlan_mask- > >inner_type) { > if (vlan_mask->inner_type !=3D > RTE_BE16(0xffff)) { @@ -3894,10 +3907,10 @@ > i40e_flow_parse_vxlan_pattern(__rte_unused struct rte_eth_dev *dev, >=20 > if (vlan_spec && vlan_mask) { > if (vlan_mask->tci =3D=3D > - rte_cpu_to_be_16(I40E_TCI_MASK)) > + rte_cpu_to_be_16(I40E_VLAN_TCI_MASK)) > filter->inner_vlan =3D > rte_be_to_cpu_16(vlan_spec->tci) > & > - I40E_TCI_MASK; > + I40E_VLAN_TCI_MASK; > filter_type |=3D ETH_TUNNEL_FILTER_IVLAN; > } > break; > @@ -4125,10 +4138,10 @@ i40e_flow_parse_nvgre_pattern(__rte_unused > struct rte_eth_dev *dev, >=20 > if (vlan_spec && vlan_mask) { > if (vlan_mask->tci =3D=3D > - rte_cpu_to_be_16(I40E_TCI_MASK)) > + rte_cpu_to_be_16(I40E_VLAN_TCI_MASK)) > filter->inner_vlan =3D > rte_be_to_cpu_16(vlan_spec->tci) > & > - I40E_TCI_MASK; > + I40E_VLAN_TCI_MASK; > filter_type |=3D ETH_TUNNEL_FILTER_IVLAN; > } > break; > @@ -4800,7 +4813,7 @@ i40e_flow_parse_rss_pattern(__rte_unused struct > rte_eth_dev *dev, > vlan_mask =3D item->mask; > if (vlan_spec && vlan_mask) { > if (vlan_mask->tci =3D=3D > - rte_cpu_to_be_16(I40E_TCI_MASK)) > { > + > rte_cpu_to_be_16(I40E_VLAN_TCI_MASK)) { > info->region[0].user_priority[0] =3D > (rte_be_to_cpu_16( > vlan_spec->tci) >> 13) & 0x7; > -- > 2.26.2