From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 24FBB45500; Wed, 26 Jun 2024 13:56:33 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EA3B3432D2; Wed, 26 Jun 2024 13:55:11 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by mails.dpdk.org (Postfix) with ESMTP id CD50942E95; Wed, 26 Jun 2024 13:43:25 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719402206; x=1750938206; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yD2zfhrtArch0AtuxwUaV1cf03PU6WgEaGZVgQbXA7s=; b=YY+Yq1nFtXoFCta7bZV8FEYLmag1SJMip3hqOsVTfQhsqrdrEBd8ccaI QI1Omrozjh5nwWHfgiWnSwrGpNg4BOmsVK7gzeXcKs4Em8Tfc6Vq+MUlG NdPiZf5yPb/P8zQ6TU0YMbEm3YaWnzHocKka6pveDaAWDQFnQWu4eJzcp VimTsK4NbIOLZbvycFg+PHvh48aoxlNTQdNsBfhTVJduCw6x71yzR9+/0 kekWT13pl9Bl1WPUtKD3peF20e5XNViQ2cEknEo6FkL0liwAIyntjpHkZ pp3lRTOVJGiN2xIGJhxzgLgbeC5lQ7x4RYl6q/nyrEXR3Zoq+yur9dRPV g==; X-CSE-ConnectionGUID: 96VD1gGnTh6lK0oBSAFJPg== X-CSE-MsgGUID: m2VrMnTdRwmsfPV2UiQh/g== X-IronPort-AV: E=McAfee;i="6700,10204,11114"; a="38979320" X-IronPort-AV: E=Sophos;i="6.08,266,1712646000"; d="scan'208";a="38979320" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jun 2024 04:43:25 -0700 X-CSE-ConnectionGUID: fOlG7ly+SFyUgI1i7xXOEw== X-CSE-MsgGUID: ASvGdVZAQlSngT9lpcW6fw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,266,1712646000"; d="scan'208";a="43873518" Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167]) by orviesa010.jf.intel.com with ESMTP; 26 Jun 2024 04:43:23 -0700 From: Anatoly Burakov To: dev@dpdk.org, Paul M Stillwell Jr , Qi Zhang , Dan Nowlin , Xiaolong Ye Cc: Jesse Brandeburg , ian.stokes@intel.com, bruce.richardson@intel.com, stable@dpdk.org Subject: [PATCH v4 015/103] net/ice/base: fix sign-extension Date: Wed, 26 Jun 2024 12:41:03 +0100 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Jesse Brandeburg Fix a static analysis warning where if the 16-bit value in mask has the high-bit set, it will be sign extended by the shift left (which converts it to a signed integer). Avoid this by casting to a u32 to make sure the conversion happens before the shift and that it stays unsigned. Fixes: 9467486f179f ("net/ice/base: enable masking for RSS and FD field vectors") Cc: qi.z.zhang@intel.com Cc: stable@dpdk.org Signed-off-by: Jesse Brandeburg Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_flex_pipe.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index e06dbb0885..413b6f8ece 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -1534,16 +1534,14 @@ ice_write_prof_mask_reg(struct ice_hw *hw, enum ice_block blk, u16 mask_idx, switch (blk) { case ICE_BLK_RSS: offset = GLQF_HMASK(mask_idx); - val = (idx << GLQF_HMASK_MSK_INDEX_S) & - GLQF_HMASK_MSK_INDEX_M; - val |= (mask << GLQF_HMASK_MASK_S) & GLQF_HMASK_MASK_M; + val = (idx << GLQF_HMASK_MSK_INDEX_S) & GLQF_HMASK_MSK_INDEX_M; + val |= ((u32)mask << GLQF_HMASK_MASK_S) & GLQF_HMASK_MASK_M; break; case ICE_BLK_FD: offset = GLQF_FDMASK(mask_idx); val = (idx << GLQF_FDMASK_MSK_INDEX_S) & GLQF_FDMASK_MSK_INDEX_M; - val |= (mask << GLQF_FDMASK_MASK_S) & - GLQF_FDMASK_MASK_M; + val |= ((u32)mask << GLQF_FDMASK_MASK_S) & GLQF_FDMASK_MASK_M; break; default: ice_debug(hw, ICE_DBG_PKG, "No profile masks for block %d\n", -- 2.43.0