From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id CBD581B322 for ; Thu, 2 Nov 2017 04:36:17 +0100 (CET) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Nov 2017 20:36:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,331,1505804400"; d="scan'208";a="1032439823" Received: from tanjianf-mobl.ccr.corp.intel.com (HELO [10.239.200.77]) ([10.239.200.77]) by orsmga003.jf.intel.com with ESMTP; 01 Nov 2017 20:36:14 -0700 To: Zhiyong Yang , dev@dpdk.org References: <20171031094456.24912-1-zhiyong.yang@intel.com> Cc: yliu@fridaylinux.org, maxime.coquelin@redhat.com From: "Tan, Jianfeng" Message-ID: Date: Thu, 2 Nov 2017 11:36:14 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: <20171031094456.24912-1-zhiyong.yang@intel.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [dpdk-dev] [PATCH] net/virtio: fix use_msix get the wrong value X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 02 Nov 2017 03:36:18 -0000 On 10/31/2017 5:44 PM, Zhiyong Yang wrote: > When running l3fwd-power to test virtio rxq interrupt using vfio > pci noiommu mode, startup fails. In the function virtio_read_caps, > the code if (flags & PCI_MSIX_ENABLE) intends to double check > if vfio msix is enabled or not. However, it is indeed not valid. > Come back to l3fwd-power, use_msix is not assigned to the right > value "1". The patch fixes the issue. > > Fixes: cb482cb3a305 ("net/virtio: fix MAC address read") > Signed-off-by: Zhiyong Yang > --- > drivers/net/virtio/virtio_pci.c | 11 +---------- > 1 file changed, 1 insertion(+), 10 deletions(-) > > diff --git a/drivers/net/virtio/virtio_pci.c b/drivers/net/virtio/virtio_pci.c > index 55b717c03..be5b07a58 100644 > --- a/drivers/net/virtio/virtio_pci.c > +++ b/drivers/net/virtio/virtio_pci.c > @@ -580,8 +580,6 @@ get_cfg_addr(struct rte_pci_device *dev, struct virtio_pci_cap *cap) > return base + offset; > } > > -#define PCI_MSIX_ENABLE 0x8000 > - > static int > virtio_read_caps(struct rte_pci_device *dev, struct virtio_hw *hw) > { > @@ -609,14 +607,7 @@ virtio_read_caps(struct rte_pci_device *dev, struct virtio_hw *hw) > } > > if (cap.cap_vndr == PCI_CAP_ID_MSIX) { > - /* Transitional devices would also have this capability, > - * that's why we also check if msix is enabled. > - * 1st byte is cap ID; 2nd byte is the position of next > - * cap; next two bytes are the flags. > - */ > - uint16_t flags = ((uint16_t *)&cap)[1]; > - > - if (flags & PCI_MSIX_ENABLE) > + if (dev->intr_handle.type == RTE_INTR_HANDLE_VFIO_MSIX) > hw->use_msix = 1; > } > The real issue is that, if vfio (noiommu) is used, msix enable (rte_intr_enable) is after the msix detection. IMO, we shall try to move msix enable ahead for virtio. - igb_uio do that in the open(). - uio_pci_generic does not. - vfio-pci does not. For previous fix on mmio position adjustment, we might need to change to ask if msix is enabled each time. Thanks, Jianfeng