From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3CDC3A0506; Wed, 13 Apr 2022 08:13:12 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CF6EA4069D; Wed, 13 Apr 2022 08:13:11 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 473254068B for ; Wed, 13 Apr 2022 08:13:10 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 23D5O7lL008778; Tue, 12 Apr 2022 23:13:08 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=pfpt0220; bh=Pz9VkXV2NY1HZhtAt7NDzL+aToGuj+QToPZITpu6Wwk=; b=j5mNhV00LAxSuIHgKV7YtxZGkfhX1Lw8DKsfyILO7v+ud55npz5KDM8KhTayyf9wvZ5h 5oGg8E/nDdsoS/zqqwQxsNcvpVeJTXHEyjbMahbalr85hA76QgmHqVCT+LWy3LJ/30Xh s/gXjsf1GM8Ri2Nku6LzMG5lqR6q5/jta/knoCzGVvWe+CylDNar3SZFfYabsNFHLIjg VQzKvhsuwfU6ZLHyniz/O5usmDNVIePxjBDvpvn5QuLGtZ7v9kp6/LGRPWwCK5HWo6uW RrwHxsCe2tHnnGRrIeaCyKMUApTuLL64sk3UGmjZWQO9XTTiAzj03WqIq5sRkNGyvldW ow== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3fd6nfcx5e-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 12 Apr 2022 23:13:07 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 12 Apr 2022 23:13:06 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 12 Apr 2022 23:13:06 -0700 Received: from [10.28.175.194] (PE-LT1350.marvell.com [10.28.175.194]) by maili.marvell.com (Postfix) with ESMTP id DC7993F705C; Tue, 12 Apr 2022 23:13:04 -0700 (PDT) Message-ID: Date: Wed, 13 Apr 2022 11:43:03 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.8.0 Subject: Re: [PATCH 1/7] examples/ipsec-secgw: disable Tx chksum offload for inline Content-Language: en-US To: , Radu Nicolau , Akhil Goyal CC: , References: <20220322175902.363520-1-ndabilpuram@marvell.com> From: Nithin Kumar Dabilpuram In-Reply-To: <20220322175902.363520-1-ndabilpuram@marvell.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: ib_shIFeXaBF8MsjrXl75DYFkFOewk2X X-Proofpoint-ORIG-GUID: ib_shIFeXaBF8MsjrXl75DYFkFOewk2X X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-04-12_06,2022-04-12_02,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Ping. On 3/22/22 11:28 PM, Nithin Dabilpuram wrote: > Enable Tx IPv4 checksum offload only when Tx inline crypto, lookaside > crypto/protocol or cpu crypto is needed. > For Tx Inline protocol offload, checksum computation > is implicitly taken care by HW. > > Signed-off-by: Nithin Dabilpuram > --- > examples/ipsec-secgw/ipsec-secgw.c | 3 --- > examples/ipsec-secgw/sa.c | 32 +++++++++++++++++++++++++------- > 2 files changed, 25 insertions(+), 10 deletions(-) > > diff --git a/examples/ipsec-secgw/ipsec-secgw.c b/examples/ipsec-secgw/ipsec-secgw.c > index 42b5081..76919e5 100644 > --- a/examples/ipsec-secgw/ipsec-secgw.c > +++ b/examples/ipsec-secgw/ipsec-secgw.c > @@ -2330,9 +2330,6 @@ port_init(uint16_t portid, uint64_t req_rx_offloads, uint64_t req_tx_offloads) > local_port_conf.txmode.offloads |= > RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; > > - if (dev_info.tx_offload_capa & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM) > - local_port_conf.txmode.offloads |= RTE_ETH_TX_OFFLOAD_IPV4_CKSUM; > - > printf("port %u configuring rx_offloads=0x%" PRIx64 > ", tx_offloads=0x%" PRIx64 "\n", > portid, local_port_conf.rxmode.offloads, > diff --git a/examples/ipsec-secgw/sa.c b/examples/ipsec-secgw/sa.c > index 1839ac7..36d890f 100644 > --- a/examples/ipsec-secgw/sa.c > +++ b/examples/ipsec-secgw/sa.c > @@ -1785,13 +1785,31 @@ sa_check_offloads(uint16_t port_id, uint64_t *rx_offloads, > for (idx_sa = 0; idx_sa < nb_sa_out; idx_sa++) { > rule = &sa_out[idx_sa]; > rule_type = ipsec_get_action_type(rule); > - if ((rule_type == RTE_SECURITY_ACTION_TYPE_INLINE_CRYPTO || > - rule_type == > - RTE_SECURITY_ACTION_TYPE_INLINE_PROTOCOL) > - && rule->portid == port_id) { > - *tx_offloads |= RTE_ETH_TX_OFFLOAD_SECURITY; > - if (rule->mss) > - *tx_offloads |= RTE_ETH_TX_OFFLOAD_TCP_TSO; > + switch (rule_type) { > + case RTE_SECURITY_ACTION_TYPE_INLINE_PROTOCOL: > + /* Checksum offload is not needed for inline protocol as > + * all processing for Outbound IPSec packets will be > + * implicitly taken care and for non-IPSec packets, > + * there is no need of IPv4 Checksum offload. > + */ > + if (rule->portid == port_id) > + *tx_offloads |= RTE_ETH_TX_OFFLOAD_SECURITY; > + break; > + case RTE_SECURITY_ACTION_TYPE_INLINE_CRYPTO: > + if (rule->portid == port_id) { > + *tx_offloads |= RTE_ETH_TX_OFFLOAD_SECURITY; > + if (rule->mss) > + *tx_offloads |= > + RTE_ETH_TX_OFFLOAD_TCP_TSO; > + *tx_offloads |= RTE_ETH_TX_OFFLOAD_IPV4_CKSUM; > + } > + break; > + default: > + /* Enable IPv4 checksum offload even if one of lookaside > + * SA's are present. > + */ > + *tx_offloads |= RTE_ETH_TX_OFFLOAD_IPV4_CKSUM; > + break; > } > } > return 0;