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[24.205.208.113]) by smtp.gmail.com with ESMTPSA id k22-20020a05620a415600b006b4880b08a9sm7172780qko.88.2022.07.07.06.20.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 07 Jul 2022 06:21:00 -0700 (PDT) Subject: Re: [PATCH v4 4/7] drivers/baseband: update PMDs to expose queue per operation To: "Chautru, Nicolas" , "dev@dpdk.org" , "thomas@monjalon.net" , "gakhil@marvell.com" , "hemant.agrawal@nxp.com" Cc: "maxime.coquelin@redhat.com" , "mdr@ashroe.eu" , "Richardson, Bruce" , "david.marchand@redhat.com" , "stephen@networkplumber.org" References: <1655491040-183649-6-git-send-email-nicolas.chautru@intel.com> <1657067022-54373-1-git-send-email-nicolas.chautru@intel.com> <1657067022-54373-5-git-send-email-nicolas.chautru@intel.com> From: Tom Rix Message-ID: Date: Thu, 7 Jul 2022 06:20:57 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.1 MIME-Version: 1.0 In-Reply-To: Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=trix@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On 7/6/22 2:10 PM, Chautru, Nicolas wrote: > Hi Tom, > >> -----Original Message----- >> From: Tom Rix >> Sent: Wednesday, July 6, 2022 9:15 AM >> To: Chautru, Nicolas ; dev@dpdk.org; >> thomas@monjalon.net; gakhil@marvell.com; hemant.agrawal@nxp.com >> Cc: maxime.coquelin@redhat.com; mdr@ashroe.eu; Richardson, Bruce >> ; david.marchand@redhat.com; >> stephen@networkplumber.org >> Subject: Re: [PATCH v4 4/7] drivers/baseband: update PMDs to expose queue >> per operation >> >> >> On 7/5/22 5:23 PM, Nicolas Chautru wrote: >>> Add support in existing bbdev PMDs for the explicit number of queue >>> and priority for each operation type configured on the device. >>> >>> Signed-off-by: Nicolas Chautru >>> --- >>> drivers/baseband/acc100/rte_acc100_pmd.c | 29 +++++++++++++------ >> --- >>> drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c | 8 ++++++ >>> drivers/baseband/fpga_lte_fec/fpga_lte_fec.c | 8 ++++++ >>> drivers/baseband/la12xx/bbdev_la12xx.c | 7 ++++++ >>> drivers/baseband/turbo_sw/bbdev_turbo_software.c | 11 ++++++++ >>> 5 files changed, 51 insertions(+), 12 deletions(-) >>> >>> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c >>> b/drivers/baseband/acc100/rte_acc100_pmd.c >>> index 17ba798..d568d0d 100644 >>> --- a/drivers/baseband/acc100/rte_acc100_pmd.c >>> +++ b/drivers/baseband/acc100/rte_acc100_pmd.c >>> @@ -966,6 +966,7 @@ >>> struct rte_bbdev_driver_info *dev_info) >>> { >>> struct acc100_device *d = dev->data->dev_private; >>> + int i; >>> >>> static const struct rte_bbdev_op_cap bbdev_capabilities[] = { >>> { >>> @@ -1062,19 +1063,23 @@ >>> fetch_acc100_config(dev); >>> dev_info->device_status = RTE_BBDEV_DEV_NOT_SUPPORTED; >>> >>> - /* This isn't ideal because it reports the maximum number of queues >> but >>> - * does not provide info on how many can be uplink/downlink or >> different >>> - * priorities >>> - */ >>> - dev_info->max_num_queues = >>> - d->acc100_conf.q_dl_5g.num_aqs_per_groups * >>> - d->acc100_conf.q_dl_5g.num_qgroups + >>> - d->acc100_conf.q_ul_5g.num_aqs_per_groups * >>> - d->acc100_conf.q_ul_5g.num_qgroups + >>> - d->acc100_conf.q_dl_4g.num_aqs_per_groups * >>> - d->acc100_conf.q_dl_4g.num_qgroups + >>> - d->acc100_conf.q_ul_4g.num_aqs_per_groups * >>> + /* Expose number of queues */ >>> + dev_info->num_queues[RTE_BBDEV_OP_NONE] = 0; >>> + dev_info->num_queues[RTE_BBDEV_OP_TURBO_DEC] = >>> +d->acc100_conf.q_ul_4g.num_aqs_per_groups * >>> d->acc100_conf.q_ul_4g.num_qgroups; >>> + dev_info->num_queues[RTE_BBDEV_OP_TURBO_ENC] = d- >>> acc100_conf.q_dl_4g.num_aqs_per_groups * >>> + d->acc100_conf.q_dl_4g.num_qgroups; >>> + dev_info->num_queues[RTE_BBDEV_OP_LDPC_DEC] = d- >>> acc100_conf.q_ul_5g.num_aqs_per_groups * >>> + d->acc100_conf.q_ul_5g.num_qgroups; >>> + dev_info->num_queues[RTE_BBDEV_OP_LDPC_ENC] = d- >>> acc100_conf.q_dl_5g.num_aqs_per_groups * >>> + d->acc100_conf.q_dl_5g.num_qgroups; >>> + dev_info->queue_priority[RTE_BBDEV_OP_TURBO_DEC] = d- >>> acc100_conf.q_ul_4g.num_qgroups; >>> + dev_info->queue_priority[RTE_BBDEV_OP_TURBO_ENC] = d- >>> acc100_conf.q_dl_4g.num_qgroups; >>> + dev_info->queue_priority[RTE_BBDEV_OP_LDPC_DEC] = d- >>> acc100_conf.q_ul_5g.num_qgroups; >>> + dev_info->queue_priority[RTE_BBDEV_OP_LDPC_ENC] = d- >>> acc100_conf.q_dl_5g.num_qgroups; >>> + dev_info->max_num_queues = 0; >>> + for (i = RTE_BBDEV_OP_TURBO_DEC; i < RTE_BBDEV_OP_LDPC_ENC; >> i++) >> >> should this be i <=  ? >> > Thanks > >>> + dev_info->max_num_queues += dev_info->num_queues[i]; >>> dev_info->queue_size_lim = ACC100_MAX_QUEUE_DEPTH; >>> dev_info->hardware_accelerated = true; >>> dev_info->max_dl_queue_priority = >>> diff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c >>> b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c >>> index 57b12af..b4982af 100644 >>> --- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c >>> +++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c >>> @@ -379,6 +379,14 @@ >>> if (hw_q_id != FPGA_INVALID_HW_QUEUE_ID) >>> dev_info->max_num_queues++; >>> } >>> + /* Expose number of queue per operation type */ >>> + dev_info->num_queues[RTE_BBDEV_OP_NONE] = 0; >>> + dev_info->num_queues[RTE_BBDEV_OP_TURBO_DEC] = 0; >>> + dev_info->num_queues[RTE_BBDEV_OP_TURBO_ENC] = 0; >>> + dev_info->num_queues[RTE_BBDEV_OP_LDPC_DEC] = dev_info- >>> max_num_queues / 2; >>> + dev_info->num_queues[RTE_BBDEV_OP_LDPC_ENC] = dev_info- >>> max_num_queues / 2; >>> + dev_info->queue_priority[RTE_BBDEV_OP_LDPC_DEC] = 1; >>> + dev_info->queue_priority[RTE_BBDEV_OP_LDPC_ENC] = 1; >>> } >>> >>> /** >>> diff --git a/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c >>> b/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c >>> index 2a330c4..dc7f479 100644 >>> --- a/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c >>> +++ b/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c >>> @@ -655,6 +655,14 @@ struct __rte_cache_aligned fpga_queue { >>> if (hw_q_id != FPGA_INVALID_HW_QUEUE_ID) >>> dev_info->max_num_queues++; >>> } >>> + /* Expose number of queue per operation type */ >>> + dev_info->num_queues[RTE_BBDEV_OP_NONE] = 0; >>> + dev_info->num_queues[RTE_BBDEV_OP_TURBO_DEC] = dev_info- >>> max_num_queues / 2; >>> + dev_info->num_queues[RTE_BBDEV_OP_TURBO_ENC] = dev_info- >>> max_num_queues / 2; >>> + dev_info->num_queues[RTE_BBDEV_OP_LDPC_DEC] = 0; >>> + dev_info->num_queues[RTE_BBDEV_OP_LDPC_ENC] = 0; >>> + dev_info->queue_priority[RTE_BBDEV_OP_TURBO_DEC] = 1; >>> + dev_info->queue_priority[RTE_BBDEV_OP_TURBO_ENC] = 1; >>> } >>> >>> /** >>> diff --git a/drivers/baseband/la12xx/bbdev_la12xx.c >>> b/drivers/baseband/la12xx/bbdev_la12xx.c >>> index c1f88c6..e99ea9a 100644 >>> --- a/drivers/baseband/la12xx/bbdev_la12xx.c >>> +++ b/drivers/baseband/la12xx/bbdev_la12xx.c >>> @@ -102,6 +102,13 @@ struct bbdev_la12xx_params { >>> dev_info->min_alignment = 64; >>> dev_info->device_status = RTE_BBDEV_DEV_NOT_SUPPORTED; >>> >>> + dev_info->num_queues[RTE_BBDEV_OP_NONE] = 0; >>> + dev_info->num_queues[RTE_BBDEV_OP_TURBO_DEC] = 0; >>> + dev_info->num_queues[RTE_BBDEV_OP_TURBO_ENC] = 0; >>> + dev_info->num_queues[RTE_BBDEV_OP_LDPC_DEC] = >> LA12XX_MAX_QUEUES / 2; >>> + dev_info->num_queues[RTE_BBDEV_OP_LDPC_ENC] = >> LA12XX_MAX_QUEUES / 2; >>> + dev_info->queue_priority[RTE_BBDEV_OP_LDPC_DEC] = 1; >>> + dev_info->queue_priority[RTE_BBDEV_OP_LDPC_ENC] = 1; >>> rte_bbdev_log_debug("got device info from %u", dev->data->dev_id); >>> } >>> >>> diff --git a/drivers/baseband/turbo_sw/bbdev_turbo_software.c >>> b/drivers/baseband/turbo_sw/bbdev_turbo_software.c >>> index dbc5524..647e706 100644 >>> --- a/drivers/baseband/turbo_sw/bbdev_turbo_software.c >>> +++ b/drivers/baseband/turbo_sw/bbdev_turbo_software.c >>> @@ -256,6 +256,17 @@ struct turbo_sw_queue { >>> dev_info->data_endianness = RTE_LITTLE_ENDIAN; >>> dev_info->device_status = RTE_BBDEV_DEV_NOT_SUPPORTED; >>> >>> + const struct rte_bbdev_op_cap *op_cap = bbdev_capabilities; >> Should this be done through dev instead of assigning directly ? > I am not sure I follow your suggestion. Do you mind clarifying? bbdev_capabilites is a const defined in this function, do you really need to loop over it to find information that is constant ? Tom > >> Tom >> >>> + int num_op_type = 0; >>> + for (; op_cap->type != RTE_BBDEV_OP_NONE; ++op_cap) >>> + num_op_type++; >>> + op_cap = bbdev_capabilities; >>> + if (num_op_type > 0) { >>> + int num_queue_per_type = dev_info->max_num_queues / >> num_op_type; >>> + for (; op_cap->type != RTE_BBDEV_OP_NONE; ++op_cap) >>> + dev_info->num_queues[op_cap->type] = >> num_queue_per_type; >>> + } >>> + >>> rte_bbdev_log_debug("got device info from %u\n", dev->data- >>> dev_id); >>> } >>>