From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9784D4404F; Wed, 12 Jun 2024 17:13:38 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4B3BA42E57; Wed, 12 Jun 2024 17:05:10 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mails.dpdk.org (Postfix) with ESMTP id 0BFEE427A0 for ; Wed, 12 Jun 2024 17:05:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718204706; x=1749740706; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/eas7Ka6wvEqsjED7URygx21cOoHxplGecN3HlDecrI=; b=EeOj2Ewcmc2OfibyixrRcZN/gm4+I6U8hGu6zRTkfiSHV3ooFrNNzeVE oEoPidQAicRMYDOrRlCXnBYpbQUwRgGtLnz8U1W7gWwQW6CWIbHhYsSlA Q1WTfDrx9iw82ER26IzSxngN4aZFFFl/pOtWQMkIj5h04GYoSnXCSi2CL 3IXLLWPjjGiyVJn/EJXAGK2MW6mX2F9ge6MTG45BPa80V9opaczpnO77y KXPufhHtGNvb6+swicC2lJwgDixE/vPjHDd6mVVhEYQUG/0fqUSZX/qqN i7NQW4vcaUYHTTfTWQ3XqWaLAMS9sIv9qAf54b3ZpZg6xjzwClm9QaaqG g==; X-CSE-ConnectionGUID: Etw/SMJcRFi1RjfA2x9o2Q== X-CSE-MsgGUID: w9sW4vD+TbWoVOHAtuMIYw== X-IronPort-AV: E=McAfee;i="6700,10204,11101"; a="32459546" X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="32459546" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2024 08:04:51 -0700 X-CSE-ConnectionGUID: J2A/10p4TbyI0aKZMfZiIw== X-CSE-MsgGUID: P68S2S00QBued4fA0AyBjA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="39925389" Received: from silpixa00401119.ir.intel.com ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 12 Jun 2024 08:04:49 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Ian Stokes , bruce.richardson@intel.com, Przemek Kitszel Subject: [PATCH v2 057/148] net/ice/base: get rid of enum ice_status Date: Wed, 12 Jun 2024 16:00:51 +0100 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: <20240430154014.1026-1-ian.stokes@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Ian Stokes Replace enum ice_status with int. Also replcae ICE_SUCCESS instances with 0. Signed-off-by: Przemek Kitszel Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_common.c | 12 ++-- drivers/net/ice/base/ice_ptp_hw.c | 93 +++++++++++++++---------------- drivers/net/ice/base/ice_ptp_hw.h | 20 +++---- drivers/net/ice/base/ice_switch.c | 20 +++---- 4 files changed, 71 insertions(+), 74 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index d4b9d793ba..75d02d39f5 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -703,7 +703,7 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd); - if (status != 0) + if (status) return status; /* save off old link status information */ @@ -3973,7 +3973,7 @@ int ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, struct ice_sq_cd *cd) { - enum ice_status status = ICE_ERR_AQ_ERROR; + int status = ICE_ERR_AQ_ERROR; struct ice_aqc_restart_an *cmd; struct ice_aq_desc desc; @@ -3997,7 +3997,7 @@ ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, else pi->phy.curr_user_phy_cfg.caps &= ~ICE_AQC_PHY_EN_LINK; - return ICE_SUCCESS; + return 0; } /** @@ -5228,7 +5228,7 @@ ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, /* add the LAN queue */ status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); - if (status != 0) { + if (status) { ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", LE16_TO_CPU(buf->txqs[0].txq_id), hw->adminq.sq_last_status); @@ -5323,7 +5323,7 @@ ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, vmvf_num, cd); - if (status != 0) + if (status) break; ice_free_sched_node(pi, node); q_ctx->q_handle = ICE_INVAL_Q_HANDLE; @@ -5664,7 +5664,7 @@ ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, buf->node_teid = CPU_TO_LE32(node_teid); status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, NULL); - if (status != 0 || num_elem_ret != 1) + if (status || num_elem_ret != 1) ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); return status; } diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index ad3a7599d7..7424b8d6f4 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -354,7 +354,7 @@ ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq, * Configure the Clock Generation Unit with the desired clock frequency and * time reference, enabling the PLL which drives the PTP hardware clock. */ -enum ice_status +int ice_cfg_cgu_pll_e825c(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq, enum ice_clk_src *clk_src) { @@ -364,7 +364,7 @@ ice_cfg_cgu_pll_e825c(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq, union nac_cgu_dword22 dw22; union nac_cgu_dword24 dw24; union nac_cgu_dword9 dw9; - enum ice_status status; + int status; if (*clk_freq >= NUM_ICE_TIME_REF_FREQ) { ice_warn(hw, "Invalid TIME_REF frequency %u\n", *clk_freq); @@ -492,7 +492,7 @@ ice_cfg_cgu_pll_e825c(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq, *clk_freq = (enum ice_time_ref_freq)dw9.field.time_ref_freq_sel; *clk_src = (enum ice_clk_src)dw23.field.time_ref_sel; - return ICE_SUCCESS; + return 0; } /** @@ -502,7 +502,7 @@ ice_cfg_cgu_pll_e825c(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq, * Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on * losing TS PLL lock, but always show current state. */ -static enum ice_status ice_cfg_cgu_pll_dis_sticky_bits_e822(struct ice_hw *hw) +static int ice_cfg_cgu_pll_dis_sticky_bits_e822(struct ice_hw *hw) { union tspll_cntr_bist_settings cntr_bist; int status; @@ -527,10 +527,10 @@ static enum ice_status ice_cfg_cgu_pll_dis_sticky_bits_e822(struct ice_hw *hw) * Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on * losing TS PLL lock, but always show current state. */ -static enum ice_status ice_cfg_cgu_pll_dis_sticky_bits_e825c(struct ice_hw *hw) +static int ice_cfg_cgu_pll_dis_sticky_bits_e825c(struct ice_hw *hw) { union tspll_bw_tdc_e825c bw_tdc; - enum ice_status status; + int status; status = ice_read_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C, &bw_tdc.val); @@ -549,11 +549,11 @@ static enum ice_status ice_cfg_cgu_pll_dis_sticky_bits_e825c(struct ice_hw *hw) * @hw: pointer to the HW struct * @lost_lock: output flag for reporting lost lock */ -enum ice_status +int ice_cgu_ts_pll_lost_lock_e825c(struct ice_hw *hw, bool *lost_lock) { union tspll_ro_lock_e825c ro_lock; - enum ice_status status; + int status; status = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val); if (status) @@ -565,17 +565,17 @@ ice_cgu_ts_pll_lost_lock_e825c(struct ice_hw *hw, bool *lost_lock) else *lost_lock = false; - return ICE_SUCCESS; + return 0; } /** * ice_cgu_ts_pll_restart_e825c - trigger TS PLL restart * @hw: pointer to the HW struct */ -enum ice_status ice_cgu_ts_pll_restart_e825c(struct ice_hw *hw) +int ice_cgu_ts_pll_restart_e825c(struct ice_hw *hw) { union nac_cgu_dword23_e825c dw23; - enum ice_status status; + int status; /* Read the initial values of DW23 */ status = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val); @@ -599,7 +599,7 @@ enum ice_status ice_cgu_ts_pll_restart_e825c(struct ice_hw *hw) if (status) return status; - return ICE_SUCCESS; + return 0; } #define E825C_CGU_BYPASS_MUX_OFFSET 3 @@ -620,11 +620,11 @@ static u32 cgu_bypass_mux_port(struct ice_hw *hw, u8 port) * @port: number of the port * @active: output flag showing if port is active */ -enum ice_status +int ice_cgu_bypass_mux_port_active_e825c(struct ice_hw *hw, u8 port, bool *active) { union nac_cgu_dword11_e825c dw11; - enum ice_status status; + int status; status = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD11_E825C, &dw11.val); if (status) @@ -635,7 +635,7 @@ ice_cgu_bypass_mux_port_active_e825c(struct ice_hw *hw, u8 port, bool *active) else *active = false; - return ICE_SUCCESS; + return 0; } /** @@ -645,13 +645,13 @@ ice_cgu_bypass_mux_port_active_e825c(struct ice_hw *hw, u8 port, bool *active) * @clock_1588: true to enable 1588 reference, false to recover from port * @ena: true to enable the reference, false if disable */ -enum ice_status +int ice_cfg_cgu_bypass_mux_e825c(struct ice_hw *hw, u8 port, bool clock_1588, unsigned int ena) { union nac_cgu_dword11_e825c dw11; union nac_cgu_dword10_e825c dw10; - enum ice_status status; + int status; status = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD11_E825C, &dw11.val); if (status) @@ -682,7 +682,7 @@ ice_cfg_cgu_bypass_mux_e825c(struct ice_hw *hw, u8 port, bool clock_1588, * @link_speed: link speed of the port * @divider: output value, calculated divider */ -static enum ice_status ice_get_div_e825c(u16 link_speed, u8 *divider) +static int ice_get_div_e825c(u16 link_speed, u8 *divider) { switch (link_speed) { case ICE_AQ_LINK_SPEED_100GB: @@ -705,7 +705,7 @@ static enum ice_status ice_get_div_e825c(u16 link_speed, u8 *divider) default: return ICE_ERR_NOT_SUPPORTED; } - return ICE_SUCCESS; + return 0; } /** @@ -713,10 +713,10 @@ static enum ice_status ice_get_div_e825c(u16 link_speed, u8 *divider) * @hw: pointer to the HW struct * @divider: output parameter, returns used divider value */ -enum ice_status ice_cfg_synce_ethdiv_e825c(struct ice_hw *hw, u8 *divider) +int ice_cfg_synce_ethdiv_e825c(struct ice_hw *hw, u8 *divider) { union nac_cgu_dword10_e825c dw10; - enum ice_status status; + int status; u16 link_speed; link_speed = hw->port_info->phy.link_info.link_speed; @@ -742,12 +742,12 @@ enum ice_status ice_cfg_synce_ethdiv_e825c(struct ice_hw *hw, u8 *divider) * * Initialize the Clock Generation Unit of the E822/E823/E825 device. */ -static enum ice_status ice_init_cgu_e82x(struct ice_hw *hw) +static int ice_init_cgu_e82x(struct ice_hw *hw) { struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info; enum ice_time_ref_freq time_ref_freq; enum ice_clk_src clk_src; - enum ice_status status; + int status; /* Disable sticky lock detection so lock status reported is accurate */ if (ice_is_e825c(hw)) @@ -4904,9 +4904,8 @@ ice_ptp_prep_phy_adj_target_e810(struct ice_hw *hw, u32 target_time) * Prepare the external PHYs connected to this device for a timer sync * command. */ -enum ice_status -ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, - bool lock_sbq) +int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, + bool lock_sbq) { u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); @@ -5149,7 +5148,7 @@ bool ice_is_pca9575_present(struct ice_hw *hw) * GLTSYN_INCVAL_L and GLTSYN_INCVAL_H registers. The actual change is * completed by FW automatically. */ -static enum ice_status +static int ice_ptp_write_direct_incval_e830(struct ice_hw *hw, u64 incval) { u32 high, low; @@ -5162,7 +5161,7 @@ ice_ptp_write_direct_incval_e830(struct ice_hw *hw, u64 incval) wr32(hw, GLTSYN_INCVAL_L(tmr_idx), low); wr32(hw, GLTSYN_INCVAL_H(tmr_idx), high); - return ICE_SUCCESS; + return 0; } /** @@ -5177,7 +5176,7 @@ ice_ptp_write_direct_incval_e830(struct ice_hw *hw, u64 incval) * The time value is the upper 32 bits of the PHY timer, usually in units of * nominal nanoseconds. */ -static enum ice_status +static int ice_ptp_write_direct_phc_time_e830(struct ice_hw *hw, u64 time) { u8 tmr_idx; @@ -5188,7 +5187,7 @@ ice_ptp_write_direct_phc_time_e830(struct ice_hw *hw, u64 time) wr32(hw, GLTSYN_TIME_L(tmr_idx), ICE_LO_DWORD(time)); wr32(hw, GLTSYN_TIME_H(tmr_idx), ICE_HI_DWORD(time)); - return ICE_SUCCESS; + return 0; } /** @@ -5200,7 +5199,7 @@ ice_ptp_write_direct_phc_time_e830(struct ice_hw *hw, u64 time) * Prepare the external PHYs connected to this device for a timer sync * command. */ -enum ice_status +int ice_ptp_port_cmd_e830(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, bool lock_sbq) { @@ -5220,7 +5219,7 @@ ice_ptp_port_cmd_e830(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, * Read a 40bit timestamp value out of the timestamp block of the external PHY * on the E830 device. */ -static enum ice_status +static int ice_read_phy_tstamp_e830(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) { u32 hi_addr = E830_HIGH_TX_MEMORY_BANK(idx, lport); @@ -5239,7 +5238,7 @@ ice_read_phy_tstamp_e830(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) */ *tstamp = ((u64)hi) << TS_HIGH_S | ((u64)lo & TS_LOW_M); - return ICE_SUCCESS; + return 0; } /** @@ -5249,7 +5248,7 @@ ice_read_phy_tstamp_e830(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) * @tstamp_ready: contents of the Tx memory status register * */ -enum ice_status +int ice_get_phy_tx_tstamp_ready_e830(struct ice_hw *hw, u8 port, u64 *tstamp_ready) { u64 hi; @@ -5260,7 +5259,7 @@ ice_get_phy_tx_tstamp_ready_e830(struct ice_hw *hw, u8 port, u64 *tstamp_ready) *tstamp_ready = hi | lo; - return ICE_SUCCESS; + return 0; } /* Device agnostic functions @@ -5330,9 +5329,8 @@ void ice_ptp_unlock(struct ice_hw *hw) * programming only a single port, instead use ice_ptp_one_port_cmd() to * ensure non-modified ports get properly initialized to ICE_PTP_NOP. */ -enum ice_status -ice_ptp_write_port_cmd(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd, - bool lock_sbq) +int ice_ptp_write_port_cmd(struct ice_hw *hw, u8 port, + enum ice_ptp_tmr_cmd cmd, bool lock_sbq) { switch (hw->phy_cfg) { case ICE_PHY_E822: @@ -5353,15 +5351,14 @@ ice_ptp_write_port_cmd(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd, * ports to ICE_PTP_NOP. This allows executing a command on a single port * while ensuring all other ports do not execute stale commands. */ -enum ice_status -ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port, - enum ice_ptp_tmr_cmd configured_cmd, bool lock_sbq) +int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port, + enum ice_ptp_tmr_cmd configured_cmd, bool lock_sbq) { u8 port; for (port = 0; port < hw->max_phy_port; port++) { enum ice_ptp_tmr_cmd cmd; - enum ice_status status; + int status; /* Program the configured port with the configured command, * program all other ports with ICE_PTP_NOP. @@ -5373,7 +5370,7 @@ ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port, return status; } - return ICE_SUCCESS; + return 0; } /** @@ -5386,8 +5383,8 @@ ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port, * some families this can be done in one shot, but for other families each * port must be configured individually. */ -static enum ice_status -ice_ptp_port_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, bool lock_sbq) +static int ice_ptp_port_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, + bool lock_sbq) { u8 port; @@ -5403,14 +5400,14 @@ ice_ptp_port_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, bool lock_sbq) /* PHY models which require programming each port separately */ for (port = 0; port < hw->max_phy_port; port++) { - enum ice_status status; + int status; status = ice_ptp_write_port_cmd(hw, port, cmd, lock_sbq); if (status) return status; } - return ICE_SUCCESS; + return 0; } /** @@ -5605,7 +5602,7 @@ int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq) break; case ICE_PHY_E830: /* E830 sync PHYs automatically after setting GLTSYN_SHADJ */ - return ICE_SUCCESS; + return 0; case ICE_PHY_E810: status = ice_ptp_prep_phy_adj_e810(hw, adj, lock_sbq); break; diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index 1fda3cd74c..be62e594bc 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -170,30 +170,30 @@ ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq, int ice_ptp_write_port_cmd_e822(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd, bool lock_sbq); -enum ice_status +int ice_ptp_write_port_cmd(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd, bool lock_sbq); -enum ice_status +int ice_cfg_cgu_pll_e825c(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq, enum ice_clk_src *clk_src); -enum ice_status +int ice_cgu_ts_pll_lost_lock_e825c(struct ice_hw *hw, bool *lost_lock); -enum ice_status ice_cgu_ts_pll_restart_e825c(struct ice_hw *hw); -enum ice_status +int ice_cgu_ts_pll_restart_e825c(struct ice_hw *hw); +int ice_cgu_bypass_mux_port_active_e825c(struct ice_hw *hw, u8 port, bool *active); -enum ice_status +int ice_cfg_cgu_bypass_mux_e825c(struct ice_hw *hw, u8 port_num, bool clock_1588, unsigned int ena); -enum ice_status ice_cfg_synce_ethdiv_e825c(struct ice_hw *hw, u8 *divider); +int ice_cfg_synce_ethdiv_e825c(struct ice_hw *hw, u8 *divider); /* E8 Family */ -enum ice_status +int ice_ptp_port_cmd_e830(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, bool lock_sbq); -enum ice_status +int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, bool lock_sbq); -enum ice_status +int ice_get_phy_tx_tstamp_ready_e830(struct ice_hw *hw, u8 port, u64 *tstamp_ready); int ice_ptp_port_cmd_eth56g(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index e49b86e009..6d0dcf43c6 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -3823,11 +3823,11 @@ ice_alloc_legacy_shared_recipe(struct ice_hw *hw, u16 *rid) * @hw: pointer to the hardware structure * @rid: recipe ID returned as response to AQ call */ -static enum ice_status +static int ice_alloc_subscribable_recipe(struct ice_hw *hw, u16 *rid) { struct ice_aqc_alloc_free_res_elem *buf; - enum ice_status status; + int status; u16 buf_len; buf_len = ice_struct_size(buf, elem, 1); @@ -3860,7 +3860,7 @@ ice_alloc_subscribable_recipe(struct ice_hw *hw, u16 *rid) * @hw: pointer to the hardware structure * @rid: recipe ID returned as response to AQ call */ -enum ice_status ice_alloc_recipe(struct ice_hw *hw, u16 *rid) +int ice_alloc_recipe(struct ice_hw *hw, u16 *rid) { if (hw->subscribable_recipes_supported) return ice_alloc_subscribable_recipe(hw, rid); @@ -3873,7 +3873,7 @@ enum ice_status ice_alloc_recipe(struct ice_hw *hw, u16 *rid) * @hw: pointer to the hardware structure * @rid: recipe ID to free */ -static enum ice_status ice_free_recipe_res(struct ice_hw *hw, u16 rid) +static int ice_free_recipe_res(struct ice_hw *hw, u16 rid) { return ice_free_hw_res(hw, ICE_AQC_RES_TYPE_RECIPE, 1, &rid); } @@ -3883,10 +3883,10 @@ static enum ice_status ice_free_recipe_res(struct ice_hw *hw, u16 rid) * @hw: pointer to the hardware structure * @rid: recipe ID to subscribe to */ -static enum ice_status ice_subscribe_recipe(struct ice_hw *hw, u16 rid) +static int ice_subscribe_recipe(struct ice_hw *hw, u16 rid) { struct ice_aqc_alloc_free_res_elem *buf; - enum ice_status status; + int status; u16 buf_len; buf_len = ice_struct_size(buf, elem, 1); @@ -3939,12 +3939,12 @@ static void ice_subscribable_recp_shared(struct ice_hw *hw, u16 rid) * @hw: pointer to the hardware structure * @recp: the recipe struct resource to unassociate and free */ -static enum ice_status ice_release_recipe_res(struct ice_hw *hw, - struct ice_sw_recipe *recp) +static int ice_release_recipe_res(struct ice_hw *hw, + struct ice_sw_recipe *recp) { ice_declare_bitmap(r_bitmap, ICE_MAX_NUM_RECIPES); struct ice_switch_info *sw = hw->switch_info; - enum ice_status status = ICE_SUCCESS; + int status = 0; u16 num_recp, num_prof; u8 rid, prof, i, j; @@ -10418,7 +10418,7 @@ ice_replay_vsi_all_fltr(struct ice_hw *hw, struct ice_port_info *pi, head); else status = ice_replay_vsi_adv_rule(hw, vsi_handle, head); - if (status != 0) + if (status) return status; } -- 2.43.0