From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 96ECA454EF; Tue, 25 Jun 2024 13:19:46 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DA1A242EDF; Tue, 25 Jun 2024 13:16:37 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by mails.dpdk.org (Postfix) with ESMTP id E09C742D45; Tue, 25 Jun 2024 13:15:57 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719314158; x=1750850158; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yD2zfhrtArch0AtuxwUaV1cf03PU6WgEaGZVgQbXA7s=; b=cZqiNbu9VoDpqziKwWEuFUVCe5tMuZZ1OqVpa1v5w6ZmN87E48l+bGfn CfhPckQNVac6k+NPiTON+pXHMlDyr95LLG36xSivmn0QEWROU7A6EB+QO 2e/lhsPP4ZXbRMZmHE7ix46ZSuB0ymD0ayi/qspgv049eSeQ997jOOMQC SGHGzD02xNnemg/l4WYIbEWDL4sylhSOoykE0Os6bm5V2pcItnBNCkfoR pfpB531xvC4pLzpsVqEwVehFat92OYPxDznqbY+045PKB4G/pUdYL96Tr VrmAOKWrS4nkKBePDes9CiFvnTjzC53Txa2w8ZlrST6HB+VoWQtcJVwUz g==; X-CSE-ConnectionGUID: 9UPJvgshROKmxvLFlF4FWA== X-CSE-MsgGUID: vEx5cyY9RIag5om6eHeCIA== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16080168" X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="16080168" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2024 04:15:57 -0700 X-CSE-ConnectionGUID: a9IvRqR1T/+HkVXw+KgpEA== X-CSE-MsgGUID: kjY+y0h+SSy6BKFARKs38A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="43719132" Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 25 Jun 2024 04:15:56 -0700 From: Anatoly Burakov To: dev@dpdk.org, Dan Nowlin , Paul M Stillwell Jr , Xiaolong Ye , Qi Zhang Cc: Jesse Brandeburg , bruce.richardson@intel.com, ian.stokes@intel.com, stable@dpdk.org Subject: [PATCH v3 035/129] net/ice/base: fix sign-extension Date: Tue, 25 Jun 2024 12:12:40 +0100 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Jesse Brandeburg Fix a static analysis warning where if the 16-bit value in mask has the high-bit set, it will be sign extended by the shift left (which converts it to a signed integer). Avoid this by casting to a u32 to make sure the conversion happens before the shift and that it stays unsigned. Fixes: 9467486f179f ("net/ice/base: enable masking for RSS and FD field vectors") Cc: qi.z.zhang@intel.com Cc: stable@dpdk.org Signed-off-by: Jesse Brandeburg Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_flex_pipe.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index e06dbb0885..413b6f8ece 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -1534,16 +1534,14 @@ ice_write_prof_mask_reg(struct ice_hw *hw, enum ice_block blk, u16 mask_idx, switch (blk) { case ICE_BLK_RSS: offset = GLQF_HMASK(mask_idx); - val = (idx << GLQF_HMASK_MSK_INDEX_S) & - GLQF_HMASK_MSK_INDEX_M; - val |= (mask << GLQF_HMASK_MASK_S) & GLQF_HMASK_MASK_M; + val = (idx << GLQF_HMASK_MSK_INDEX_S) & GLQF_HMASK_MSK_INDEX_M; + val |= ((u32)mask << GLQF_HMASK_MASK_S) & GLQF_HMASK_MASK_M; break; case ICE_BLK_FD: offset = GLQF_FDMASK(mask_idx); val = (idx << GLQF_FDMASK_MSK_INDEX_S) & GLQF_FDMASK_MSK_INDEX_M; - val |= (mask << GLQF_FDMASK_MASK_S) & - GLQF_FDMASK_MASK_M; + val |= ((u32)mask << GLQF_FDMASK_MASK_S) & GLQF_FDMASK_MASK_M; break; default: ice_debug(hw, ICE_DBG_PKG, "No profile masks for block %d\n", -- 2.43.0