From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 761F5A0C4E; Tue, 2 Nov 2021 10:31:35 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 44D8F4068F; Tue, 2 Nov 2021 10:31:35 +0100 (CET) Received: from szxga03-in.huawei.com (szxga03-in.huawei.com [45.249.212.189]) by mails.dpdk.org (Postfix) with ESMTP id 45DC240689 for ; Tue, 2 Nov 2021 10:31:32 +0100 (CET) Received: from dggemv703-chm.china.huawei.com (unknown [172.30.72.53]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4Hk4PQ50lbzSh2H; Tue, 2 Nov 2021 17:30:02 +0800 (CST) Received: from dggpeml500024.china.huawei.com (7.185.36.10) by dggemv703-chm.china.huawei.com (10.3.19.46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Tue, 2 Nov 2021 17:31:28 +0800 Received: from [127.0.0.1] (10.67.100.224) by dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.15; Tue, 2 Nov 2021 17:31:28 +0800 To: Gagandeep Singh , , CC: References: <20210909111500.3901706-1-g.singh@nxp.com> <20211101085143.2472241-1-g.singh@nxp.com> <20211101085143.2472241-6-g.singh@nxp.com> From: fengchengwen Message-ID: Date: Tue, 2 Nov 2021 17:31:28 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: <20211101085143.2472241-6-g.singh@nxp.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.67.100.224] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To dggpeml500024.china.huawei.com (7.185.36.10) X-CFilter-Loop: Reflected Subject: Re: [dpdk-dev] [PATCH v2 5/6] dma/dpaa: support DMA operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 2021/11/1 16:51, Gagandeep Singh wrote: > This patch support copy, submit, completed and > completed status functionality of DMA driver. > > Signed-off-by: Gagandeep Singh ... > + > +static int fsl_qdma_enqueue_desc(struct fsl_qdma_chan *fsl_chan, > + struct fsl_qdma_comp *fsl_comp, > + uint64_t flags) > +{ > + struct fsl_qdma_queue *fsl_queue = fsl_chan->queue; > + void *block = fsl_queue->block_base; > + struct fsl_qdma_format *ccdf; > + u32 reg; > + > + /* retrieve and store the register value in big endian > + * to avoid bits swap > + */ > + reg = qdma_readl_be(block + > + FSL_QDMA_BCQSR(fsl_queue->id)); > + if (reg & (FSL_QDMA_BCQSR_QF_XOFF_BE)) > + return -1; > + > + /* filling descriptor command table */ > + ccdf = (struct fsl_qdma_format *)fsl_queue->virt_head; > + qdma_desc_addr_set64(ccdf, fsl_comp->bus_addr + 16); > + qdma_ccdf_set_format(ccdf, qdma_ccdf_get_offset(fsl_comp->virt_addr)); > + qdma_ccdf_set_ser(ccdf, qdma_ccdf_get_status(fsl_comp->virt_addr)); > + fsl_comp->index = fsl_queue->virt_head - fsl_queue->cq; > + fsl_queue->virt_head++; > + > + if (fsl_queue->virt_head == fsl_queue->cq + fsl_queue->n_cq) > + fsl_queue->virt_head = fsl_queue->cq; > + > + list_add_tail(&fsl_comp->list, &fsl_queue->comp_used); > + > + if (flags == RTE_DMA_OP_FLAG_SUBMIT) { > + reg = qdma_readl_be(block + FSL_QDMA_BCQMR(fsl_queue->id)); > + reg |= FSL_QDMA_BCQMR_EI_BE; > + qdma_writel_be(reg, block + FSL_QDMA_BCQMR(fsl_queue->id)); > + } > + return fsl_comp->index; I can't catch the index real range? it should to be [0, 0xffff] from framework view. > +} > + > static int fsl_qdma_alloc_chan_resources(struct fsl_qdma_chan *fsl_chan) > { > struct fsl_qdma_queue *fsl_queue = fsl_chan->queue; > @@ -492,6 +690,148 @@ dpaa_qdma_queue_setup(struct rte_dma_dev *dmadev, > return dpaa_get_channel(fsl_qdma, vchan); > } > > +static int > +dpaa_qdma_submit(void *dev_private, uint16_t vchan) > +{ > + struct fsl_qdma_engine *fsl_qdma = (struct fsl_qdma_engine *)dev_private; > + struct fsl_qdma_chan *fsl_chan = > + &fsl_qdma->chans[fsl_qdma->vchan_map[vchan]]; > + struct fsl_qdma_queue *fsl_queue = fsl_chan->queue; > + void *block = fsl_queue->block_base; > + u32 reg; > + > + reg = qdma_readl_be(block + FSL_QDMA_BCQMR(fsl_queue->id)); > + reg |= FSL_QDMA_BCQMR_EI_BE; > + qdma_writel_be(reg, block + FSL_QDMA_BCQMR(fsl_queue->id)); > + > + return 0; > +} > + ... > >