From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4BB34A04B5; Tue, 12 Jan 2021 09:07:28 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BB738140D07; Tue, 12 Jan 2021 09:07:27 +0100 (CET) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [63.128.21.124]) by mails.dpdk.org (Postfix) with ESMTP id 0C026140D06 for ; Tue, 12 Jan 2021 09:07:26 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1610438846; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fTTIn6cSFzbdcJCHlnFaXZ0NXfjZDJJhAGX9Dm4k+kg=; b=Da+dTmvZQDDs9TH1dCShp1i/+zEI80PwTt3uT65RpzPFr+HC+ESXeFcd9WZfokdsmobRHI x4OuBObxZiGMjXb7/s58+0BqK3OpUm0scLeigs9cBSpu5eNut7bOuTnb5oEWh0y8sZPt7e OLcdj8PblO5Hsc3QghnPAXsJs2U5YG4= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-108-rGhy2bpAP0GlujKuyA0oTA-1; Tue, 12 Jan 2021 03:07:24 -0500 X-MC-Unique: rGhy2bpAP0GlujKuyA0oTA-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 49B76107ACF9; Tue, 12 Jan 2021 08:07:23 +0000 (UTC) Received: from [10.36.110.24] (unknown [10.36.110.24]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 9103550DD5; Tue, 12 Jan 2021 08:07:17 +0000 (UTC) To: =?UTF-8?B?6LCi5Y2O5LyfKOatpOaXtuatpOWIu++8iQ==?= , ferruh.yigit@intel.com Cc: dev@dpdk.org, anatoly.burakov@intel.com, david.marchand@redhat.com, zhihong.wang@intel.com, chenbo.xia@intel.com, grive@u256.net References: <68ecd941-9c56-4de7-fae2-2ad15bdfd81a@alibaba-inc.com> <1603381885-88819-1-git-send-email-huawei.xhw@alibaba-inc.com> <1603381885-88819-2-git-send-email-huawei.xhw@alibaba-inc.com> From: Maxime Coquelin Message-ID: Date: Tue, 12 Jan 2021 09:07:15 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <1603381885-88819-2-git-send-email-huawei.xhw@alibaba-inc.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=maxime.coquelin@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH v5 1/3] PCI: use PCI standard sysfs entry to get PIO address X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Huawei, The title should be under the form: "bus/pci: use PCI standard sysfs entry to get PIO address" On 10/22/20 5:51 PM, 谢华伟(此时此刻） wrote: > From: "huawei.xhw" > > Previously with igb_uio we get PIO address from igb_uio sysfs entry, with > uio_pci_generic, we get PIO address from /proc/ioports. > > Signed-off-by: huawei.xhw In order to comply with the contribution rules, your name must be disaplyed under the form: Signed-off-by: Firstname Lastname > --- > drivers/bus/pci/linux/pci.c | 77 ----------------------------------------- > drivers/bus/pci/linux/pci_uio.c | 64 ++++++++++++++++++++++++---------- > 2 files changed, 46 insertions(+), 95 deletions(-) > > diff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.c > index 2e1808b..0f38abf 100644 > --- a/drivers/bus/pci/linux/pci.c > +++ b/drivers/bus/pci/linux/pci.c > @@ -677,71 +677,6 @@ int rte_pci_write_config(const struct rte_pci_device *device, > } > } > > -#if defined(RTE_ARCH_X86) > -static int > -pci_ioport_map(struct rte_pci_device *dev, int bar __rte_unused, > - struct rte_pci_ioport *p) > -{ > - uint16_t start, end; > - FILE *fp; > - char *line = NULL; > - char pci_id[16]; > - int found = 0; > - size_t linesz; > - > - if (rte_eal_iopl_init() != 0) { > - RTE_LOG(ERR, EAL, "%s(): insufficient ioport permissions for PCI device %s\n", > - __func__, dev->name); > - return -1; > - } > - > - snprintf(pci_id, sizeof(pci_id), PCI_PRI_FMT, > - dev->addr.domain, dev->addr.bus, > - dev->addr.devid, dev->addr.function); > - > - fp = fopen("/proc/ioports", "r"); > - if (fp == NULL) { > - RTE_LOG(ERR, EAL, "%s(): can't open ioports\n", __func__); > - return -1; > - } > - > - while (getdelim(&line, &linesz, '\n', fp) > 0) { > - char *ptr = line; > - char *left; > - int n; > - > - n = strcspn(ptr, ":"); > - ptr[n] = 0; > - left = &ptr[n + 1]; > - > - while (*left && isspace(*left)) > - left++; > - > - if (!strncmp(left, pci_id, strlen(pci_id))) { > - found = 1; > - > - while (*ptr && isspace(*ptr)) > - ptr++; > - > - sscanf(ptr, "%04hx-%04hx", &start, &end); > - > - break; > - } > - } > - > - free(line); > - fclose(fp); > - > - if (!found) > - return -1; > - > - p->base = start; > - RTE_LOG(DEBUG, EAL, "PCI Port IO found start=0x%x\n", start); > - > - return 0; > -} > -#endif > - > int > rte_pci_ioport_map(struct rte_pci_device *dev, int bar, > struct rte_pci_ioport *p) > @@ -756,14 +691,8 @@ int rte_pci_write_config(const struct rte_pci_device *device, > break; > #endif > case RTE_PCI_KDRV_IGB_UIO: > - ret = pci_uio_ioport_map(dev, bar, p); > - break; > case RTE_PCI_KDRV_UIO_GENERIC: > -#if defined(RTE_ARCH_X86) > - ret = pci_ioport_map(dev, bar, p); > -#else > ret = pci_uio_ioport_map(dev, bar, p); > -#endif > break; > default: > break; > @@ -830,14 +759,8 @@ int rte_pci_write_config(const struct rte_pci_device *device, > break; > #endif > case RTE_PCI_KDRV_IGB_UIO: > - ret = pci_uio_ioport_unmap(p); > - break; > case RTE_PCI_KDRV_UIO_GENERIC: > -#if defined(RTE_ARCH_X86) > - ret = 0; > -#else > ret = pci_uio_ioport_unmap(p); > -#endif > break; > default: > break; > diff --git a/drivers/bus/pci/linux/pci_uio.c b/drivers/bus/pci/linux/pci_uio.c > index f3305a2..01f2a40 100644 > --- a/drivers/bus/pci/linux/pci_uio.c > +++ b/drivers/bus/pci/linux/pci_uio.c > @@ -373,10 +373,13 @@ > pci_uio_ioport_map(struct rte_pci_device *dev, int bar, > struct rte_pci_ioport *p) > { > + FILE *f = NULL; > char dirname[PATH_MAX]; > char filename[PATH_MAX]; > - int uio_num; > - unsigned long start; > + char buf[BUFSIZ]; > + uint64_t phys_addr, end_addr, flags; > + unsigned long base; > + int i; > > if (rte_eal_iopl_init() != 0) { > RTE_LOG(ERR, EAL, "%s(): insufficient ioport permissions for PCI device %s\n", > @@ -384,41 +387,66 @@ > return -1; > } > > - uio_num = pci_get_uio_dev(dev, dirname, sizeof(dirname), 0); > - if (uio_num < 0) > + /* open and read addresses of the corresponding resource in sysfs */ > + snprintf(filename, sizeof(filename), "%s/" PCI_PRI_FMT "/resource", > + rte_pci_get_sysfs_path(), dev->addr.domain, dev->addr.bus, > + dev->addr.devid, dev->addr.function); > + f = fopen(filename, "r"); > + if (f == NULL) { > + RTE_LOG(ERR, EAL, "%s(): Cannot open sysfs resource: %s\n", > + __func__, strerror(errno)); > return -1; > + } > > - /* get portio start */ > - snprintf(filename, sizeof(filename), > - "%s/portio/port%d/start", dirname, bar); > - if (eal_parse_sysfs_value(filename, &start) < 0) { > - RTE_LOG(ERR, EAL, "%s(): cannot parse portio start\n", > - __func__); > - return -1; > + for (i = 0; i < bar + 1; i++) { > + if (fgets(buf, sizeof(buf), f) == NULL) { > + RTE_LOG(ERR, EAL, "%s(): Cannot read sysfs resource\n", __func__); > + goto error; > + } > } > - /* ensure we don't get anything funny here, read/write will cast to > - * uin16_t */ > - if (start > UINT16_MAX) > - return -1; > + if (pci_parse_one_sysfs_resource(buf, sizeof(buf), &phys_addr, > + &end_addr, &flags) < 0) > + goto error; > + > + if (!(flags & IORESOURCE_IO)) { > + RTE_LOG(ERR, EAL, "%s(): bar resource other than IO is not supported\n", __func__); > + goto error; > + } > + base = (unsigned long)phys_addr; > + RTE_LOG(INFO, EAL, "%s(): PIO BAR %08lx detected\n", __func__, base); > + > + if (base > UINT16_MAX) > + goto error; > > /* FIXME only for primary process ? */ > if (dev->intr_handle.type == RTE_INTR_HANDLE_UNKNOWN) { > + int uio_num = pci_get_uio_dev(dev, dirname, sizeof(dirname), 0); > + if (uio_num < 0) { > + RTE_LOG(ERR, EAL, "cannot open %s: %s\n", > + dirname, strerror(errno)); > + goto error; > + } > > snprintf(filename, sizeof(filename), "/dev/uio%u", uio_num); > dev->intr_handle.fd = open(filename, O_RDWR); > if (dev->intr_handle.fd < 0) { > RTE_LOG(ERR, EAL, "Cannot open %s: %s\n", > filename, strerror(errno)); > - return -1; > + goto error; > } > dev->intr_handle.type = RTE_INTR_HANDLE_UIO; > } > > - RTE_LOG(DEBUG, EAL, "PCI Port IO found start=0x%lx\n", start); > + RTE_LOG(DEBUG, EAL, "PCI Port IO found start=0x%lx\n", base); > > - p->base = start; > + p->base = base; > p->len = 0; > + fclose(f); > return 0; > +error: > + if (f) > + fclose(f); > + return -1; > } > #else > int > I think it makes sense to have a common way for both igb_uio and uio_pci_generic to get the PIO base address. With commit message and title fixed, feel free to add my: Reviewed-by: Maxime Coquelin Thanks, Maxime