From mboxrd@z Thu Jan 1 00:00:00 1970
Return-Path: <dev-bounces@dpdk.org>
Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124])
by inbox.dpdk.org (Postfix) with ESMTP id 12D39A054F;
Thu, 8 Sep 2022 20:33:09 +0200 (CEST)
Received: from [217.70.189.124] (localhost [127.0.0.1])
by mails.dpdk.org (Postfix) with ESMTP id D5C2141141;
Thu, 8 Sep 2022 20:33:08 +0200 (CEST)
Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com
[148.163.158.5])
by mails.dpdk.org (Postfix) with ESMTP id 7B66B40DDC;
Thu, 8 Sep 2022 20:33:07 +0200 (CEST)
Received: from pps.filterd (m0098419.ppops.net [127.0.0.1])
by mx0b-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 288IKaqn023015;
Thu, 8 Sep 2022 18:33:06 GMT
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com;
h=message-id : date :
mime-version : subject : to : cc : references : from : in-reply-to :
content-type : content-transfer-encoding; s=pp1;
bh=sMfsrpAO2Xf5rIuAAP2djPWE9Kf6d98jtdFh1VeBrNY=;
b=dinlTmoZ1hn5QIyi212wQ+GS7Yzzau6M/2jTHx/3wmMwBeffSlpuc/yag0+MZPYO+NJ6
Ky9HKtZoeX7J7jLkThXEDsvlvbh4vcPeBeXEOsmMcdmlwCGQBekpU/pxjDPoWVzFM3N/
duYJuNweU4NhKX7G49zJcbs7pC78HxJXBE888Jwy6VFCvTBCTSh0W947qV/BqjSvNU+z
f0UY0jgE08687IaW6GQNOeNUZBjWv/ru+x2+xytoiRgwS/ipSS7xNC3GqT87sMmA/TFC
K8Vwz4niijkFBdDeHHzu+96JGLay2oe0G5/9lzerFQWRKUjpHvw7vWt+v7hehTDL0sy1 uQ==
Received: from ppma01wdc.us.ibm.com (fd.55.37a9.ip4.static.sl-reverse.com
[169.55.85.253])
by mx0b-001b2d01.pphosted.com (PPS) with ESMTPS id 3jfnkc0ahm-1
(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);
Thu, 08 Sep 2022 18:33:06 +0000
Received: from pps.filterd (ppma01wdc.us.ibm.com [127.0.0.1])
by ppma01wdc.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 288ILQXp008526;
Thu, 8 Sep 2022 18:33:06 GMT
Received: from b03cxnp08028.gho.boulder.ibm.com
(b03cxnp08028.gho.boulder.ibm.com [9.17.130.20])
by ppma01wdc.us.ibm.com with ESMTP id 3jbxj9t172-1
(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);
Thu, 08 Sep 2022 18:33:06 +0000
Received: from b03ledav004.gho.boulder.ibm.com
(b03ledav004.gho.boulder.ibm.com [9.17.130.235])
by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id
288IX5bP8127184
(version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK);
Thu, 8 Sep 2022 18:33:05 GMT
Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1])
by IMSVA (Postfix) with ESMTP id 101847805F;
Thu, 8 Sep 2022 18:44:10 +0000 (GMT)
Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1])
by IMSVA (Postfix) with ESMTP id CFF8D7805C;
Thu, 8 Sep 2022 18:44:09 +0000 (GMT)
Received: from [9.211.79.90] (unknown [9.211.79.90])
by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTP;
Thu, 8 Sep 2022 18:44:09 +0000 (GMT)
Message-ID: <d8dc9469-c222-847c-82c5-f0af659d9495@linux.vnet.ibm.com>
Date: Thu, 8 Sep 2022 11:33:04 -0700
MIME-Version: 1.0
User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0)
Gecko/20100101 Thunderbird/91.13.0
Subject: Re: [PATCH v2 1/5] examples/l3fwd: fix port group mask generation
Content-Language: en-US
To: pbhagavatula@marvell.com, jerinj@marvell.com
Cc: dev@dpdk.org, stable@dpdk.org
References: <20220829094442.3422-1-pbhagavatula@marvell.com>
<20220902091833.9074-1-pbhagavatula@marvell.com>
From: David Christensen <drc@linux.vnet.ibm.com>
In-Reply-To: <20220902091833.9074-1-pbhagavatula@marvell.com>
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 7bit
X-TM-AS-GCONF: 00
X-Proofpoint-GUID: n0sO9izY9j4GtZa5jqFnisL8P3SRBrML
X-Proofpoint-ORIG-GUID: n0sO9izY9j4GtZa5jqFnisL8P3SRBrML
X-Proofpoint-Virus-Version: vendor=baseguard
engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1
definitions=2022-09-08_10,2022-09-08_01,2022-06-22_01
X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0
mlxscore=0 spamscore=0
clxscore=1011 malwarescore=0 priorityscore=1501 phishscore=0
mlxlogscore=999 adultscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0
impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1
engine=8.12.0-2207270000 definitions=main-2209080065
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <https://mails.dpdk.org/options/dev>,
<mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://mails.dpdk.org/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <https://mails.dpdk.org/listinfo/dev>,
<mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org
On 9/2/22 2:18 AM, pbhagavatula@marvell.com wrote:
> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
>
> Fix port group mask generation in altivec, vec_any_eq returns
> 0 or 1 while port_groupx4 expects comparison mask result.
>
> Fixes: 2193b7467f7a ("examples/l3fwd: optimize packet processing on powerpc")
> Cc: stable@dpdk.org
>
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> ---
> v2 Changes:
> - Fix PPC, RISC-V, aarch32 compilation.
>
> examples/common/altivec/port_group.h | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/examples/common/altivec/port_group.h b/examples/common/altivec/port_group.h
> index 5e209b02fa..592ef80b7f 100644
> --- a/examples/common/altivec/port_group.h
> +++ b/examples/common/altivec/port_group.h
> @@ -26,12 +26,19 @@ port_groupx4(uint16_t pn[FWDSTEP + 1], uint16_t *lp,
> uint16_t u16[FWDSTEP + 1];
> uint64_t u64;
> } *pnum = (void *)pn;
> + union u_vec {
> + __vector unsigned short v_us;
> + unsigned short s[8];
> + };
>
> + union u_vec res;
> int32_t v;
>
> - v = vec_any_eq(dp1, dp2);
> -
> + dp1 = (__vector unsigned short)vec_cmpeq(dp1, dp2);
Altivec vec_cmpeq() is similar to Intel _mm_cmpeq_*(), so this looks
right to me.
> + res.v_us = dp1;
>
> + v = (res.s[0] & 0x1) | (res.s[1] & 0x2) | (res.s[2] & 0x4) |
> + (res.s[3] & 0x8);
This can be vectorized too. The Intel _mm_unpacklo_epi16() intrinsic
can be replaced with the following Altivec code:
extern __inline __m128i __attribute__((__gnu_inline__,
__always_inline__, __artificial__))
_mm_unpacklo_epi16 (__m128i __A, __m128i __B)
{
return (__m128i) vec_mergeh ((__v8hi)__A, (__v8hi)__B);
}
The Intel _mm_movemask_ps() intrinsic can be replaced with the following
Altivec implementation:
/* Creates a 4-bit mask from the most significant bits of the SPFP
values. */
extern __inline int __attribute__((__gnu_inline__, __always_inline__,
__artificial__))
_mm_movemask_ps (__m128 __A)
{
__vector unsigned long long result;
static const __vector unsigned int perm_mask =
{
#ifdef __LITTLE_ENDIAN__
0x00204060, 0x80808080, 0x80808080, 0x80808080
#else
0x80808080, 0x80808080, 0x80808080, 0x00204060
#endif
};
result = ((__vector unsigned long long)
vec_vbpermq ((__vector unsigned char) __A,
(__vector unsigned char) perm_mask));
#ifdef __LITTLE_ENDIAN__
return result[1];
#else
return result[0];
#endif
}
Dave