From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 259C7454EF; Tue, 25 Jun 2024 13:15:40 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2FA89427B5; Tue, 25 Jun 2024 13:15:26 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by mails.dpdk.org (Postfix) with ESMTP id F38C7402C4 for ; Tue, 25 Jun 2024 13:15:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719314106; x=1750850106; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Z6gKsuKpxCgliAFosMA8DbYwhHjp4SOY1XK1iWCiTYE=; b=ESHPbdO7ELMnNJ92FHhnomaHpmOw5Gj7d0WGqBuFCUlnt770sC8blf4q Zcpy0jb/y0TeyzbQUGqVrHKjyNCEwr8IJ6zTvGnRC6hQjcnmD4yBlH0/s b3eSPXllW/6T1mCVm+/f0O7aNAOKZ/O1hhq9q+3+TKNSfSeSFvEGN01ob E1j7O3SAv0Z2LfFbXIOopHW7ZG56fd76TUZSFocCBi4eMMQjQ3XiE7iRz r5MAN1ZCebLL1Fu0l7nskPxRl7VDGm3mJgAsBO2pUKjH2r7SUIEZkHJW2 6gCd97SUp/GPXjx+BOmMQ+M4WvuYUIYGhRKuycEZEC4uOJjmSlUjDFNQg A==; X-CSE-ConnectionGUID: NCiJrqrsSVaHXdYXspx9Jg== X-CSE-MsgGUID: qz5+ixGDQnuIE2FBNywLLQ== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16080061" X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="16080061" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2024 04:15:05 -0700 X-CSE-ConnectionGUID: tP+WLT8wTyO7ixuNVKDr5w== X-CSE-MsgGUID: P3aauPZFSMWClN8TNf2yMw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="43718843" Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 25 Jun 2024 04:15:05 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Paul Greenwalt , bruce.richardson@intel.com, ian.stokes@intel.com Subject: [PATCH v3 003/129] net/ice/base: add E830 definitions Date: Tue, 25 Jun 2024 12:12:08 +0100 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Paul Greenwalt Add initial set of E830-related definitions. Signed-off-by: Paul Greenwalt Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_hw_autogen.h | 79 +++++++++++++++++---------- 1 file changed, 50 insertions(+), 29 deletions(-) diff --git a/drivers/net/ice/base/ice_hw_autogen.h b/drivers/net/ice/base/ice_hw_autogen.h index 4610cec6a7..5215d71c70 100644 --- a/drivers/net/ice/base/ice_hw_autogen.h +++ b/drivers/net/ice/base/ice_hw_autogen.h @@ -429,9 +429,11 @@ #define PF0INT_OICR_CPM_PAGE_QUEUE_S 1 #define PF0INT_OICR_CPM_PAGE_QUEUE_M BIT(1) #define PF0INT_OICR_CPM_PAGE_RSV1_S 2 -#define PF0INT_OICR_CPM_PAGE_RSV1_M MAKEMASK(0xFF, 2) -#define PF0INT_OICR_CPM_PAGE_HH_COMP_S 10 -#define PF0INT_OICR_CPM_PAGE_HH_COMP_M BIT(10) +#define PF0INT_OICR_CPM_PAGE_RSV1_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PF0INT_OICR_CPM_PAGE_RSV1_M : E800_PF0INT_OICR_CPM_PAGE_RSV1_M) +#define E800_PF0INT_OICR_CPM_PAGE_RSV1_M MAKEMASK(0xFF, 2) +#define E830_PF0INT_OICR_CPM_PAGE_RSV1_M MAKEMASK(0x3F, 2) +#define E800_PF0INT_OICR_CPM_PAGE_HH_COMP_S 10 +#define E800_PF0INT_OICR_CPM_PAGE_HH_COMP_M BIT(10) #define PF0INT_OICR_CPM_PAGE_TSYN_TX_S 11 #define PF0INT_OICR_CPM_PAGE_TSYN_TX_M BIT(11) #define PF0INT_OICR_CPM_PAGE_TSYN_EVNT_S 12 @@ -493,9 +495,11 @@ #define PF0INT_OICR_HLP_PAGE_QUEUE_S 1 #define PF0INT_OICR_HLP_PAGE_QUEUE_M BIT(1) #define PF0INT_OICR_HLP_PAGE_RSV1_S 2 -#define PF0INT_OICR_HLP_PAGE_RSV1_M MAKEMASK(0xFF, 2) -#define PF0INT_OICR_HLP_PAGE_HH_COMP_S 10 -#define PF0INT_OICR_HLP_PAGE_HH_COMP_M BIT(10) +#define PF0INT_OICR_HLP_PAGE_RSV1_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PF0INT_OICR_HLP_PAGE_RSV1_M : E800_PF0INT_OICR_HLP_PAGE_RSV1_M) +#define E800_PF0INT_OICR_HLP_PAGE_RSV1_M MAKEMASK(0xFF, 2) +#define E830_PF0INT_OICR_HLP_PAGE_RSV1_M MAKEMASK(0x3F, 2) +#define E800_PF0INT_OICR_HLP_PAGE_HH_COMP_S 10 +#define E800_PF0INT_OICR_HLP_PAGE_HH_COMP_M BIT(10) #define PF0INT_OICR_HLP_PAGE_TSYN_TX_S 11 #define PF0INT_OICR_HLP_PAGE_TSYN_TX_M BIT(11) #define PF0INT_OICR_HLP_PAGE_TSYN_EVNT_S 12 @@ -542,9 +546,11 @@ #define PF0INT_OICR_PSM_PAGE_QUEUE_S 1 #define PF0INT_OICR_PSM_PAGE_QUEUE_M BIT(1) #define PF0INT_OICR_PSM_PAGE_RSV1_S 2 -#define PF0INT_OICR_PSM_PAGE_RSV1_M MAKEMASK(0xFF, 2) -#define PF0INT_OICR_PSM_PAGE_HH_COMP_S 10 -#define PF0INT_OICR_PSM_PAGE_HH_COMP_M BIT(10) +#define PF0INT_OICR_PSM_PAGE_RSV1_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PF0INT_OICR_PSM_PAGE_RSV1_M : E800_PF0INT_OICR_PSM_PAGE_RSV1_M) +#define E800_PF0INT_OICR_PSM_PAGE_RSV1_M MAKEMASK(0xFF, 2) +#define E830_PF0INT_OICR_PSM_PAGE_RSV1_M MAKEMASK(0x3F, 2) +#define E800_PF0INT_OICR_PSM_PAGE_HH_COMP_S 10 +#define E800_PF0INT_OICR_PSM_PAGE_HH_COMP_M BIT(10) #define PF0INT_OICR_PSM_PAGE_TSYN_TX_S 11 #define PF0INT_OICR_PSM_PAGE_TSYN_TX_M BIT(11) #define PF0INT_OICR_PSM_PAGE_TSYN_EVNT_S 12 @@ -4397,11 +4403,11 @@ #define GLTPB_100G_MAC_FC_THRESH_PORT0_FC_THRESH_M MAKEMASK(0xFFFF, 0) #define GLTPB_100G_MAC_FC_THRESH_PORT1_FC_THRESH_S 16 #define GLTPB_100G_MAC_FC_THRESH_PORT1_FC_THRESH_M MAKEMASK(0xFFFF, 16) -#define GLTPB_100G_RPB_FC_THRESH 0x0009963C /* Reset Source: CORER */ -#define GLTPB_100G_RPB_FC_THRESH_PORT0_FC_THRESH_S 0 -#define GLTPB_100G_RPB_FC_THRESH_PORT0_FC_THRESH_M MAKEMASK(0xFFFF, 0) -#define GLTPB_100G_RPB_FC_THRESH_PORT1_FC_THRESH_S 16 -#define GLTPB_100G_RPB_FC_THRESH_PORT1_FC_THRESH_M MAKEMASK(0xFFFF, 16) +#define E800_GLTPB_100G_RPB_FC_THRESH 0x0009963C /* Reset Source: CORER */ +#define E800_GLTPB_100G_RPB_FC_THRESH_PORT0_FC_THRESH_S 0 +#define E800_GLTPB_100G_RPB_FC_THRESH_PORT0_FC_THRESH_M MAKEMASK(0xFFFF, 0) +#define E800_GLTPB_100G_RPB_FC_THRESH_PORT1_FC_THRESH_S 16 +#define E800_GLTPB_100G_RPB_FC_THRESH_PORT1_FC_THRESH_M MAKEMASK(0xFFFF, 16) #define GLTPB_PACING_10G 0x000994E4 /* Reset Source: CORER */ #define GLTPB_PACING_10G_N_S 0 #define GLTPB_PACING_10G_N_M MAKEMASK(0xFF, 0) @@ -4545,7 +4551,9 @@ #define GLINT_TSYN_PFMSTR_PF_MASTER_M MAKEMASK(0x7, 0) #define GLINT_TSYN_PHY 0x0016CC50 /* Reset Source: CORER */ #define GLINT_TSYN_PHY_PHY_INDX_S 0 -#define GLINT_TSYN_PHY_PHY_INDX_M MAKEMASK(0x1F, 0) +#define GLINT_TSYN_PHY_PHY_INDX_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GLINT_TSYN_PHY_PHY_INDX_M : E800_GLINT_TSYN_PHY_PHY_INDX_M) +#define E800_GLINT_TSYN_PHY_PHY_INDX_M MAKEMASK(0x1F, 0) +#define E830_GLINT_TSYN_PHY_PHY_INDX_M MAKEMASK(0xFF, 0) #define GLINT_VECT2FUNC(_INT) (0x00162000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */ #define GLINT_VECT2FUNC_MAX_INDEX 2047 #define GLINT_VECT2FUNC_VF_NUM_S 0 @@ -4605,9 +4613,11 @@ #define PF0INT_OICR_CPM_QUEUE_S 1 #define PF0INT_OICR_CPM_QUEUE_M BIT(1) #define PF0INT_OICR_CPM_RSV1_S 2 -#define PF0INT_OICR_CPM_RSV1_M MAKEMASK(0xFF, 2) -#define PF0INT_OICR_CPM_HH_COMP_S 10 -#define PF0INT_OICR_CPM_HH_COMP_M BIT(10) +#define PF0INT_OICR_CPM_RSV1_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PF0INT_OICR_CPM_RSV1_M : E800_PF0INT_OICR_CPM_RSV1_M) +#define E800_PF0INT_OICR_CPM_RSV1_M MAKEMASK(0xFF, 2) +#define E830_PF0INT_OICR_CPM_RSV1_M MAKEMASK(0x3F, 2) +#define E800_PF0INT_OICR_CPM_HH_COMP_S 10 +#define E800_PF0INT_OICR_CPM_HH_COMP_M BIT(10) #define PF0INT_OICR_CPM_TSYN_TX_S 11 #define PF0INT_OICR_CPM_TSYN_TX_M BIT(11) #define PF0INT_OICR_CPM_TSYN_EVNT_S 12 @@ -4696,9 +4706,11 @@ #define PF0INT_OICR_HLP_QUEUE_S 1 #define PF0INT_OICR_HLP_QUEUE_M BIT(1) #define PF0INT_OICR_HLP_RSV1_S 2 -#define PF0INT_OICR_HLP_RSV1_M MAKEMASK(0xFF, 2) -#define PF0INT_OICR_HLP_HH_COMP_S 10 -#define PF0INT_OICR_HLP_HH_COMP_M BIT(10) +#define PF0INT_OICR_HLP_RSV1_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PF0INT_OICR_HLP_RSV1_M : E800_PF0INT_OICR_HLP_RSV1_M) +#define E800_PF0INT_OICR_HLP_RSV1_M MAKEMASK(0xFF, 2) +#define E830_PF0INT_OICR_HLP_RSV1_M MAKEMASK(0x3F, 2) +#define E800_PF0INT_OICR_HLP_HH_COMP_S 10 +#define E800_PF0INT_OICR_HLP_HH_COMP_M BIT(10) #define PF0INT_OICR_HLP_TSYN_TX_S 11 #define PF0INT_OICR_HLP_TSYN_TX_M BIT(11) #define PF0INT_OICR_HLP_TSYN_EVNT_S 12 @@ -4745,9 +4757,11 @@ #define PF0INT_OICR_PSM_QUEUE_S 1 #define PF0INT_OICR_PSM_QUEUE_M BIT(1) #define PF0INT_OICR_PSM_RSV1_S 2 -#define PF0INT_OICR_PSM_RSV1_M MAKEMASK(0xFF, 2) -#define PF0INT_OICR_PSM_HH_COMP_S 10 -#define PF0INT_OICR_PSM_HH_COMP_M BIT(10) +#define PF0INT_OICR_PSM_RSV1_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PF0INT_OICR_PSM_RSV1_M : E800_PF0INT_OICR_PSM_RSV1_M) +#define E800_PF0INT_OICR_PSM_RSV1_M MAKEMASK(0xFF, 2) +#define E830_PF0INT_OICR_PSM_RSV1_M MAKEMASK(0x3F, 2) +#define E800_PF0INT_OICR_PSM_HH_COMP_S 10 +#define E800_PF0INT_OICR_PSM_HH_COMP_M BIT(10) #define PF0INT_OICR_PSM_TSYN_TX_S 11 #define PF0INT_OICR_PSM_TSYN_TX_M BIT(11) #define PF0INT_OICR_PSM_TSYN_EVNT_S 12 @@ -4868,9 +4882,11 @@ #define PFINT_OICR_QUEUE_S 1 #define PFINT_OICR_QUEUE_M BIT(1) #define PFINT_OICR_RSV1_S 2 -#define PFINT_OICR_RSV1_M MAKEMASK(0xFF, 2) -#define PFINT_OICR_HH_COMP_S 10 -#define PFINT_OICR_HH_COMP_M BIT(10) +#define PFINT_OICR_RSV1_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PFINT_OICR_RSV1_M : E800_PFINT_OICR_RSV1_M) +#define E800_PFINT_OICR_RSV1_M MAKEMASK(0xFF, 2) +#define E830_PFINT_OICR_RSV1_M MAKEMASK(0x3F, 2) +#define E800_PFINT_OICR_HH_COMP_S 10 +#define E800_PFINT_OICR_HH_COMP_M BIT(10) #define PFINT_OICR_TSYN_TX_S 11 #define PFINT_OICR_TSYN_TX_M BIT(11) #define PFINT_OICR_TSYN_EVNT_S 12 @@ -4936,7 +4952,9 @@ #define PFINT_SB_CTL_INTEVENT_M BIT(31) #define PFINT_TSYN_MSK 0x0016C980 /* Reset Source: CORER */ #define PFINT_TSYN_MSK_PHY_INDX_S 0 -#define PFINT_TSYN_MSK_PHY_INDX_M MAKEMASK(0x1F, 0) +#define PFINT_TSYN_MSK_PHY_INDX_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PFINT_TSYN_MSK_PHY_INDX_M : E800_PFINT_TSYN_MSK_PHY_INDX_M) +#define E800_PFINT_TSYN_MSK_PHY_INDX_M MAKEMASK(0x1F, 0) +#define E830_PFINT_TSYN_MSK_PHY_INDX_M MAKEMASK(0xFF, 0) #define QINT_RQCTL(_QRX) (0x00150000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */ #define QINT_RQCTL_MAX_INDEX 2047 #define QINT_RQCTL_MSIX_INDX_S 0 @@ -5443,12 +5461,15 @@ #define GL_FWRESETCNT 0x00083100 /* Reset Source: POR */ #define GL_FWRESETCNT_FWRESETCNT_S 0 #define GL_FWRESETCNT_FWRESETCNT_M MAKEMASK(0xFFFFFFFF, 0) -#define GL_MNG_FW_RAM_STAT 0x0008309C /* Reset Source: POR */ +#define GL_MNG_FW_RAM_STAT_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_MNG_FW_RAM_STAT : E800_GL_MNG_FW_RAM_STAT) +#define E800_GL_MNG_FW_RAM_STAT 0x0008309C /* Reset Source: POR */ +#define E830_GL_MNG_FW_RAM_STAT 0x000830F4 /* Reset Source: POR */ #define GL_MNG_FW_RAM_STAT_FW_RAM_RST_STAT_S 0 #define GL_MNG_FW_RAM_STAT_FW_RAM_RST_STAT_M BIT(0) #define GL_MNG_FW_RAM_STAT_MNG_MEM_ECC_ERR_S 1 #define GL_MNG_FW_RAM_STAT_MNG_MEM_ECC_ERR_M BIT(1) #define GL_MNG_FWSM 0x000B6134 /* Reset Source: POR */ +#define GL_MNG_FWSM_FW_LOADING_M BIT(30) #define GL_MNG_FWSM_FW_MODES_S 0 #define GL_MNG_FWSM_FW_MODES_M MAKEMASK(0x7, 0) #define GL_MNG_FWSM_RSV0_S 3 -- 2.43.0