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Thu, 7 Mar 2019 09:48:21 +0000 (GMT) To: "Gavin Hu (Arm Technology China)" , "dev@dpdk.org" Cc: nd , "thomas@monjalon.net" , "jerinj@marvell.com" , "hemant.agrawal@nxp.com" , "Nipun.gupta@nxp.com" , Honnappa Nagarahalli , "olivier.matz@6wind.com" From: Ilya Maximets Message-ID: Date: Thu, 7 Mar 2019 12:48:21 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.5.1 MIME-Version: 1.0 In-Reply-To: Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrMKsWRmVeSWpSXmKPExsWy7djP87rPXzTEGPROFbR492k7k8XJF68Y LVY+3shmMfNpC7vFlfaf7Ba952czWpxZ3sNsce74aUaLrU0bmSw+PTjB4sDlcbH/DqPHmnlr GD1+LVjK6jF54UVmj2M3p7F7bHy3g8mjb8sqxgD2KC6blNSczLLUIn27BK6M5dcnsxV8lKn4 +u4sewPjafEuRk4OCQETiZYFnUxdjFwcQgIrGCV2HDjKAuF8YZT4sHwBM4TzmVGi7ckyti5G DrCWKU1sIN1CAssZJX43OULUfGSUOLtzHiNIjbBAgMSddn6QGhGBSIlrpz+DDWUW2M0k8eF7 PzNIgk1AR+LU6iOMIDavgJ3E1Bf7wWwWARWJSUcng9WICkRIvH+6mwWiRlDi5MwnYDanQKzE +T1tYDXMAuISTV9WskLY8hLb384BO1pC4B67xKXFO5kh/nSROHEPollCQFji1fEt7BC2jMT/ nfOZIOx6ifstLxkhmjsYJaYf+geVsJfY8vocO8hnzAKaEut36UOEHSUuT21hggQKn8SNt4IQ N/BJTNo2nRkizCvR0SYEUa0i8fvgcqhrpCRuvvvMPoFRaRaSz2Yh+WYWkm9mIexdwMiyilE8 tbQ4Nz212DgvtVyvODG3uDQvXS85P3cTIzBpnf53/OsOxn1/kg4xCnAwKvHwJlyqjxFiTSwr rsw9xCjBwawkwvvjeUOMEG9KYmVValF+fFFpTmrxIUZpDhYlcd5qhgfRQgLpiSWp2ampBalF MFkmDk6pBsakuP49/SpSc25UKIZNvBXwJvnxjuJLPw/fM5c9dd3S0yjJfbfJur0Cuw1FeEuO Hqy92DC5wDnnmscxw8OsVlcNZx2z2tZx3mw1j6qdZPXkHQ1LQuJ3mHixKZ/+8ETGu1t+c2lN 7Knnl/b///k+5cv1L48nFTZOqs48kqx2Mn3PwuS//z1uPHVVYinOSDTUYi4qTgQAu7Nqs1YD AAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrOIsWRmVeSWpSXmKPExsVy+t/xe7rPXjTEGGzfxmvx7tN2JouTL14x Wqx8vJHNYubTFnaLK+0/2S16z89mtDizvIfZ4tzx04wWW5s2Mll8enCCxYHL42L/HUaPNfPW MHr8WrCU1WPywovMHsduTmP32PhuB5NH35ZVjAHsUXo2RfmlJakKGfnFJbZK0YYWRnqGlhZ6 RiaWeobG5rFWRqZK+nY2Kak5mWWpRfp2CXoZy69PZiv4KFPx9d1Z9gbG0+JdjBwcEgImElOa 2LoYuTiEBJYySkxbvYy5i5ETKC4l8ePXBVYIW1jiz7UuNhBbSOA9o8TKnQogtrCAn8SyZ4/A 4iICkRJPtrSygAxiFtjLJDGtvYMJYuplJomHq3uYQKrYBHQkTq0+wghi8wrYSUx9sR/MZhFQ kZh0dDLYZlGBCIm7F1+wQNQISpyc+QTM5hSIlTi/pw2shllAXeLPvEtQtrhE05eVrBC2vMT2 t3OYJzAKzULSPgtJyywkLbOQtCxgZFnFKJJaWpybnltsqFecmFtcmpeul5yfu4kRGKnbjv3c vIPx0sbgQ4wCHIxKPLwRp+tjhFgTy4orcw8xSnAwK4nw/njeECPEm5JYWZValB9fVJqTWnyI 0RTouYnMUqLJ+cAkklcSb2hqaG5haWhubG5sZqEkznveoDJKSCA9sSQ1OzW1ILUIpo+Jg1Oq gTFe4hbjBbOHeetfJf+YZj7LwfBjMN/39t1fmWLnvVSb3eJuWy0Z4bSghsd51sTv8l3XS/9s VVh3VXdKsusJwRnv/O1nXJb9dm13W23/zYWCQvMvHD2pWSkxc3nj/dxbmu7L8+9v0f/x499e vst+Ok9i11xfnzT3tJLBpT9npGbVWfvl/HLTYk9TYinOSDTUYi4qTgQAaf1RTuoCAAA= X-CMS-MailID: 20190307094822eucas1p2264609593248a009cc798711e715c6a6 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20190307064616epcas4p141948c129d532da259eab6fd3e6e4dc7 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190307064616epcas4p141948c129d532da259eab6fd3e6e4dc7 References: <1551841661-42892-1-git-send-email-gavin.hu@arm.com> <1551941137-33250-1-git-send-email-gavin.hu@arm.com> <3cdf6747-21f3-d77e-0935-d73b5cc617f6@samsung.com> Subject: Re: [dpdk-dev] [PATCH v2] ring: enforce reading the tails before ring operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Mar 2019 09:48:25 -0000 On 07.03.2019 12:27, Gavin Hu (Arm Technology China) wrote: > > >> -----Original Message----- >> From: Ilya Maximets >> Sent: Thursday, March 7, 2019 4:52 PM >> To: Gavin Hu (Arm Technology China) ; >> dev@dpdk.org >> Cc: nd ; thomas@monjalon.net; jerinj@marvell.com; >> hemant.agrawal@nxp.com; Nipun.gupta@nxp.com; Honnappa Nagarahalli >> ; olivier.matz@6wind.com >> Subject: Re: [PATCH v2] ring: enforce reading the tails before ring >> operations >> >> On 07.03.2019 9:45, gavin hu wrote: >>> In weak memory models, like arm64, reading the {prod,cons}.tail may get >>> reordered after reading or writing the ring slots, which corrupts the ring >>> and stale data is observed. >>> >>> This issue was reported by NXP on 8-A72 DPAA2 board. The problem is >> most >>> likely caused by missing the acquire semantics when reading cons.tail (in >>> SP enqueue) or prod.tail (in SC dequeue) which makes it possible to read >> a >>> stale value from the ring slots. >>> >>> For MP (and MC) case, rte_atomic32_cmpset() already provides the >> required >>> ordering. This patch is to prevent reading and writing the ring slots get >>> reordered before reading {prod,cons}.tail for SP (and SC) case. >> >> Read barrier rte_smp_rmb() is OK to prevent reading the ring get >> reordered >> before reading the tail. However, to prevent *writing* the ring get >> reordered >> *before reading* the tail you need a full memory barrier, i.e. >> rte_smp_mb(). > > ISHLD(rte_smp_rmb is DMB(ishld) orders LD/LD and LD/ST, while WMB(ST Option) orders ST/ST. > For more details, please refer to: Table B2-1 Encoding of the DMB and DSB