[PATCH v4 025/103] net/ice/base: avoid stale PHY commands in ice_ptp_one_port_cmd

[Anatoly Burakov <anatoly.burakov@intel.com>]

From: Jacob Keller <jacob.e.keller@intel.com>

Code using ice_ptp_one_port_cmd() (or the device specific variants for E822 and
ETH56G) has a subtle bug where-in the executing of ice_ptp_exec_tmr_cmd() will
cause all other ports to execute their last executed command.

Most flows operate on all timers at once, but some flows such as handling link
state change only operate on one port at a time. This can lead to issues if the
userspace performs clock operations at just the right time.

In addition to this bug, recent support for new hardware families has
complicated the structure and organization of the various functions involved in
programming PHY ports.

For example:

 * ETH56G and E822 both re-implement the same looping structure for operating on
   all ports
 * E810 and E830 use "ice_ptp_port_cmd" which takes a register value to write
   and only operates on these two families despite having a generic name.

Refactor ice_ptp_one_port_cmd() to both fix the issue of stale PHY port
commands, and reduce the organizational complexity.

Rename the existing device implementations from ice_ptp_one_port_cmd_<device> to
ice_ptp_write_port_cmd_<device>. This function just performs the task of writing
one command to one port. Do not export this outside of ice_ptp_hw.c, instead
ensure all callers use the refactored ice_ptp_one_port_cmd() which properly
initializes all ports.

Fix ice_ptp_one_port_cmd() to correctly loop over all ports. For the configured
port, call ice_ptp_write_port_cmd() with the configured command. For all other
ports, call ice_ptp_write_port_cmd() with ICE_PTP_NOP.

Stop duplicating the port iteration logic in each of the
ice_ptp_port_cmd_<dev>() implementations, instead moving this into the generic
ice_ptp_port_cmd() implementation.

Since every flow now properly initializes both the main timer register and all
port registers, ice_ptp_clean_cmd() is no longer needed, so remove it.

This fixes the issue of using stale PHY port commands, and aligns better with
the flow for how ice_ptp_hw.c is implemented.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
---
 drivers/net/ice/base/ice_ptp_hw.c | 311 +++++++++++++-----------------
 drivers/net/ice/base/ice_ptp_hw.h |  23 ++-
 2 files changed, 153 insertions(+), 181 deletions(-)

diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c
index e9079e6ed9..27451a5897 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -898,18 +898,6 @@ static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw)
 	ice_flush(hw);
 }
 
-/**
- * ice_ptp_clean_cmd - Clean the timer command register
- * @hw: pointer to HW struct
- *
- * Zero out the GLTSYN_CMD to avoid any residual command execution.
- */
-static void ice_ptp_clean_cmd(struct ice_hw *hw)
-{
-	wr32(hw, GLTSYN_CMD, 0);
-	ice_flush(hw);
-}
-
 /* 56G PHY access functions */
 static const u32 eth56g_port_base[ICE_NUM_PHY_PORTS] = {
 	ICE_PHY0_BASE,
@@ -1772,7 +1760,7 @@ ice_ptp_read_port_capture_eth56g(struct ice_hw *hw, u8 port, u64 *tx_ts,
 }
 
 /**
- * ice_ptp_one_port_cmd_eth56g - Prepare a single PHY port for a timer command
+ * ice_ptp_write_port_cmd_eth56g - Prepare a single PHY port for a timer command
  * @hw: pointer to HW struct
  * @port: Port to which cmd has to be sent
  * @cmd: Command to be sent to the port
@@ -1780,9 +1768,9 @@ ice_ptp_read_port_capture_eth56g(struct ice_hw *hw, u8 port, u64 *tx_ts,
  *
  * Prepare the requested port for an upcoming timer sync command.
  */
-int
-ice_ptp_one_port_cmd_eth56g(struct ice_hw *hw, u8 port,
-			    enum ice_ptp_tmr_cmd cmd, bool lock_sbq)
+static int
+ice_ptp_write_port_cmd_eth56g(struct ice_hw *hw, u8 port,
+			      enum ice_ptp_tmr_cmd cmd, bool lock_sbq)
 {
 	u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd);
 	int status;
@@ -1808,34 +1796,6 @@ ice_ptp_one_port_cmd_eth56g(struct ice_hw *hw, u8 port,
 	return 0;
 }
 
-/**
- * ice_ptp_port_cmd_eth56g - Prepare all ports for a timer command
- * @hw: pointer to the HW struct
- * @cmd: timer command to prepare
- * @lock_sbq: true if the sideband queue lock must  be acquired
- *
- * Prepare all ports connected to this device for an upcoming timer sync
- * command.
- */
-static int
-ice_ptp_port_cmd_eth56g(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
-			bool lock_sbq)
-{
-	int status;
-	u8 port;
-
-	for (port = 0; port < hw->max_phy_port; port++) {
-		if (!(hw->ena_lports & BIT(port)))
-			continue;
-
-		status = ice_ptp_one_port_cmd_eth56g(hw, port, cmd, lock_sbq);
-		if (status)
-			return status;
-	}
-
-	return 0;
-}
-
 /**
  * ice_calc_fixed_tx_offset_eth56g - Calculated Fixed Tx offset for a port
  * @hw: pointer to the HW struct
@@ -1964,13 +1924,12 @@ ice_read_phy_and_phc_time_eth56g(struct ice_hw *hw, u8 port, u64 *phy_time,
 	ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME);
 
 	/* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */
-	status = ice_ptp_one_port_cmd_eth56g(hw, port, ICE_PTP_READ_TIME, true);
+	status = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME, true);
 	if (status)
 		return status;
 
 	/* Issue the sync to start the ICE_PTP_READ_TIME capture */
 	ice_ptp_exec_tmr_cmd(hw);
-	ice_ptp_clean_cmd(hw);
 
 	/* Read the captured PHC time from the shadow time registers */
 	zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx));
@@ -2039,13 +1998,12 @@ static int ice_sync_phy_timer_eth56g(struct ice_hw *hw, u8 port)
 	if (status)
 		goto err_unlock;
 
-	status = ice_ptp_one_port_cmd_eth56g(hw, port, ICE_PTP_ADJ_TIME, true);
+	status = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME, true);
 	if (status)
 		goto err_unlock;
 
 	/* Issue the sync to activate the time adjustment */
 	ice_ptp_exec_tmr_cmd(hw);
-	ice_ptp_clean_cmd(hw);
 
 	/* Re-capture the timer values to flush the command registers and
 	 * verify that the time was properly adjusted.
@@ -2129,8 +2087,7 @@ ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool bypass)
 	if (status)
 		return status;
 
-	status = ice_ptp_one_port_cmd_eth56g(hw, port, ICE_PTP_INIT_INCVAL,
-					     true);
+	status = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL, true);
 	if (status)
 		return status;
 
@@ -2206,8 +2163,7 @@ ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status)
  * mask. Returns the mask of ports where TX timestamps are available
  * @hw: pointer to the HW struct
  */
-int
-ice_ptp_init_phy_cfg(struct ice_hw *hw)
+int ice_ptp_init_phy_cfg(struct ice_hw *hw)
 {
 	int status;
 	u32 phy_rev;
@@ -3175,7 +3131,7 @@ ice_ptp_read_port_capture_e822(struct ice_hw *hw, u8 port, u64 *tx_ts,
 }
 
 /**
- * ice_ptp_one_port_cmd_e822 - Prepare a single PHY port for a timer command
+ * ice_ptp_write_port_cmd_e822 - Prepare a single PHY port for a timer command
  * @hw: pointer to HW struct
  * @port: Port to which cmd has to be sent
  * @cmd: Command to be sent to the port
@@ -3187,8 +3143,8 @@ ice_ptp_read_port_capture_e822(struct ice_hw *hw, u8 port, u64 *tx_ts,
  * always handles all external PHYs internally.
  */
 int
-ice_ptp_one_port_cmd_e822(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd,
-			  bool lock_sbq)
+ice_ptp_write_port_cmd_e822(struct ice_hw *hw, u8 port,
+			    enum ice_ptp_tmr_cmd cmd, bool lock_sbq)
 {
 	u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd);
 	int status;
@@ -3214,32 +3170,6 @@ ice_ptp_one_port_cmd_e822(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd,
 	return 0;
 }
 
-/**
- * ice_ptp_port_cmd_e822 - Prepare all ports for a timer command
- * @hw: pointer to the HW struct
- * @cmd: timer command to prepare
- * @lock_sbq: true if the sideband queue lock must  be acquired
- *
- * Prepare all ports connected to this device for an upcoming timer sync
- * command.
- */
-static int
-ice_ptp_port_cmd_e822(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
-		      bool lock_sbq)
-{
-	u8 port;
-
-	for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
-		int status;
-
-		status = ice_ptp_one_port_cmd_e822(hw, port, cmd, lock_sbq);
-		if (status)
-			return status;
-	}
-
-	return 0;
-}
-
 /* E822 Vernier calibration functions
  *
  * The following functions are used as part of the vernier calibration of
@@ -4109,13 +4039,12 @@ ice_read_phy_and_phc_time_e822(struct ice_hw *hw, u8 port, u64 *phy_time,
 	ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME);
 
 	/* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */
-	status = ice_ptp_one_port_cmd_e822(hw, port, ICE_PTP_READ_TIME, true);
+	status = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME, true);
 	if (status)
 		return status;
 
 	/* Issue the sync to start the ICE_PTP_READ_TIME capture */
 	ice_ptp_exec_tmr_cmd(hw);
-	ice_ptp_clean_cmd(hw);
 
 	/* Read the captured PHC time from the shadow time registers */
 	zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx));
@@ -4181,7 +4110,7 @@ static int ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port)
 	if (status)
 		goto err_unlock;
 
-	status = ice_ptp_one_port_cmd_e822(hw, port, ICE_PTP_ADJ_TIME, true);
+	status = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME, true);
 	if (status)
 		goto err_unlock;
 
@@ -4190,7 +4119,6 @@ static int ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port)
 
 	/* Issue the sync to activate the time adjustment */
 	ice_ptp_exec_tmr_cmd(hw);
-	ice_ptp_clean_cmd(hw);
 
 	/* Re-capture the timer values to flush the command registers and
 	 * verify that the time was properly adjusted.
@@ -4286,7 +4214,6 @@ ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass)
 	u64 incval;
 	u8 tmr_idx;
 
-	ice_ptp_clean_cmd(hw);
 	tmr_idx = ice_get_ptp_src_clock_index(hw);
 
 	status = ice_stop_phy_timer_e822(hw, port, false);
@@ -4311,7 +4238,7 @@ ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass)
 	if (status)
 		return status;
 
-	status = ice_ptp_one_port_cmd_e822(hw, port, ICE_PTP_INIT_INCVAL, true);
+	status = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL, true);
 	if (status)
 		return status;
 
@@ -4339,7 +4266,7 @@ ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass)
 	if (status)
 		return status;
 
-	status = ice_ptp_one_port_cmd_e822(hw, port, ICE_PTP_INIT_INCVAL, true);
+	status = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL, true);
 	if (status)
 		return status;
 
@@ -4890,55 +4817,6 @@ ice_ptp_prep_phy_adj_target_e810(struct ice_hw *hw, u32 target_time)
 	return 0;
 }
 
-/**
- * ice_ptp_port_cmd - Prepare all external PHYs for a timer command
- * @hw: pointer to HW struct
- * @cmd: Command to be sent to the port
- * @lock_sbq: true if the sideband queue lock must be acquired
- * @eth_gltsyn_cmd_addr: address for ETH_GLTSYN_CMD register
- *
- * Prepare the external PHYs connected to this device for a timer sync
- * command.
- */
-static int
-ice_ptp_port_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
-		 bool lock_sbq, u32 eth_gltsyn_cmd_addr)
-{
-	int status;
-	u32 val;
-
-	switch (cmd) {
-	case ICE_PTP_INIT_TIME:
-		val = GLTSYN_CMD_INIT_TIME;
-		break;
-	case ICE_PTP_INIT_INCVAL:
-		val = GLTSYN_CMD_INIT_INCVAL;
-		break;
-	case ICE_PTP_ADJ_TIME:
-		val = GLTSYN_CMD_ADJ_TIME;
-		break;
-	case ICE_PTP_ADJ_TIME_AT_TIME:
-		val = GLTSYN_CMD_ADJ_INIT_TIME;
-		break;
-	case ICE_PTP_READ_TIME:
-		val = GLTSYN_CMD_READ_TIME;
-		break;
-	default:
-		ice_warn(hw, "Unknown timer command %u\n", cmd);
-		return ICE_ERR_PARAM;
-	}
-
-	status = ice_write_phy_reg_e810_lp(hw, eth_gltsyn_cmd_addr, val,
-					   lock_sbq);
-	if (status) {
-		ice_debug(hw, ICE_DBG_PTP, "Failed to write back GLTSYN_CMD, status %d\n",
-			  status);
-		return status;
-	}
-
-	return 0;
-}
-
 /**
  * ice_ptp_port_cmd_e810 - Prepare all external PHYs for a timer command
  * @hw: pointer to HW struct
@@ -4948,27 +4826,13 @@ ice_ptp_port_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
  * Prepare the external PHYs connected to this device for a timer sync
  * command.
  */
-static int
-ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
-		      bool lock_sbq)
+int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
+			  bool lock_sbq)
 {
-	return ice_ptp_port_cmd(hw, cmd, lock_sbq, E810_ETH_GLTSYN_CMD);
-}
+	u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd);
 
-/**
- * ice_ptp_port_cmd_e830 - Prepare all external PHYs for a timer command
- * @hw: pointer to HW struct
- * @cmd: Command to be sent to the port
- * @lock_sbq: true if the sideband queue lock must be acquired
- *
- * Prepare the external PHYs connected to this device for a timer sync
- * command.
- */
-static int
-ice_ptp_port_cmd_e830(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
-		      bool lock_sbq)
-{
-	return ice_ptp_port_cmd(hw, cmd, lock_sbq, E830_ETH_GLTSYN_CMD);
+	return ice_write_phy_reg_e810_lp(hw, E810_ETH_GLTSYN_CMD, val,
+					 lock_sbq);
 }
 
 /* E810T SMA functions
@@ -5249,6 +5113,25 @@ ice_ptp_write_direct_phc_time_e830(struct ice_hw *hw, u64 time)
 	return 0;
 }
 
+/**
+ * ice_ptp_port_cmd_e830 - Prepare all external PHYs for a timer command
+ * @hw: pointer to HW struct
+ * @cmd: Command to be sent to the port
+ * @lock_sbq: true if the sideband queue lock must be acquired
+ *
+ * Prepare the external PHYs connected to this device for a timer sync
+ * command.
+ */
+int
+ice_ptp_port_cmd_e830(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
+		      bool lock_sbq)
+{
+	u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd);
+
+	return ice_write_phy_reg_e810_lp(hw, E830_ETH_GLTSYN_CMD, val,
+					   lock_sbq);
+}
+
 /**
  * ice_read_phy_tstamp_e830 - Read a PHY timestamp out of the external PHY
  * @hw: pointer to the HW struct
@@ -5358,6 +5241,100 @@ void ice_ptp_unlock(struct ice_hw *hw)
 	wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0);
 }
 
+/**
+ * ice_ptp_write_port_cmd - Prepare a single PHY port for a timer command
+ * @hw: pointer to HW struct
+ * @port: Port to which cmd has to be sent
+ * @cmd: Command to be sent to the port
+ * @lock_sbq: true if the sideband queue lock must be acquired
+ *
+ * Prepare one port for the upcoming timer sync command. Do not use this for
+ * programming only a single port, instead use ice_ptp_one_port_cmd() to
+ * ensure non-modified ports get properly initialized to ICE_PTP_NOP.
+ */
+int ice_ptp_write_port_cmd(struct ice_hw *hw, u8 port,
+			   enum ice_ptp_tmr_cmd cmd, bool lock_sbq)
+{
+	switch (hw->phy_cfg) {
+	case ICE_PHY_ETH56G:
+		return ice_ptp_write_port_cmd_eth56g(hw, port, cmd, lock_sbq);
+	case ICE_PHY_E822:
+		return ice_ptp_write_port_cmd_e822(hw, port, cmd, lock_sbq);
+	default:
+		return ICE_ERR_NOT_SUPPORTED;
+	}
+}
+
+/**
+ * ice_ptp_one_port_cmd - Program one PHY port for a timer command
+ * @hw: pointer to HW struct
+ * @configured_port: the port that should execute the command
+ * @configured_cmd: the command to be executed on the configured port
+ * @lock_sbq: true if the sideband queue lock must be acquired
+ *
+ * Prepare one port for executing a timer command, while preparing all other
+ * ports to ICE_PTP_NOP. This allows executing a command on a single port
+ * while ensuring all other ports do not execute stale commands.
+ */
+int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port,
+			 enum ice_ptp_tmr_cmd configured_cmd, bool lock_sbq)
+{
+	u8 port;
+
+	for (port = 0; port < hw->max_phy_port; port++) {
+		enum ice_ptp_tmr_cmd cmd;
+		int status;
+
+		/* Program the configured port with the configured command,
+		 * program all other ports with ICE_PTP_NOP.
+		 */
+		cmd = port == configured_port ? configured_cmd : ICE_PTP_NOP;
+
+		status = ice_ptp_write_port_cmd(hw, port, cmd, lock_sbq);
+		if (status)
+			return status;
+	}
+
+	return 0;
+}
+
+/**
+ * ice_ptp_port_cmd - Prepare PHY ports for a timer sync command
+ * @hw: pointer to HW struct
+ * @cmd: the timer command to setup
+ * @lock_sbq: true of sideband queue lock must be acquired
+ *
+ * Prepare all PHY ports on this device for the requested timer command. For
+ * some families this can be done in one shot, but for other families each
+ * port must be configured individually.
+ */
+static int ice_ptp_port_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
+			    bool lock_sbq)
+{
+	u8 port;
+
+	/* PHY models which can program all ports simultaneously */
+	switch (hw->phy_cfg) {
+	case ICE_PHY_E830:
+		return ice_ptp_port_cmd_e830(hw, cmd, lock_sbq);
+	case ICE_PHY_E810:
+		return ice_ptp_port_cmd_e810(hw, cmd, lock_sbq);
+	default:
+		break;
+	}
+
+	/* PHY models which require programming each port separately */
+	for (port = 0; port < hw->max_phy_port; port++) {
+		int status;
+
+		status = ice_ptp_write_port_cmd(hw, port, cmd, lock_sbq);
+		if (status)
+			return status;
+	}
+
+	return 0;
+}
+
 /**
  * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command
  * @hw: pointer to HW struct
@@ -5378,22 +5355,7 @@ static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
 	ice_ptp_src_cmd(hw, cmd);
 
 	/* Next, prepare the ports */
-	switch (hw->phy_cfg) {
-	case ICE_PHY_ETH56G:
-		status = ice_ptp_port_cmd_eth56g(hw, cmd, lock_sbq);
-		break;
-	case ICE_PHY_E830:
-		status = ice_ptp_port_cmd_e830(hw, cmd, lock_sbq);
-		break;
-	case ICE_PHY_E810:
-		status = ice_ptp_port_cmd_e810(hw, cmd, lock_sbq);
-		break;
-	case ICE_PHY_E822:
-		status = ice_ptp_port_cmd_e822(hw, cmd, lock_sbq);
-		break;
-	default:
-		status = ICE_ERR_NOT_SUPPORTED;
-	}
+	status = ice_ptp_port_cmd(hw, cmd, lock_sbq);
 	if (status) {
 		ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, status %d\n",
 			  cmd, status);
@@ -5404,7 +5366,6 @@ static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
 	 * commands synchronously
 	 */
 	ice_ptp_exec_tmr_cmd(hw);
-	ice_ptp_clean_cmd(hw);
 
 	return 0;
 }
@@ -5431,7 +5392,7 @@ int ice_ptp_init_time(struct ice_hw *hw, u64 time)
 
 	/* Source timers */
 	/* For E830 we don't need to use shadow registers, its automatic */
-	if (ice_is_e830(hw))
+	if (hw->phy_cfg == ICE_PHY_E830)
 		return ice_ptp_write_direct_phc_time_e830(hw, time);
 
 	wr32(hw, GLTSYN_SHTIME_L(tmr_idx), ICE_LO_DWORD(time));
@@ -5482,7 +5443,7 @@ int ice_ptp_write_incval(struct ice_hw *hw, u64 incval)
 	tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
 
 	/* For E830 we don't need to use shadow registers, its automatic */
-	if (ice_is_e830(hw))
+	if (hw->phy_cfg == ICE_PHY_E830)
 		return ice_ptp_write_direct_incval_e830(hw, incval);
 
 	/* Shadow Adjust */
diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h
index 935c3f9648..f4110108e2 100644
--- a/drivers/net/ice/base/ice_ptp_hw.h
+++ b/drivers/net/ice/base/ice_ptp_hw.h
@@ -143,6 +143,9 @@ int
 ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);
 int ice_ptp_init_phc(struct ice_hw *hw);
 bool refsync_pin_id_valid(struct ice_hw *hw, u8 id);
+int
+ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port,
+		     enum ice_ptp_tmr_cmd configured_cmd, bool lock_sbq);
 
 /* E822 family functions */
 int
@@ -162,12 +165,15 @@ int
 ice_ptp_read_port_capture_e822(struct ice_hw *hw, u8 port,
 			       u64 *tx_ts, u64 *rx_ts);
 int
-ice_ptp_one_port_cmd_e822(struct ice_hw *hw, u8 port,
-			  enum ice_ptp_tmr_cmd cmd, bool lock_sbq);
-int
 ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,
 		     enum ice_clk_src clk_src);
 int
+ice_ptp_write_port_cmd_e822(struct ice_hw *hw, u8 port,
+			    enum ice_ptp_tmr_cmd cmd, bool lock_sbq);
+int
+ice_ptp_write_port_cmd(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd,
+		       bool lock_sbq);
+int
 ice_cfg_cgu_pll_e825c(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq,
 		      enum ice_clk_src *clk_src);
 int
@@ -179,6 +185,14 @@ int
 ice_cfg_cgu_bypass_mux_e825c(struct ice_hw *hw, u8 port_num, bool clock_1588,
 			     unsigned int ena);
 int ice_cfg_synce_ethdiv_e825c(struct ice_hw *hw, u8 *divider);
+
+/* E8 Family */
+int
+ice_ptp_port_cmd_e830(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
+		      bool lock_sbq);
+int
+ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
+		      bool lock_sbq);
 int
 ice_get_phy_tx_tstamp_ready_e830(struct ice_hw *hw, u8 port, u64 *tstamp_ready);
 
@@ -270,9 +284,6 @@ int
 ice_ptp_read_port_capture_eth56g(struct ice_hw *hw, u8 port,
 				 u64 *tx_ts, u64 *rx_ts);
 int
-ice_ptp_one_port_cmd_eth56g(struct ice_hw *hw, u8 port,
-			    enum ice_ptp_tmr_cmd cmd, bool lock_sbq);
-int
 ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status);
 int
 ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset);
-- 
2.43.0