* [PATCH v2 1/6] net/axgbe: always attempt link training in KR mode
2022-01-25 12:17 [PATCH v2 0/6] axgbe pmd updates ssebasti
@ 2022-01-25 12:17 ` ssebasti
2022-01-27 13:45 ` Namburu, Chandu-babu
2022-01-25 12:17 ` [PATCH v2 2/6] net/axgbe: toggle PLL settings during rate change ssebasti
` (6 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: ssebasti @ 2022-01-25 12:17 UTC (permalink / raw)
To: dev
From: Selwin Sebastian <selwin.sebastian@amd.com>
Link training is always attempted when in KR mode, but the code is
structured to check if link training has been enabled before attempting
to perform it.Since that check will always be true, simplify the code
to always enable and start link training during KR auto-negotiation.
Signed-off-by: Selwin Sebastian <selwin.sebastian@amd.com>
---
drivers/net/axgbe/axgbe_mdio.c | 62 ++++++++--------------------------
1 file changed, 15 insertions(+), 47 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_mdio.c b/drivers/net/axgbe/axgbe_mdio.c
index 32d8c666f9..913ceada0d 100644
--- a/drivers/net/axgbe/axgbe_mdio.c
+++ b/drivers/net/axgbe/axgbe_mdio.c
@@ -80,31 +80,10 @@ static void axgbe_an_clear_interrupts_all(struct axgbe_port *pdata)
axgbe_an37_clear_interrupts(pdata);
}
-static void axgbe_an73_enable_kr_training(struct axgbe_port *pdata)
-{
- unsigned int reg;
-
- reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
- reg |= AXGBE_KR_TRAINING_ENABLE;
- XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
-}
-
-static void axgbe_an73_disable_kr_training(struct axgbe_port *pdata)
-{
- unsigned int reg;
-
- reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
-
- reg &= ~AXGBE_KR_TRAINING_ENABLE;
- XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
-}
static void axgbe_kr_mode(struct axgbe_port *pdata)
{
- /* Enable KR training */
- axgbe_an73_enable_kr_training(pdata);
-
/* Set MAC to 10G speed */
pdata->hw_if.set_speed(pdata, SPEED_10000);
@@ -114,9 +93,6 @@ static void axgbe_kr_mode(struct axgbe_port *pdata)
static void axgbe_kx_2500_mode(struct axgbe_port *pdata)
{
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
-
/* Set MAC to 2.5G speed */
pdata->hw_if.set_speed(pdata, SPEED_2500);
@@ -126,9 +102,6 @@ static void axgbe_kx_2500_mode(struct axgbe_port *pdata)
static void axgbe_kx_1000_mode(struct axgbe_port *pdata)
{
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
-
/* Set MAC to 1G speed */
pdata->hw_if.set_speed(pdata, SPEED_1000);
@@ -142,8 +115,6 @@ static void axgbe_sfi_mode(struct axgbe_port *pdata)
if (pdata->kr_redrv)
return axgbe_kr_mode(pdata);
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
/* Set MAC to 10G speed */
pdata->hw_if.set_speed(pdata, SPEED_10000);
@@ -154,8 +125,6 @@ static void axgbe_sfi_mode(struct axgbe_port *pdata)
static void axgbe_x_mode(struct axgbe_port *pdata)
{
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
/* Set MAC to 1G speed */
pdata->hw_if.set_speed(pdata, SPEED_1000);
@@ -166,8 +135,6 @@ static void axgbe_x_mode(struct axgbe_port *pdata)
static void axgbe_sgmii_1000_mode(struct axgbe_port *pdata)
{
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
/* Set MAC to 1G speed */
pdata->hw_if.set_speed(pdata, SPEED_1000);
@@ -178,8 +145,6 @@ static void axgbe_sgmii_1000_mode(struct axgbe_port *pdata)
static void axgbe_sgmii_100_mode(struct axgbe_port *pdata)
{
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
/* Set MAC to 1G speed */
pdata->hw_if.set_speed(pdata, SPEED_1000);
@@ -284,6 +249,12 @@ static void axgbe_an73_set(struct axgbe_port *pdata, bool enable,
{
unsigned int reg;
+ /* Disable KR training for now */
+ reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
+ reg &= ~AXGBE_KR_TRAINING_ENABLE;
+ XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
+
+ /* Update AN settings */
reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
reg &= ~MDIO_AN_CTRL1_ENABLE;
@@ -379,20 +350,17 @@ static enum axgbe_an axgbe_an73_tx_training(struct axgbe_port *pdata,
XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg);
/* Start KR training */
- reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
- if (reg & AXGBE_KR_TRAINING_ENABLE) {
- if (pdata->phy_if.phy_impl.kr_training_pre)
- pdata->phy_if.phy_impl.kr_training_pre(pdata);
+ if (pdata->phy_if.phy_impl.kr_training_pre)
+ pdata->phy_if.phy_impl.kr_training_pre(pdata);
- reg |= AXGBE_KR_TRAINING_START;
- XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL,
- reg);
-
- PMD_DRV_LOG(DEBUG, "KR training initiated\n");
+ reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
+ reg |= AXGBE_KR_TRAINING_ENABLE;
+ reg |= AXGBE_KR_TRAINING_START;
+ XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
- if (pdata->phy_if.phy_impl.kr_training_post)
- pdata->phy_if.phy_impl.kr_training_post(pdata);
- }
+ PMD_DRV_LOG(DEBUG, "KR training initiated\n");
+ if (pdata->phy_if.phy_impl.kr_training_post)
+ pdata->phy_if.phy_impl.kr_training_post(pdata);
return AXGBE_AN_PAGE_RECEIVED;
}
--
2.25.1
^ permalink raw reply [flat|nested] 16+ messages in thread* RE: [PATCH v2 1/6] net/axgbe: always attempt link training in KR mode
2022-01-25 12:17 ` [PATCH v2 1/6] net/axgbe: always attempt link training in KR mode ssebasti
@ 2022-01-27 13:45 ` Namburu, Chandu-babu
0 siblings, 0 replies; 16+ messages in thread
From: Namburu, Chandu-babu @ 2022-01-27 13:45 UTC (permalink / raw)
To: Sebastian, Selwin, dev
[Public]
Acked-by: Chandubabu Namburu <chandu@amd.com>
-----Original Message-----
From: ssebasti@amd.com <ssebasti@amd.com>
Sent: Tuesday, January 25, 2022 5:48 PM
To: dev@dpdk.org
Subject: [PATCH v2 1/6] net/axgbe: always attempt link training in KR mode
From: Selwin Sebastian <selwin.sebastian@amd.com>
Link training is always attempted when in KR mode, but the code is structured to check if link training has been enabled before attempting to perform it.Since that check will always be true, simplify the code to always enable and start link training during KR auto-negotiation.
Signed-off-by: Selwin Sebastian <selwin.sebastian@amd.com>
---
drivers/net/axgbe/axgbe_mdio.c | 62 ++++++++--------------------------
1 file changed, 15 insertions(+), 47 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_mdio.c b/drivers/net/axgbe/axgbe_mdio.c index 32d8c666f9..913ceada0d 100644
--- a/drivers/net/axgbe/axgbe_mdio.c
+++ b/drivers/net/axgbe/axgbe_mdio.c
@@ -80,31 +80,10 @@ static void axgbe_an_clear_interrupts_all(struct axgbe_port *pdata)
axgbe_an37_clear_interrupts(pdata);
}
-static void axgbe_an73_enable_kr_training(struct axgbe_port *pdata) -{
- unsigned int reg;
-
- reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
- reg |= AXGBE_KR_TRAINING_ENABLE;
- XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
-}
-
-static void axgbe_an73_disable_kr_training(struct axgbe_port *pdata) -{
- unsigned int reg;
-
- reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
-
- reg &= ~AXGBE_KR_TRAINING_ENABLE;
- XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
-}
static void axgbe_kr_mode(struct axgbe_port *pdata) {
- /* Enable KR training */
- axgbe_an73_enable_kr_training(pdata);
-
/* Set MAC to 10G speed */
pdata->hw_if.set_speed(pdata, SPEED_10000);
@@ -114,9 +93,6 @@ static void axgbe_kr_mode(struct axgbe_port *pdata)
static void axgbe_kx_2500_mode(struct axgbe_port *pdata) {
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
-
/* Set MAC to 2.5G speed */
pdata->hw_if.set_speed(pdata, SPEED_2500);
@@ -126,9 +102,6 @@ static void axgbe_kx_2500_mode(struct axgbe_port *pdata)
static void axgbe_kx_1000_mode(struct axgbe_port *pdata) {
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
-
/* Set MAC to 1G speed */
pdata->hw_if.set_speed(pdata, SPEED_1000);
@@ -142,8 +115,6 @@ static void axgbe_sfi_mode(struct axgbe_port *pdata)
if (pdata->kr_redrv)
return axgbe_kr_mode(pdata);
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
/* Set MAC to 10G speed */
pdata->hw_if.set_speed(pdata, SPEED_10000); @@ -154,8 +125,6 @@ static void axgbe_sfi_mode(struct axgbe_port *pdata)
static void axgbe_x_mode(struct axgbe_port *pdata) {
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
/* Set MAC to 1G speed */
pdata->hw_if.set_speed(pdata, SPEED_1000); @@ -166,8 +135,6 @@ static void axgbe_x_mode(struct axgbe_port *pdata)
static void axgbe_sgmii_1000_mode(struct axgbe_port *pdata) {
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
/* Set MAC to 1G speed */
pdata->hw_if.set_speed(pdata, SPEED_1000); @@ -178,8 +145,6 @@ static void axgbe_sgmii_1000_mode(struct axgbe_port *pdata)
static void axgbe_sgmii_100_mode(struct axgbe_port *pdata) {
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
/* Set MAC to 1G speed */
pdata->hw_if.set_speed(pdata, SPEED_1000); @@ -284,6 +249,12 @@ static void axgbe_an73_set(struct axgbe_port *pdata, bool enable, {
unsigned int reg;
+ /* Disable KR training for now */
+ reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
+ reg &= ~AXGBE_KR_TRAINING_ENABLE;
+ XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
+
+ /* Update AN settings */
reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
reg &= ~MDIO_AN_CTRL1_ENABLE;
@@ -379,20 +350,17 @@ static enum axgbe_an axgbe_an73_tx_training(struct axgbe_port *pdata,
XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg);
/* Start KR training */
- reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
- if (reg & AXGBE_KR_TRAINING_ENABLE) {
- if (pdata->phy_if.phy_impl.kr_training_pre)
- pdata->phy_if.phy_impl.kr_training_pre(pdata);
+ if (pdata->phy_if.phy_impl.kr_training_pre)
+ pdata->phy_if.phy_impl.kr_training_pre(pdata);
- reg |= AXGBE_KR_TRAINING_START;
- XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL,
- reg);
-
- PMD_DRV_LOG(DEBUG, "KR training initiated\n");
+ reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
+ reg |= AXGBE_KR_TRAINING_ENABLE;
+ reg |= AXGBE_KR_TRAINING_START;
+ XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
- if (pdata->phy_if.phy_impl.kr_training_post)
- pdata->phy_if.phy_impl.kr_training_post(pdata);
- }
+ PMD_DRV_LOG(DEBUG, "KR training initiated\n");
+ if (pdata->phy_if.phy_impl.kr_training_post)
+ pdata->phy_if.phy_impl.kr_training_post(pdata);
return AXGBE_AN_PAGE_RECEIVED;
}
--
2.25.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 2/6] net/axgbe: toggle PLL settings during rate change
2022-01-25 12:17 [PATCH v2 0/6] axgbe pmd updates ssebasti
2022-01-25 12:17 ` [PATCH v2 1/6] net/axgbe: always attempt link training in KR mode ssebasti
@ 2022-01-25 12:17 ` ssebasti
2022-01-27 13:39 ` Namburu, Chandu-babu
2022-01-25 12:17 ` [PATCH v2 3/6] net/axgbe: simplify mailbox interface rate change code ssebasti
` (5 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: ssebasti @ 2022-01-25 12:17 UTC (permalink / raw)
To: dev
From: Selwin Sebastian <selwin.sebastian@amd.com>
For each rate change command submission, the FW has to do a phy
power off sequence internally. For this to happen correctly, the
PLL re-initialization control setting has to be turned off before
sending mailbox commands and re-enabled once the command submission
is complete. Without the PLL control setting, the link up takes
longer time in a fixed phy configuration.
Signed-off-by: Selwin Sebastian <selwin.sebastian@amd.com>
---
drivers/net/axgbe/axgbe_common.h | 9 +++++++++
drivers/net/axgbe/axgbe_phy_impl.c | 22 ++++++++++++++++++++--
2 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index df0aa21a9b..5a7ac35b6a 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -1314,6 +1314,11 @@
#define MDIO_VEND2_PMA_CDR_CONTROL 0x8056
#endif
+#ifndef MDIO_VEND2_PMA_MISC_CTRL0
+#define MDIO_VEND2_PMA_MISC_CTRL0 0x8090
+#endif
+
+
#ifndef MDIO_CTRL1_SPEED1G
#define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
#endif
@@ -1392,6 +1397,10 @@ static inline uint32_t high32_value(uint64_t addr)
return (addr >> 32) & 0x0ffffffff;
}
+#define XGBE_PMA_PLL_CTRL_MASK BIT(15)
+#define XGBE_PMA_PLL_CTRL_SET BIT(15)
+#define XGBE_PMA_PLL_CTRL_CLEAR 0x0000
+
/*END*/
/* Bit setting and getting macros
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c
index 72104f8a3f..08d3484a11 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -1196,8 +1196,22 @@ static void axgbe_phy_set_redrv_mode(struct axgbe_port *pdata)
axgbe_phy_put_comm_ownership(pdata);
}
+static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable)
+{
+ XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
+ XGBE_PMA_PLL_CTRL_MASK,
+ enable ? XGBE_PMA_PLL_CTRL_SET
+ : XGBE_PMA_PLL_CTRL_CLEAR);
+
+ /* Wait for command to complete */
+ rte_delay_us(150);
+}
+
static void axgbe_phy_start_ratechange(struct axgbe_port *pdata)
{
+ /* Clear the PLL so that it helps in power down sequence */
+ axgbe_phy_pll_ctrl(pdata, false);
+
/* Log if a previous command did not complete */
if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for command\n");
@@ -1213,10 +1227,14 @@ static void axgbe_phy_complete_ratechange(struct axgbe_port *pdata)
wait = AXGBE_RATECHANGE_COUNT;
while (wait--) {
if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
- return;
-
+ goto reenable_pll;
rte_delay_us(1500);
}
+
+reenable_pll:
+ /* Re-enable the PLL control */
+ axgbe_phy_pll_ctrl(pdata, true);
+
PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n");
}
--
2.25.1
^ permalink raw reply [flat|nested] 16+ messages in thread* RE: [PATCH v2 2/6] net/axgbe: toggle PLL settings during rate change
2022-01-25 12:17 ` [PATCH v2 2/6] net/axgbe: toggle PLL settings during rate change ssebasti
@ 2022-01-27 13:39 ` Namburu, Chandu-babu
0 siblings, 0 replies; 16+ messages in thread
From: Namburu, Chandu-babu @ 2022-01-27 13:39 UTC (permalink / raw)
To: Sebastian, Selwin, dev
[Public]
Acked-by: Chandubabu Namburu <chandu@amd.com>
-----Original Message-----
From: ssebasti@amd.com <ssebasti@amd.com>
Sent: Tuesday, January 25, 2022 5:48 PM
To: dev@dpdk.org
Subject: [PATCH v2 2/6] net/axgbe: toggle PLL settings during rate change
From: Selwin Sebastian <selwin.sebastian@amd.com>
For each rate change command submission, the FW has to do a phy power off sequence internally. For this to happen correctly, the PLL re-initialization control setting has to be turned off before sending mailbox commands and re-enabled once the command submission is complete. Without the PLL control setting, the link up takes longer time in a fixed phy configuration.
Signed-off-by: Selwin Sebastian <selwin.sebastian@amd.com>
---
drivers/net/axgbe/axgbe_common.h | 9 +++++++++
drivers/net/axgbe/axgbe_phy_impl.c | 22 ++++++++++++++++++++--
2 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index df0aa21a9b..5a7ac35b6a 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -1314,6 +1314,11 @@
#define MDIO_VEND2_PMA_CDR_CONTROL 0x8056
#endif
+#ifndef MDIO_VEND2_PMA_MISC_CTRL0
+#define MDIO_VEND2_PMA_MISC_CTRL0 0x8090
+#endif
+
+
#ifndef MDIO_CTRL1_SPEED1G
#define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
#endif
@@ -1392,6 +1397,10 @@ static inline uint32_t high32_value(uint64_t addr)
return (addr >> 32) & 0x0ffffffff;
}
+#define XGBE_PMA_PLL_CTRL_MASK BIT(15)
+#define XGBE_PMA_PLL_CTRL_SET BIT(15)
+#define XGBE_PMA_PLL_CTRL_CLEAR 0x0000
+
/*END*/
/* Bit setting and getting macros
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c
index 72104f8a3f..08d3484a11 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -1196,8 +1196,22 @@ static void axgbe_phy_set_redrv_mode(struct axgbe_port *pdata)
axgbe_phy_put_comm_ownership(pdata);
}
+static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable) {
+ XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
+ XGBE_PMA_PLL_CTRL_MASK,
+ enable ? XGBE_PMA_PLL_CTRL_SET
+ : XGBE_PMA_PLL_CTRL_CLEAR);
+
+ /* Wait for command to complete */
+ rte_delay_us(150);
+}
+
static void axgbe_phy_start_ratechange(struct axgbe_port *pdata) {
+ /* Clear the PLL so that it helps in power down sequence */
+ axgbe_phy_pll_ctrl(pdata, false);
+
/* Log if a previous command did not complete */
if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for command\n"); @@ -1213,10 +1227,14 @@ static void axgbe_phy_complete_ratechange(struct axgbe_port *pdata)
wait = AXGBE_RATECHANGE_COUNT;
while (wait--) {
if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
- return;
-
+ goto reenable_pll;
rte_delay_us(1500);
}
+
+reenable_pll:
+ /* Re-enable the PLL control */
+ axgbe_phy_pll_ctrl(pdata, true);
+
PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n"); }
--
2.25.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 3/6] net/axgbe: simplify mailbox interface rate change code
2022-01-25 12:17 [PATCH v2 0/6] axgbe pmd updates ssebasti
2022-01-25 12:17 ` [PATCH v2 1/6] net/axgbe: always attempt link training in KR mode ssebasti
2022-01-25 12:17 ` [PATCH v2 2/6] net/axgbe: toggle PLL settings during rate change ssebasti
@ 2022-01-25 12:17 ` ssebasti
2022-01-27 13:39 ` Namburu, Chandu-babu
2022-01-25 12:17 ` [PATCH v2 4/6] net/axgbe: reset PHY Rx when mailbox command timeout ssebasti
` (4 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: ssebasti @ 2022-01-25 12:17 UTC (permalink / raw)
To: dev
From: Selwin Sebastian <selwin.sebastian@amd.com>
Simplify and centralize the mailbox command rate change interface by
having a single function perform the writes to the mailbox registers
to issue the request.
Signed-off-by: Selwin Sebastian <selwin.sebastian@amd.com>
---
drivers/net/axgbe/axgbe_phy_impl.c | 95 ++++++++----------------------
1 file changed, 23 insertions(+), 72 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c
index 08d3484a11..2ed94868b8 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -1207,21 +1207,26 @@ static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable)
rte_delay_us(150);
}
-static void axgbe_phy_start_ratechange(struct axgbe_port *pdata)
+static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata,
+ unsigned int cmd, unsigned int sub_cmd)
{
+ unsigned int s0 = 0;
+ unsigned int wait;
/* Clear the PLL so that it helps in power down sequence */
axgbe_phy_pll_ctrl(pdata, false);
/* Log if a previous command did not complete */
if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for command\n");
- else
- return;
-}
-static void axgbe_phy_complete_ratechange(struct axgbe_port *pdata)
-{
- unsigned int wait;
+ /* Construct the command */
+ XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
+ XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd);
+
+ /* Issue the command */
+ XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
+ XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
+ XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
/* Wait for command to complete */
wait = AXGBE_RATECHANGE_COUNT;
@@ -1240,21 +1245,10 @@ static void axgbe_phy_complete_ratechange(struct axgbe_port *pdata)
static void axgbe_phy_rrc(struct axgbe_port *pdata)
{
- unsigned int s0;
- axgbe_phy_start_ratechange(pdata);
/* Receiver Reset Cycle */
- s0 = 0;
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 5);
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
-
- /* Call FW to make the change */
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
- XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
-
- axgbe_phy_complete_ratechange(pdata);
+ axgbe_phy_perform_ratechange(pdata, 5, 0);
PMD_DRV_LOG(DEBUG, "receiver reset complete\n");
}
@@ -1263,13 +1257,9 @@ static void axgbe_phy_power_off(struct axgbe_port *pdata)
{
struct axgbe_phy_data *phy_data = pdata->phy_data;
- axgbe_phy_start_ratechange(pdata);
+ /* Power off */
+ axgbe_phy_perform_ratechange(pdata, 0, 0);
- /* Call FW to make the change */
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, 0);
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
- XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
- axgbe_phy_complete_ratechange(pdata);
phy_data->cur_mode = AXGBE_MODE_UNKNOWN;
PMD_DRV_LOG(DEBUG, "phy powered off\n");
@@ -1278,31 +1268,21 @@ static void axgbe_phy_power_off(struct axgbe_port *pdata)
static void axgbe_phy_sfi_mode(struct axgbe_port *pdata)
{
struct axgbe_phy_data *phy_data = pdata->phy_data;
- unsigned int s0;
axgbe_phy_set_redrv_mode(pdata);
- axgbe_phy_start_ratechange(pdata);
-
/* 10G/SFI */
- s0 = 0;
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 3);
if (phy_data->sfp_cable != AXGBE_SFP_CABLE_PASSIVE) {
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
+ axgbe_phy_perform_ratechange(pdata, 3, 0);
} else {
if (phy_data->sfp_cable_len <= 1)
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 1);
+ axgbe_phy_perform_ratechange(pdata, 3, 1);
else if (phy_data->sfp_cable_len <= 3)
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2);
+ axgbe_phy_perform_ratechange(pdata, 3, 2);
else
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3);
+ axgbe_phy_perform_ratechange(pdata, 3, 3);
}
- /* Call FW to make the change */
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
- XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
- axgbe_phy_complete_ratechange(pdata);
phy_data->cur_mode = AXGBE_MODE_SFI;
PMD_DRV_LOG(DEBUG, "10GbE SFI mode set\n");
@@ -1311,22 +1291,11 @@ static void axgbe_phy_sfi_mode(struct axgbe_port *pdata)
static void axgbe_phy_kr_mode(struct axgbe_port *pdata)
{
struct axgbe_phy_data *phy_data = pdata->phy_data;
- unsigned int s0;
axgbe_phy_set_redrv_mode(pdata);
- axgbe_phy_start_ratechange(pdata);
-
/* 10G/KR */
- s0 = 0;
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 4);
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
-
- /* Call FW to make the change */
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
- XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
- axgbe_phy_complete_ratechange(pdata);
+ axgbe_phy_perform_ratechange(pdata, 4, 0);
phy_data->cur_mode = AXGBE_MODE_KR;
PMD_DRV_LOG(DEBUG, "10GbE KR mode set\n");
@@ -1335,40 +1304,22 @@ static void axgbe_phy_kr_mode(struct axgbe_port *pdata)
static void axgbe_phy_kx_2500_mode(struct axgbe_port *pdata)
{
struct axgbe_phy_data *phy_data = pdata->phy_data;
- unsigned int s0;
axgbe_phy_set_redrv_mode(pdata);
- /* 2.5G/KX */
- axgbe_phy_start_ratechange(pdata);
- s0 = 0;
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 2);
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
-
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
-
- XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
+ /* 2.5G/KX */
+ axgbe_phy_perform_ratechange(pdata, 2, 0);
phy_data->cur_mode = AXGBE_MODE_KX_2500;
}
static void axgbe_phy_sgmii_1000_mode(struct axgbe_port *pdata)
{
struct axgbe_phy_data *phy_data = pdata->phy_data;
- unsigned int s0;
axgbe_phy_set_redrv_mode(pdata);
/* 1G/SGMII */
- axgbe_phy_start_ratechange(pdata);
- s0 = 0;
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 1);
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2);
-
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
-
- XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
+ axgbe_phy_perform_ratechange(pdata, 1, 2);
phy_data->cur_mode = AXGBE_MODE_SGMII_1000;
}
--
2.25.1
^ permalink raw reply [flat|nested] 16+ messages in thread* RE: [PATCH v2 3/6] net/axgbe: simplify mailbox interface rate change code
2022-01-25 12:17 ` [PATCH v2 3/6] net/axgbe: simplify mailbox interface rate change code ssebasti
@ 2022-01-27 13:39 ` Namburu, Chandu-babu
0 siblings, 0 replies; 16+ messages in thread
From: Namburu, Chandu-babu @ 2022-01-27 13:39 UTC (permalink / raw)
To: Sebastian, Selwin, dev
[Public]
Acked-by: Chandubabu Namburu <chandu@amd.com>
-----Original Message-----
From: ssebasti@amd.com <ssebasti@amd.com>
Sent: Tuesday, January 25, 2022 5:48 PM
To: dev@dpdk.org
Subject: [PATCH v2 3/6] net/axgbe: simplify mailbox interface rate change code
From: Selwin Sebastian <selwin.sebastian@amd.com>
Simplify and centralize the mailbox command rate change interface by having a single function perform the writes to the mailbox registers to issue the request.
Signed-off-by: Selwin Sebastian <selwin.sebastian@amd.com>
---
drivers/net/axgbe/axgbe_phy_impl.c | 95 ++++++++----------------------
1 file changed, 23 insertions(+), 72 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c
index 08d3484a11..2ed94868b8 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -1207,21 +1207,26 @@ static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable)
rte_delay_us(150);
}
-static void axgbe_phy_start_ratechange(struct axgbe_port *pdata)
+static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata,
+ unsigned int cmd, unsigned int sub_cmd)
{
+ unsigned int s0 = 0;
+ unsigned int wait;
/* Clear the PLL so that it helps in power down sequence */
axgbe_phy_pll_ctrl(pdata, false);
/* Log if a previous command did not complete */
if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for command\n");
- else
- return;
-}
-static void axgbe_phy_complete_ratechange(struct axgbe_port *pdata) -{
- unsigned int wait;
+ /* Construct the command */
+ XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
+ XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd);
+
+ /* Issue the command */
+ XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
+ XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
+ XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
/* Wait for command to complete */
wait = AXGBE_RATECHANGE_COUNT;
@@ -1240,21 +1245,10 @@ static void axgbe_phy_complete_ratechange(struct axgbe_port *pdata)
static void axgbe_phy_rrc(struct axgbe_port *pdata) {
- unsigned int s0;
- axgbe_phy_start_ratechange(pdata);
/* Receiver Reset Cycle */
- s0 = 0;
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 5);
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
-
- /* Call FW to make the change */
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
- XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
-
- axgbe_phy_complete_ratechange(pdata);
+ axgbe_phy_perform_ratechange(pdata, 5, 0);
PMD_DRV_LOG(DEBUG, "receiver reset complete\n"); } @@ -1263,13 +1257,9 @@ static void axgbe_phy_power_off(struct axgbe_port *pdata) {
struct axgbe_phy_data *phy_data = pdata->phy_data;
- axgbe_phy_start_ratechange(pdata);
+ /* Power off */
+ axgbe_phy_perform_ratechange(pdata, 0, 0);
- /* Call FW to make the change */
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, 0);
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
- XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
- axgbe_phy_complete_ratechange(pdata);
phy_data->cur_mode = AXGBE_MODE_UNKNOWN;
PMD_DRV_LOG(DEBUG, "phy powered off\n"); @@ -1278,31 +1268,21 @@ static void axgbe_phy_power_off(struct axgbe_port *pdata) static void axgbe_phy_sfi_mode(struct axgbe_port *pdata) {
struct axgbe_phy_data *phy_data = pdata->phy_data;
- unsigned int s0;
axgbe_phy_set_redrv_mode(pdata);
- axgbe_phy_start_ratechange(pdata);
-
/* 10G/SFI */
- s0 = 0;
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 3);
if (phy_data->sfp_cable != AXGBE_SFP_CABLE_PASSIVE) {
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
+ axgbe_phy_perform_ratechange(pdata, 3, 0);
} else {
if (phy_data->sfp_cable_len <= 1)
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 1);
+ axgbe_phy_perform_ratechange(pdata, 3, 1);
else if (phy_data->sfp_cable_len <= 3)
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2);
+ axgbe_phy_perform_ratechange(pdata, 3, 2);
else
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3);
+ axgbe_phy_perform_ratechange(pdata, 3, 3);
}
- /* Call FW to make the change */
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
- XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
- axgbe_phy_complete_ratechange(pdata);
phy_data->cur_mode = AXGBE_MODE_SFI;
PMD_DRV_LOG(DEBUG, "10GbE SFI mode set\n"); @@ -1311,22 +1291,11 @@ static void axgbe_phy_sfi_mode(struct axgbe_port *pdata) static void axgbe_phy_kr_mode(struct axgbe_port *pdata) {
struct axgbe_phy_data *phy_data = pdata->phy_data;
- unsigned int s0;
axgbe_phy_set_redrv_mode(pdata);
- axgbe_phy_start_ratechange(pdata);
-
/* 10G/KR */
- s0 = 0;
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 4);
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
-
- /* Call FW to make the change */
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
- XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
- axgbe_phy_complete_ratechange(pdata);
+ axgbe_phy_perform_ratechange(pdata, 4, 0);
phy_data->cur_mode = AXGBE_MODE_KR;
PMD_DRV_LOG(DEBUG, "10GbE KR mode set\n"); @@ -1335,40 +1304,22 @@ static void axgbe_phy_kr_mode(struct axgbe_port *pdata) static void axgbe_phy_kx_2500_mode(struct axgbe_port *pdata) {
struct axgbe_phy_data *phy_data = pdata->phy_data;
- unsigned int s0;
axgbe_phy_set_redrv_mode(pdata);
- /* 2.5G/KX */
- axgbe_phy_start_ratechange(pdata);
- s0 = 0;
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 2);
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
-
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
-
- XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
+ /* 2.5G/KX */
+ axgbe_phy_perform_ratechange(pdata, 2, 0);
phy_data->cur_mode = AXGBE_MODE_KX_2500; }
static void axgbe_phy_sgmii_1000_mode(struct axgbe_port *pdata) {
struct axgbe_phy_data *phy_data = pdata->phy_data;
- unsigned int s0;
axgbe_phy_set_redrv_mode(pdata);
/* 1G/SGMII */
- axgbe_phy_start_ratechange(pdata);
- s0 = 0;
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 1);
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2);
-
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
-
- XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
+ axgbe_phy_perform_ratechange(pdata, 1, 2);
phy_data->cur_mode = AXGBE_MODE_SGMII_1000; }
--
2.25.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 4/6] net/axgbe: reset PHY Rx when mailbox command timeout
2022-01-25 12:17 [PATCH v2 0/6] axgbe pmd updates ssebasti
` (2 preceding siblings ...)
2022-01-25 12:17 ` [PATCH v2 3/6] net/axgbe: simplify mailbox interface rate change code ssebasti
@ 2022-01-25 12:17 ` ssebasti
2022-01-27 13:39 ` Namburu, Chandu-babu
2022-01-25 12:17 ` [PATCH v2 5/6] net/axgbe: add support for new port mode ssebasti
` (3 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: ssebasti @ 2022-01-25 12:17 UTC (permalink / raw)
To: dev
From: Selwin Sebastian <selwin.sebastian@amd.com>
Sometimes mailbox commands timeout when the RX data path becomes
unresponsive. This prevents the submission of new mailbox commands
to DXIO. This patch identifies the timeout and resets the RX data
path so that the next message can be submitted properly.
Signed-off-by: Selwin Sebastian <selwin.sebastian@amd.com>
---
drivers/net/axgbe/axgbe_common.h | 14 ++++++++++++++
drivers/net/axgbe/axgbe_phy_impl.c | 29 ++++++++++++++++++++++++++++-
2 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index 5a7ac35b6a..a5431dd998 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -1270,10 +1270,18 @@
#define MDIO_PMA_10GBR_FECCTRL 0x00ab
#endif
+#ifndef MDIO_PMA_RX_CTRL1
+#define MDIO_PMA_RX_CTRL1 0x8051
+#endif
+
#ifndef MDIO_PCS_DIG_CTRL
#define MDIO_PCS_DIG_CTRL 0x8000
#endif
+#ifndef MDIO_PCS_DIGITAL_STAT
+#define MDIO_PCS_DIGITAL_STAT 0x8010
+#endif
+
#ifndef MDIO_AN_XNP
#define MDIO_AN_XNP 0x0016
#endif
@@ -1354,6 +1362,8 @@
#define AXGBE_KR_TRAINING_ENABLE BIT(1)
#define AXGBE_PCS_CL37_BP BIT(12)
+#define XGBE_PCS_PSEQ_STATE_MASK 0x1c
+#define XGBE_PCS_PSEQ_STATE_POWER_GOOD 0x10
#define AXGBE_AN_CL37_INT_CMPLT BIT(0)
#define AXGBE_AN_CL37_INT_MASK 0x01
@@ -1401,6 +1411,10 @@ static inline uint32_t high32_value(uint64_t addr)
#define XGBE_PMA_PLL_CTRL_SET BIT(15)
#define XGBE_PMA_PLL_CTRL_CLEAR 0x0000
+#define XGBE_PMA_RX_RST_0_MASK BIT(4)
+#define XGBE_PMA_RX_RST_0_RESET_ON 0x10
+#define XGBE_PMA_RX_RST_0_RESET_OFF 0x00
+
/*END*/
/* Bit setting and getting macros
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c
index 2ed94868b8..eefb03e94e 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -1196,6 +1196,28 @@ static void axgbe_phy_set_redrv_mode(struct axgbe_port *pdata)
axgbe_phy_put_comm_ownership(pdata);
}
+static void axgbe_phy_rx_reset(struct axgbe_port *pdata)
+{
+ int reg;
+
+ reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT,
+ XGBE_PCS_PSEQ_STATE_MASK);
+ if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) {
+ /* Mailbox command timed out, reset of RX block is required.
+ * This can be done by asseting the reset bit and wait for
+ * its compeletion.
+ */
+ XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
+ XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_ON);
+ rte_delay_us(20);
+ XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
+ XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_OFF);
+ rte_delay_us(45);
+ PMD_DRV_LOG(ERR, "firmware mailbox reset performed\n");
+ }
+}
+
+
static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable)
{
XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
@@ -1216,8 +1238,10 @@ static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata,
axgbe_phy_pll_ctrl(pdata, false);
/* Log if a previous command did not complete */
- if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
+ if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {
PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for command\n");
+ axgbe_phy_rx_reset(pdata);
+ }
/* Construct the command */
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
@@ -1235,6 +1259,9 @@ static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata,
goto reenable_pll;
rte_delay_us(1500);
}
+ PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n");
+ /* Reset on error */
+ axgbe_phy_rx_reset(pdata);
reenable_pll:
/* Re-enable the PLL control */
--
2.25.1
^ permalink raw reply [flat|nested] 16+ messages in thread* RE: [PATCH v2 4/6] net/axgbe: reset PHY Rx when mailbox command timeout
2022-01-25 12:17 ` [PATCH v2 4/6] net/axgbe: reset PHY Rx when mailbox command timeout ssebasti
@ 2022-01-27 13:39 ` Namburu, Chandu-babu
0 siblings, 0 replies; 16+ messages in thread
From: Namburu, Chandu-babu @ 2022-01-27 13:39 UTC (permalink / raw)
To: Sebastian, Selwin, dev
[Public]
Acked-by: Chandubabu Namburu <chandu@amd.com>
-----Original Message-----
From: ssebasti@amd.com <ssebasti@amd.com>
Sent: Tuesday, January 25, 2022 5:48 PM
To: dev@dpdk.org
Subject: [PATCH v2 4/6] net/axgbe: reset PHY Rx when mailbox command timeout
From: Selwin Sebastian <selwin.sebastian@amd.com>
Sometimes mailbox commands timeout when the RX data path becomes unresponsive. This prevents the submission of new mailbox commands to DXIO. This patch identifies the timeout and resets the RX data path so that the next message can be submitted properly.
Signed-off-by: Selwin Sebastian <selwin.sebastian@amd.com>
---
drivers/net/axgbe/axgbe_common.h | 14 ++++++++++++++
drivers/net/axgbe/axgbe_phy_impl.c | 29 ++++++++++++++++++++++++++++-
2 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index 5a7ac35b6a..a5431dd998 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -1270,10 +1270,18 @@
#define MDIO_PMA_10GBR_FECCTRL 0x00ab
#endif
+#ifndef MDIO_PMA_RX_CTRL1
+#define MDIO_PMA_RX_CTRL1 0x8051
+#endif
+
#ifndef MDIO_PCS_DIG_CTRL
#define MDIO_PCS_DIG_CTRL 0x8000
#endif
+#ifndef MDIO_PCS_DIGITAL_STAT
+#define MDIO_PCS_DIGITAL_STAT 0x8010
+#endif
+
#ifndef MDIO_AN_XNP
#define MDIO_AN_XNP 0x0016
#endif
@@ -1354,6 +1362,8 @@
#define AXGBE_KR_TRAINING_ENABLE BIT(1)
#define AXGBE_PCS_CL37_BP BIT(12)
+#define XGBE_PCS_PSEQ_STATE_MASK 0x1c
+#define XGBE_PCS_PSEQ_STATE_POWER_GOOD 0x10
#define AXGBE_AN_CL37_INT_CMPLT BIT(0)
#define AXGBE_AN_CL37_INT_MASK 0x01
@@ -1401,6 +1411,10 @@ static inline uint32_t high32_value(uint64_t addr)
#define XGBE_PMA_PLL_CTRL_SET BIT(15)
#define XGBE_PMA_PLL_CTRL_CLEAR 0x0000
+#define XGBE_PMA_RX_RST_0_MASK BIT(4)
+#define XGBE_PMA_RX_RST_0_RESET_ON 0x10
+#define XGBE_PMA_RX_RST_0_RESET_OFF 0x00
+
/*END*/
/* Bit setting and getting macros
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c
index 2ed94868b8..eefb03e94e 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -1196,6 +1196,28 @@ static void axgbe_phy_set_redrv_mode(struct axgbe_port *pdata)
axgbe_phy_put_comm_ownership(pdata);
}
+static void axgbe_phy_rx_reset(struct axgbe_port *pdata) {
+ int reg;
+
+ reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT,
+ XGBE_PCS_PSEQ_STATE_MASK);
+ if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) {
+ /* Mailbox command timed out, reset of RX block is required.
+ * This can be done by asseting the reset bit and wait for
+ * its compeletion.
+ */
+ XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
+ XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_ON);
+ rte_delay_us(20);
+ XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
+ XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_OFF);
+ rte_delay_us(45);
+ PMD_DRV_LOG(ERR, "firmware mailbox reset performed\n");
+ }
+}
+
+
static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable) {
XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0, @@ -1216,8 +1238,10 @@ static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata,
axgbe_phy_pll_ctrl(pdata, false);
/* Log if a previous command did not complete */
- if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
+ if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {
PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for command\n");
+ axgbe_phy_rx_reset(pdata);
+ }
/* Construct the command */
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd); @@ -1235,6 +1259,9 @@ static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata,
goto reenable_pll;
rte_delay_us(1500);
}
+ PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n");
+ /* Reset on error */
+ axgbe_phy_rx_reset(pdata);
reenable_pll:
/* Re-enable the PLL control */
--
2.25.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 5/6] net/axgbe: add support for new port mode
2022-01-25 12:17 [PATCH v2 0/6] axgbe pmd updates ssebasti
` (3 preceding siblings ...)
2022-01-25 12:17 ` [PATCH v2 4/6] net/axgbe: reset PHY Rx when mailbox command timeout ssebasti
@ 2022-01-25 12:17 ` ssebasti
2022-01-27 13:39 ` Namburu, Chandu-babu
2022-01-25 12:17 ` [PATCH v2 6/6] net/axgbe: alter the port speed bit range ssebasti
` (2 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: ssebasti @ 2022-01-25 12:17 UTC (permalink / raw)
To: dev
From: Selwin Sebastian <selwin.sebastian@amd.com>
Add support for a new port mode that is a backplane
connection without support for auto negotiation.
Signed-off-by: Selwin Sebastian <selwin.sebastian@amd.com>
---
drivers/net/axgbe/axgbe_phy_impl.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c
index eefb03e94e..b0e1c267b1 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -46,6 +46,7 @@ enum axgbe_port_mode {
AXGBE_PORT_MODE_10GBASE_T,
AXGBE_PORT_MODE_10GBASE_R,
AXGBE_PORT_MODE_SFP,
+ AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG,
AXGBE_PORT_MODE_MAX,
};
@@ -885,6 +886,7 @@ static enum axgbe_mode axgbe_phy_an73_redrv_outcome(struct axgbe_port *pdata)
if (ad_reg & 0x80) {
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
mode = AXGBE_MODE_KR;
break;
default:
@@ -894,6 +896,7 @@ static enum axgbe_mode axgbe_phy_an73_redrv_outcome(struct axgbe_port *pdata)
} else if (ad_reg & 0x20) {
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
mode = AXGBE_MODE_KX_1000;
break;
case AXGBE_PORT_MODE_1000BASE_X:
@@ -1052,6 +1055,7 @@ static unsigned int axgbe_phy_an_advertising(struct axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
advertising |= ADVERTISED_10000baseKR_Full;
break;
case AXGBE_PORT_MODE_BACKPLANE_2500:
@@ -1122,6 +1126,7 @@ static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
return AXGBE_AN_MODE_CL73;
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
case AXGBE_PORT_MODE_BACKPLANE_2500:
return AXGBE_AN_MODE_NONE;
case AXGBE_PORT_MODE_1000BASE_T:
@@ -1400,6 +1405,7 @@ static enum axgbe_mode axgbe_phy_switch_mode(struct axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
return axgbe_phy_switch_bp_mode(pdata);
case AXGBE_PORT_MODE_BACKPLANE_2500:
return axgbe_phy_switch_bp_2500_mode(pdata);
@@ -1495,6 +1501,7 @@ static enum axgbe_mode axgbe_phy_get_mode(struct axgbe_port *pdata,
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
return axgbe_phy_get_bp_mode(speed);
case AXGBE_PORT_MODE_BACKPLANE_2500:
return axgbe_phy_get_bp_2500_mode(speed);
@@ -1644,6 +1651,7 @@ static bool axgbe_phy_use_mode(struct axgbe_port *pdata, enum axgbe_mode mode)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
return axgbe_phy_use_bp_mode(pdata, mode);
case AXGBE_PORT_MODE_BACKPLANE_2500:
return axgbe_phy_use_bp_2500_mode(pdata, mode);
@@ -1806,6 +1814,7 @@ static bool axgbe_phy_port_mode_mismatch(struct axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
(phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000))
return false;
@@ -1858,6 +1867,7 @@ static bool axgbe_phy_conn_type_mismatch(struct axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
case AXGBE_PORT_MODE_BACKPLANE_2500:
if (phy_data->conn_type == AXGBE_CONN_TYPE_BACKPLANE)
return false;
@@ -2122,6 +2132,8 @@ static int axgbe_phy_init(struct axgbe_port *pdata)
/* Backplane support */
case AXGBE_PORT_MODE_BACKPLANE:
pdata->phy.supported |= SUPPORTED_Autoneg;
+ /* Fallthrough */
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
pdata->phy.supported |= SUPPORTED_Backplane;
if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
--
2.25.1
^ permalink raw reply [flat|nested] 16+ messages in thread* RE: [PATCH v2 5/6] net/axgbe: add support for new port mode
2022-01-25 12:17 ` [PATCH v2 5/6] net/axgbe: add support for new port mode ssebasti
@ 2022-01-27 13:39 ` Namburu, Chandu-babu
0 siblings, 0 replies; 16+ messages in thread
From: Namburu, Chandu-babu @ 2022-01-27 13:39 UTC (permalink / raw)
To: Sebastian, Selwin, dev
[Public]
Acked-by: Chandubabu Namburu <chandu@amd.com>
-----Original Message-----
From: ssebasti@amd.com <ssebasti@amd.com>
Sent: Tuesday, January 25, 2022 5:48 PM
To: dev@dpdk.org
Subject: [PATCH v2 5/6] net/axgbe: add support for new port mode
From: Selwin Sebastian <selwin.sebastian@amd.com>
Add support for a new port mode that is a backplane connection without support for auto negotiation.
Signed-off-by: Selwin Sebastian <selwin.sebastian@amd.com>
---
drivers/net/axgbe/axgbe_phy_impl.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c
index eefb03e94e..b0e1c267b1 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -46,6 +46,7 @@ enum axgbe_port_mode {
AXGBE_PORT_MODE_10GBASE_T,
AXGBE_PORT_MODE_10GBASE_R,
AXGBE_PORT_MODE_SFP,
+ AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG,
AXGBE_PORT_MODE_MAX,
};
@@ -885,6 +886,7 @@ static enum axgbe_mode axgbe_phy_an73_redrv_outcome(struct axgbe_port *pdata)
if (ad_reg & 0x80) {
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
mode = AXGBE_MODE_KR;
break;
default:
@@ -894,6 +896,7 @@ static enum axgbe_mode axgbe_phy_an73_redrv_outcome(struct axgbe_port *pdata)
} else if (ad_reg & 0x20) {
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
mode = AXGBE_MODE_KX_1000;
break;
case AXGBE_PORT_MODE_1000BASE_X:
@@ -1052,6 +1055,7 @@ static unsigned int axgbe_phy_an_advertising(struct axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
advertising |= ADVERTISED_10000baseKR_Full;
break;
case AXGBE_PORT_MODE_BACKPLANE_2500:
@@ -1122,6 +1126,7 @@ static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
return AXGBE_AN_MODE_CL73;
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
case AXGBE_PORT_MODE_BACKPLANE_2500:
return AXGBE_AN_MODE_NONE;
case AXGBE_PORT_MODE_1000BASE_T:
@@ -1400,6 +1405,7 @@ static enum axgbe_mode axgbe_phy_switch_mode(struct axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
return axgbe_phy_switch_bp_mode(pdata);
case AXGBE_PORT_MODE_BACKPLANE_2500:
return axgbe_phy_switch_bp_2500_mode(pdata);
@@ -1495,6 +1501,7 @@ static enum axgbe_mode axgbe_phy_get_mode(struct axgbe_port *pdata,
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
return axgbe_phy_get_bp_mode(speed);
case AXGBE_PORT_MODE_BACKPLANE_2500:
return axgbe_phy_get_bp_2500_mode(speed);
@@ -1644,6 +1651,7 @@ static bool axgbe_phy_use_mode(struct axgbe_port *pdata, enum axgbe_mode mode)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
return axgbe_phy_use_bp_mode(pdata, mode);
case AXGBE_PORT_MODE_BACKPLANE_2500:
return axgbe_phy_use_bp_2500_mode(pdata, mode); @@ -1806,6 +1814,7 @@ static bool axgbe_phy_port_mode_mismatch(struct axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
(phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000))
return false;
@@ -1858,6 +1867,7 @@ static bool axgbe_phy_conn_type_mismatch(struct axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
case AXGBE_PORT_MODE_BACKPLANE_2500:
if (phy_data->conn_type == AXGBE_CONN_TYPE_BACKPLANE)
return false;
@@ -2122,6 +2132,8 @@ static int axgbe_phy_init(struct axgbe_port *pdata)
/* Backplane support */
case AXGBE_PORT_MODE_BACKPLANE:
pdata->phy.supported |= SUPPORTED_Autoneg;
+ /* Fallthrough */
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
pdata->phy.supported |= SUPPORTED_Backplane;
if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
--
2.25.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 6/6] net/axgbe: alter the port speed bit range
2022-01-25 12:17 [PATCH v2 0/6] axgbe pmd updates ssebasti
` (4 preceding siblings ...)
2022-01-25 12:17 ` [PATCH v2 5/6] net/axgbe: add support for new port mode ssebasti
@ 2022-01-25 12:17 ` ssebasti
2022-01-25 16:21 ` Namburu, Chandu-babu
2022-01-25 12:47 ` [PATCH v2 0/6] axgbe pmd updates Ferruh Yigit
2022-01-25 12:50 ` Ferruh Yigit
7 siblings, 1 reply; 16+ messages in thread
From: ssebasti @ 2022-01-25 12:17 UTC (permalink / raw)
To: dev
From: Selwin Sebastian <selwin.sebastian@amd.com>
Newer generation Hardware uses the slightly different
port speed bit widths, so alter the existing port speed
bit range to extend support to the newer generation hardware
while maintaining the backward compatibility with older
generation hardware.
The previously reserved bits are now being used which
then requires the adjustment to the BIT values, e.g.:
Before:
PORT_PROPERTY_0[22:21] - Reserved
PORT_PROPERTY_0[26:23] - Supported Speeds
After:
PORT_PROPERTY_0[21] - Reserved
PORT_PROPERTY_0[26:22] - Supported Speeds
To make this backwards compatible, the existing BIT
definitions for the port speeds are incremented by one
to maintain the original position.
Signed-off-by: Selwin Sebastian <selwin.sebastian@amd.com>
---
drivers/net/axgbe/axgbe_common.h | 4 ++--
drivers/net/axgbe/axgbe_phy_impl.c | 8 ++++----
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index a5431dd998..5310ac54f5 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -1032,8 +1032,8 @@
#define XP_PROP_0_PORT_ID_WIDTH 8
#define XP_PROP_0_PORT_MODE_INDEX 8
#define XP_PROP_0_PORT_MODE_WIDTH 4
-#define XP_PROP_0_PORT_SPEEDS_INDEX 23
-#define XP_PROP_0_PORT_SPEEDS_WIDTH 4
+#define XP_PROP_0_PORT_SPEEDS_INDEX 22
+#define XP_PROP_0_PORT_SPEEDS_WIDTH 5
#define XP_PROP_1_MAX_RX_DMA_INDEX 24
#define XP_PROP_1_MAX_RX_DMA_WIDTH 5
#define XP_PROP_1_MAX_RX_QUEUES_INDEX 8
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c
index b0e1c267b1..d97fbbfddd 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -7,10 +7,10 @@
#include "axgbe_common.h"
#include "axgbe_phy.h"
-#define AXGBE_PHY_PORT_SPEED_100 BIT(0)
-#define AXGBE_PHY_PORT_SPEED_1000 BIT(1)
-#define AXGBE_PHY_PORT_SPEED_2500 BIT(2)
-#define AXGBE_PHY_PORT_SPEED_10000 BIT(3)
+#define AXGBE_PHY_PORT_SPEED_100 BIT(1)
+#define AXGBE_PHY_PORT_SPEED_1000 BIT(2)
+#define AXGBE_PHY_PORT_SPEED_2500 BIT(3)
+#define AXGBE_PHY_PORT_SPEED_10000 BIT(4)
#define AXGBE_MUTEX_RELEASE 0x80000000
--
2.25.1
^ permalink raw reply [flat|nested] 16+ messages in thread* RE: [PATCH v2 6/6] net/axgbe: alter the port speed bit range
2022-01-25 12:17 ` [PATCH v2 6/6] net/axgbe: alter the port speed bit range ssebasti
@ 2022-01-25 16:21 ` Namburu, Chandu-babu
2022-01-27 14:31 ` Ferruh Yigit
0 siblings, 1 reply; 16+ messages in thread
From: Namburu, Chandu-babu @ 2022-01-25 16:21 UTC (permalink / raw)
To: Sebastian, Selwin, dev, Ferruh Yigit
[Public]
For series,
Acked-by: Chandubabu Namburu <chandu@amd.com>
-----Original Message-----
From: ssebasti@amd.com <ssebasti@amd.com>
Sent: Tuesday, January 25, 2022 5:48 PM
To: dev@dpdk.org
Subject: [PATCH v2 6/6] net/axgbe: alter the port speed bit range
From: Selwin Sebastian <selwin.sebastian@amd.com>
Newer generation Hardware uses the slightly different port speed bit widths, so alter the existing port speed bit range to extend support to the newer generation hardware while maintaining the backward compatibility with older generation hardware.
The previously reserved bits are now being used which then requires the adjustment to the BIT values, e.g.:
Before:
PORT_PROPERTY_0[22:21] - Reserved
PORT_PROPERTY_0[26:23] - Supported Speeds
After:
PORT_PROPERTY_0[21] - Reserved
PORT_PROPERTY_0[26:22] - Supported Speeds
To make this backwards compatible, the existing BIT definitions for the port speeds are incremented by one to maintain the original position.
Signed-off-by: Selwin Sebastian <selwin.sebastian@amd.com>
---
drivers/net/axgbe/axgbe_common.h | 4 ++--
drivers/net/axgbe/axgbe_phy_impl.c | 8 ++++----
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index a5431dd998..5310ac54f5 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -1032,8 +1032,8 @@
#define XP_PROP_0_PORT_ID_WIDTH 8
#define XP_PROP_0_PORT_MODE_INDEX 8
#define XP_PROP_0_PORT_MODE_WIDTH 4
-#define XP_PROP_0_PORT_SPEEDS_INDEX 23
-#define XP_PROP_0_PORT_SPEEDS_WIDTH 4
+#define XP_PROP_0_PORT_SPEEDS_INDEX 22
+#define XP_PROP_0_PORT_SPEEDS_WIDTH 5
#define XP_PROP_1_MAX_RX_DMA_INDEX 24
#define XP_PROP_1_MAX_RX_DMA_WIDTH 5
#define XP_PROP_1_MAX_RX_QUEUES_INDEX 8
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c
index b0e1c267b1..d97fbbfddd 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -7,10 +7,10 @@
#include "axgbe_common.h"
#include "axgbe_phy.h"
-#define AXGBE_PHY_PORT_SPEED_100 BIT(0)
-#define AXGBE_PHY_PORT_SPEED_1000 BIT(1)
-#define AXGBE_PHY_PORT_SPEED_2500 BIT(2)
-#define AXGBE_PHY_PORT_SPEED_10000 BIT(3)
+#define AXGBE_PHY_PORT_SPEED_100 BIT(1)
+#define AXGBE_PHY_PORT_SPEED_1000 BIT(2)
+#define AXGBE_PHY_PORT_SPEED_2500 BIT(3)
+#define AXGBE_PHY_PORT_SPEED_10000 BIT(4)
#define AXGBE_MUTEX_RELEASE 0x80000000
--
2.25.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 6/6] net/axgbe: alter the port speed bit range
2022-01-25 16:21 ` Namburu, Chandu-babu
@ 2022-01-27 14:31 ` Ferruh Yigit
0 siblings, 0 replies; 16+ messages in thread
From: Ferruh Yigit @ 2022-01-27 14:31 UTC (permalink / raw)
To: Namburu, Chandu-babu, Sebastian, Selwin, dev
On 1/25/2022 4:21 PM, Namburu, Chandu-babu wrote:
> [Public]
Moving ack down, please don't top post.
>
> -----Original Message-----
> From: ssebasti@amd.com <ssebasti@amd.com>
> Sent: Tuesday, January 25, 2022 5:48 PM
> To: dev@dpdk.org
> Subject: [PATCH v2 6/6] net/axgbe: alter the port speed bit range
>
> From: Selwin Sebastian <selwin.sebastian@amd.com>
>
> Newer generation Hardware uses the slightly different port speed bit widths, so alter the existing port speed bit range to extend support to the newer generation hardware while maintaining the backward compatibility with older generation hardware.
>
> The previously reserved bits are now being used which then requires the adjustment to the BIT values, e.g.:
>
> Before:
> PORT_PROPERTY_0[22:21] - Reserved
> PORT_PROPERTY_0[26:23] - Supported Speeds
>
> After:
> PORT_PROPERTY_0[21] - Reserved
> PORT_PROPERTY_0[26:22] - Supported Speeds
>
> To make this backwards compatible, the existing BIT definitions for the port speeds are incremented by one to maintain the original position.
>
> Signed-off-by: Selwin Sebastian <selwin.sebastian@amd.com>
>
> For series,
> Acked-by: Chandubabu Namburu <chandu@amd.com>
>
Series applied to dpdk-next-net/main, thanks.
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 0/6] axgbe pmd updates
2022-01-25 12:17 [PATCH v2 0/6] axgbe pmd updates ssebasti
` (5 preceding siblings ...)
2022-01-25 12:17 ` [PATCH v2 6/6] net/axgbe: alter the port speed bit range ssebasti
@ 2022-01-25 12:47 ` Ferruh Yigit
2022-01-25 12:50 ` Ferruh Yigit
7 siblings, 0 replies; 16+ messages in thread
From: Ferruh Yigit @ 2022-01-25 12:47 UTC (permalink / raw)
To: ssebasti, dev; +Cc: Chandubabu Namburu
On 1/25/2022 12:17 PM, ssebasti@amd.com wrote:
> From: Selwin Sebastian <selwin.sebastian@amd.com>
>
> some updates to axgbe pmd driver
>
> Selwin Sebastian (6):
> net/axgbe: always attempt link training in KR mode
> net/axgbe: toggle PLL settings during rate change
> net/axgbe: simplify mailbox interface rate change code
> net/axgbe: reset PHY Rx when mailbox command timeout
> net/axgbe: add support for new port mode
> net/axgbe: alter the port speed bit range
>
Hi Selwin,
Thanks for new version. I will wait axgbe maintainer's ack to proceed,
that is why better to cc him in the patches.
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v2 0/6] axgbe pmd updates
2022-01-25 12:17 [PATCH v2 0/6] axgbe pmd updates ssebasti
` (6 preceding siblings ...)
2022-01-25 12:47 ` [PATCH v2 0/6] axgbe pmd updates Ferruh Yigit
@ 2022-01-25 12:50 ` Ferruh Yigit
7 siblings, 0 replies; 16+ messages in thread
From: Ferruh Yigit @ 2022-01-25 12:50 UTC (permalink / raw)
To: ssebasti, dev; +Cc: Chandubabu Namburu
On 1/25/2022 12:17 PM, ssebasti@amd.com wrote:
> From: Selwin Sebastian <selwin.sebastian@amd.com>
>
> some updates to axgbe pmd driver
>
> Selwin Sebastian (6):
> net/axgbe: always attempt link training in KR mode
> net/axgbe: toggle PLL settings during rate change
> net/axgbe: simplify mailbox interface rate change code
> net/axgbe: reset PHY Rx when mailbox command timeout
> net/axgbe: add support for new port mode
> net/axgbe: alter the port speed bit range
>
Hi Selwin,
Thanks for new version. I will wait axgbe maintainer's ack to proceed,
that is why better to cc him in the patches.
^ permalink raw reply [flat|nested] 16+ messages in thread