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d="scan'208";a="474522042" Received: from fmsmsx606.amr.corp.intel.com ([10.18.126.86]) by orsmga004.jf.intel.com with ESMTP; 12 Nov 2020 19:35:07 -0800 Received: from shsmsx603.ccr.corp.intel.com (10.109.6.143) by fmsmsx606.amr.corp.intel.com (10.18.126.86) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Thu, 12 Nov 2020 19:35:06 -0800 Received: from shsmsx604.ccr.corp.intel.com (10.109.6.214) by SHSMSX603.ccr.corp.intel.com (10.109.6.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Fri, 13 Nov 2020 11:35:04 +0800 Received: from shsmsx604.ccr.corp.intel.com ([10.109.6.214]) by SHSMSX604.ccr.corp.intel.com ([10.109.6.214]) with mapi id 15.01.1713.004; Fri, 13 Nov 2020 11:35:04 +0800 From: "Sun, QinX" To: "Zhang, AlvinX" , "Zhang, Qi Z" , "Rong, Leyi" , "Lu, Wenzhuo" CC: "dev@dpdk.org" , "Zhang, AlvinX" Thread-Topic: [dpdk-dev] [PATCH v3] net/ice: support flow mark ID in avx512 path Thread-Index: AQHWuWf4BfgGyoW5G0iibxH0RF5LaqnFaByg Date: Fri, 13 Nov 2020 03:35:04 +0000 Message-ID: References: <20201113022506.23076-1-alvinx.zhang@intel.com> <20201113025118.25300-1-alvinx.zhang@intel.com> In-Reply-To: <20201113025118.25300-1-alvinx.zhang@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v3] net/ice: support flow mark ID in avx512 path X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Tested-by: Sun, QinX =A0 Regards, Sun Qin > -----Original Message----- > From: dev On Behalf Of Zhang,Alvin > Sent: Friday, November 13, 2020 10:51 AM > To: Zhang, Qi Z ; Rong, Leyi ; > Lu, Wenzhuo > Cc: dev@dpdk.org; Zhang, AlvinX > Subject: [dpdk-dev] [PATCH v3] net/ice: support flow mark ID in avx512 pa= th >=20 > From: Alvin Zhang >=20 > Support flow director mark ID parsing from flexible Rx descriptor in avx5= 12 > path. >=20 > Signed-off-by: Alvin Zhang >=20 > --- >=20 > v2: Update codes according to comments. > v3: Rename the function ice_flex_rxd_to_fdir_flags_vec_avx with > ice_flex_rxd_to_fdir_flags_vec_avx512. > --- > drivers/net/ice/ice_rxtx_vec_avx512.c | 66 > +++++++++++++++++++++++++++++++++-- > 1 file changed, 64 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/net/ice/ice_rxtx_vec_avx512.c > b/drivers/net/ice/ice_rxtx_vec_avx512.c > index af6b324..df5d2be 100644 > --- a/drivers/net/ice/ice_rxtx_vec_avx512.c > +++ b/drivers/net/ice/ice_rxtx_vec_avx512.c > @@ -128,6 +128,25 @@ > ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id); } >=20 > +static inline __m256i > +ice_flex_rxd_to_fdir_flags_vec_avx512(const __m256i fdir_id0_7) { > +#define FDID_MIS_MAGIC 0xFFFFFFFF > + RTE_BUILD_BUG_ON(PKT_RX_FDIR !=3D (1 << 2)); > + RTE_BUILD_BUG_ON(PKT_RX_FDIR_ID !=3D (1 << 13)); > + const __m256i pkt_fdir_bit =3D _mm256_set1_epi32(PKT_RX_FDIR | > + PKT_RX_FDIR_ID); > + /* desc->flow_id field =3D=3D 0xFFFFFFFF means fdir mismatch */ > + const __m256i fdir_mis_mask =3D > _mm256_set1_epi32(FDID_MIS_MAGIC); > + __m256i fdir_mask =3D _mm256_cmpeq_epi32(fdir_id0_7, > + fdir_mis_mask); > + /* this XOR op results to bit-reverse the fdir_mask */ > + fdir_mask =3D _mm256_xor_si256(fdir_mask, fdir_mis_mask); > + const __m256i fdir_flags =3D _mm256_and_si256(fdir_mask, > pkt_fdir_bit); > + > + return fdir_flags; > +} > + > static inline uint16_t > _ice_recv_raw_pkts_vec_avx512(struct ice_rx_queue *rxq, > struct rte_mbuf **rx_pkts, > @@ -441,8 +460,51 @@ > rss_vlan_flag_bits); >=20 > /* merge flags */ > - const __m256i mbuf_flags =3D _mm256_or_si256(l3_l4_flags, > - rss_vlan_flags); > + __m256i mbuf_flags =3D _mm256_or_si256(l3_l4_flags, > + rss_vlan_flags); > + > + if (rxq->fdir_enabled) { > + const __m256i fdir_id4_7 =3D > + _mm256_unpackhi_epi32(raw_desc6_7, > raw_desc4_5); > + > + const __m256i fdir_id0_3 =3D > + _mm256_unpackhi_epi32(raw_desc2_3, > raw_desc0_1); > + > + const __m256i fdir_id0_7 =3D > + _mm256_unpackhi_epi64(fdir_id4_7, > fdir_id0_3); > + > + const __m256i fdir_flags =3D > + ice_flex_rxd_to_fdir_flags_vec_avx512 > + (fdir_id0_7); > + > + /* merge with fdir_flags */ > + mbuf_flags =3D _mm256_or_si256(mbuf_flags, > fdir_flags); > + > + /* write to mbuf: have to use scalar store here */ > + rx_pkts[i + 0]->hash.fdir.hi =3D > + _mm256_extract_epi32(fdir_id0_7, 3); > + > + rx_pkts[i + 1]->hash.fdir.hi =3D > + _mm256_extract_epi32(fdir_id0_7, 7); > + > + rx_pkts[i + 2]->hash.fdir.hi =3D > + _mm256_extract_epi32(fdir_id0_7, 2); > + > + rx_pkts[i + 3]->hash.fdir.hi =3D > + _mm256_extract_epi32(fdir_id0_7, 6); > + > + rx_pkts[i + 4]->hash.fdir.hi =3D > + _mm256_extract_epi32(fdir_id0_7, 1); > + > + rx_pkts[i + 5]->hash.fdir.hi =3D > + _mm256_extract_epi32(fdir_id0_7, 5); > + > + rx_pkts[i + 6]->hash.fdir.hi =3D > + _mm256_extract_epi32(fdir_id0_7, 0); > + > + rx_pkts[i + 7]->hash.fdir.hi =3D > + _mm256_extract_epi32(fdir_id0_7, 4); > + } /* if() on fdir_enabled */ >=20 > #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC > /** > -- > 1.8.3.1