From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0701045500; Wed, 26 Jun 2024 13:55:02 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5CBA942F6B; Wed, 26 Jun 2024 13:54:58 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by mails.dpdk.org (Postfix) with ESMTP id 2B40C42EDA for ; Wed, 26 Jun 2024 13:43:02 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719402182; x=1750938182; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=l7jj3eC2dTN/yMWZpj0TRPXp1GqRGagjogv3dx4eBQc=; b=dJEZtHi/v7jqGFCGEMM6QcAtT/8pk/z1rmj+UKmEbyQ8mGIetC5fPhen tAsNZOnZaf6NchmTtk+iy/8PkM8zC7HxLpOTAX6jalPKpJCQWeMHjxxq8 q83apNQ0FoPCggWG89vrAGM7jRPoqG6qbpjt8WhBzt7nnjZDxpo+wKU89 Qx3rTgc2rkRferxmq54XRCeJ+/sis1iJfAiA4WdgdqC912raUmrGui2lq cjJSUWY8HIJp6gEBlxBIJhSJYo1OWp4RjshPFHI6IrPKnC/w4Lp5IIUAh 4TClBhdncYSqvHyqLfWrv4LkJxcIHUwtfrfW/032FZVSMYFSg6HW42uyV w==; X-CSE-ConnectionGUID: 7+TG+rw+Te+h1Ri3L5Qu7g== X-CSE-MsgGUID: Qiqzr35eR2CXah3IRaZxQw== X-IronPort-AV: E=McAfee;i="6700,10204,11114"; a="38979267" X-IronPort-AV: E=Sophos;i="6.08,266,1712646000"; d="scan'208";a="38979267" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jun 2024 04:43:01 -0700 X-CSE-ConnectionGUID: w6HRje/+TP2AtXPympImDw== X-CSE-MsgGUID: kARnMshbQh2/jJf09HUI5A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,266,1712646000"; d="scan'208";a="43873382" Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167]) by orviesa010.jf.intel.com with ESMTP; 26 Jun 2024 04:43:01 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Karol Kolacinski , ian.stokes@intel.com, bruce.richardson@intel.com Subject: [PATCH v4 001/103] net/ice/base: add LL Tx timestamp interrupt read Date: Wed, 26 Jun 2024 12:40:49 +0100 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Karol Kolacinski E810 products can support low latency Tx timestamp register read using the SW interrupt from the FW. Add a check for the device capability and use the new method if supported. Signed-off-by: Karol Kolacinski Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_common.c | 3 +++ drivers/net/ice/base/ice_ptp_hw.h | 1 + drivers/net/ice/base/ice_type.h | 2 ++ 3 files changed, 6 insertions(+) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index ef6696cddf..b68afdaa14 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -2781,6 +2781,7 @@ ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0); + info->ts_ll_int_read = ((number & ICE_TS_LL_TX_TS_INT_READ_M) != 0); info->tmr_own_map = phys_id; @@ -2800,6 +2801,8 @@ ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, info->tmr1_ena); ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n", info->ts_ll_read); + ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_int_read = %u\n", + info->ts_ll_int_read); ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", info->tmr_own_map); } diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index 35ab9bb3e8..441ad0b77d 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -489,6 +489,7 @@ int ice_ptp_init_phy_cfg(struct ice_hw *hw); /* Tx timestamp low latency read definitions */ #define TS_LL_READ_RETRIES 200 +#define TS_LL_READ_TS_INTR BIT(30) #define TS_LL_READ_TS BIT(31) #define TS_LL_READ_TS_IDX_S 24 #define TS_LL_READ_TS_IDX_M MAKEMASK(0x3F, 0) diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index 239b1a018e..7a1471e474 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -778,6 +778,7 @@ struct ice_ts_func_info { #define ICE_TS_TMR0_ENA_M BIT(25) #define ICE_TS_TMR1_ENA_M BIT(26) #define ICE_TS_LL_TX_TS_READ_M BIT(28) +#define ICE_TS_LL_TX_TS_INT_READ_M BIT(29) struct ice_ts_dev_info { /* Device specific info */ @@ -790,6 +791,7 @@ struct ice_ts_dev_info { u8 tmr0_ena : 1; u8 tmr1_ena : 1; u8 ts_ll_read : 1; + u8 ts_ll_int_read : 1; }; #define ICE_NAC_TOPO_PRIMARY_M BIT(0) -- 2.43.0