From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 90202A04B5; Fri, 6 Nov 2020 17:45:31 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 68651F90; Fri, 6 Nov 2020 17:45:30 +0100 (CET) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 6CAF12AB for ; Fri, 6 Nov 2020 17:45:29 +0100 (CET) IronPort-SDR: HQKLO2W2BWxe9sqE05VONdgUP+ssz+U1NrLGSSxQGE+sdhxSEGa9FMHmkPoxrDnbA7seN2/j+c 7GXIkTDBpSHA== X-IronPort-AV: E=McAfee;i="6000,8403,9797"; a="168785964" X-IronPort-AV: E=Sophos;i="5.77,457,1596524400"; d="scan'208";a="168785964" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2020 08:45:21 -0800 IronPort-SDR: HvahSjH+i/2JWdxfZ6lRh7NemDAyb50n1Fs2MoJ0zEmURusIqxIu+qO3U3KeshACq+SkkiHhEi 8L++yB8wl4pQ== X-IronPort-AV: E=Sophos;i="5.77,457,1596524400"; d="scan'208";a="539904517" Received: from fyigit-mobl1.ger.corp.intel.com (HELO [10.213.228.45]) ([10.213.228.45]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2020 08:45:20 -0800 To: Lijun Ou Cc: dev@dpdk.org, linuxarm@huawei.com References: <1604586194-29523-1-git-send-email-oulijun@huawei.com> <1604634716-43484-1-git-send-email-oulijun@huawei.com> <1604634716-43484-5-git-send-email-oulijun@huawei.com> From: Ferruh Yigit Message-ID: Date: Fri, 6 Nov 2020 16:45:18 +0000 MIME-Version: 1.0 In-Reply-To: <1604634716-43484-5-git-send-email-oulijun@huawei.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Subject: Re: [dpdk-dev] [PATCH v2 4/5] net/hns3: check PCI config space writes X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 11/6/2020 3:51 AM, Lijun Ou wrote: > Here adds a check for the return value when calling > rte_pci_write_config. > > Coverity issue: 363714 > Fixes: cea37e513329 ("net/hns3: fix FLR reset") > Cc: stable@dpdk.org > > Signed-off-by: Lijun Ou > --- > V1->V2: > - rte_pci_wirte_config -> rte_pci_write_config > --- > drivers/net/hns3/hns3_ethdev_vf.c | 10 +++++++--- > 1 file changed, 7 insertions(+), 3 deletions(-) > > diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c > index 2e9bfda..2f6d91b 100644 > --- a/drivers/net/hns3/hns3_ethdev_vf.c > +++ b/drivers/net/hns3/hns3_ethdev_vf.c > @@ -139,7 +139,7 @@ hns3vf_enable_msix(const struct rte_pci_device *device, bool op) > ret = rte_pci_read_config(device, &control, sizeof(control), > (pos + PCI_MSIX_FLAGS)); > if (ret < 0) { > - PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", > + PMD_INIT_LOG(ERR, "failed to read PCI offset 0x%x", Can you please drop this unrelated change from the patch? > (pos + PCI_MSIX_FLAGS)); > return -ENXIO; > } > @@ -148,8 +148,12 @@ hns3vf_enable_msix(const struct rte_pci_device *device, bool op) > control |= PCI_MSIX_FLAGS_ENABLE; > else > control &= ~PCI_MSIX_FLAGS_ENABLE; > - rte_pci_write_config(device, &control, sizeof(control), > - (pos + PCI_MSIX_FLAGS)); > + ret = rte_pci_write_config(device, &control, sizeof(control), > + (pos + PCI_MSIX_FLAGS)); > + if (ret < 0) { > + PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x", > + (pos + PCI_MSIX_FLAGS)); > + } > return 0; > } > return -ENXIO; >