Re: [dpdk-dev] [PATCH V2 1/4] config/arm: add Hisilicon kunpeng920 implementer

[oulijun <oulijun@huawei.com>]

在 2021/3/25 15:45, Ruifeng Wang 写道:
>> -----Original Message-----
>> From: oulijun <oulijun@huawei.com>
>> Sent: Thursday, March 25, 2021 3:22 PM
>> To: Ruifeng Wang <Ruifeng.Wang@arm.com>; thomas@monjalon.net;
>> ferruh.yigit@intel.com
>> Cc: dev@dpdk.org; linuxarm@openeuler.org; nd <nd@arm.com>
>> Subject: Re: [dpdk-dev] [PATCH V2 1/4] config/arm: add Hisilicon
>> kunpeng920 implementer
>>
>>
>>
>> 在 2021/3/23 23:40, Ruifeng Wang 写道:
>>>> -----Original Message-----
>>>> From: oulijun <oulijun@huawei.com>
>>>> Sent: Tuesday, March 23, 2021 9:52 PM
>>>> To: Ruifeng Wang <Ruifeng.Wang@arm.com>; thomas@monjalon.net;
>>>> ferruh.yigit@intel.com
>>>> Cc: dev@dpdk.org; linuxarm@openeuler.org; nd <nd@arm.com>
>>>> Subject: Re: [dpdk-dev] [PATCH V2 1/4] config/arm: add Hisilicon
>>>> kunpeng920 implementer
>>>>
>>>>
>>>>
>>>>      2021/3/23 16:07, Ruifeng Wang д  :
>>>>>> -----Original Message-----
>>>>>> From: dev <dev-bounces@dpdk.org> On Behalf Of Lijun Ou
>>>>>> Sent: Wednesday, March 10, 2021 9:36 AM
>>>>>> To: thomas@monjalon.net; ferruh.yigit@intel.com
>>>>>> Cc: dev@dpdk.org; linuxarm@openeuler.org
>>>>>> Subject: [dpdk-dev] [PATCH V2 1/4] config/arm: add Hisilicon
>>>>>> kunpeng920 implementer
>>>>>>
>>>>>> Here addes Kunpeng920 config back which was deleted.
> 
> There was no Kunpeng920 specific config before change 91c730fd4e09.
> It would fall back to generic build because the behavior was to do generic build for unknown implementor / part number.
> 
What should we do with this patch? This is because we cannot compile on 
the Kunpeng 920 server without adding generic build.
>>>>>>
>>>>>> Fixes: 91c730fd4e09 ("config/arm: remove unused or superfluous
>>>>>> variables")
>>>>>>
>>>>>> Signed-off-by: Chengchang Tang <tangchengchang@huawei.com>
>>>>>> Signed-off-by: Lijun Ou <oulijun@huawei.com>
>>>>>> ---
>>>>>> V1->V2:
>>>>>> - rewrite patch title.
>>>>>> - split the patch into two.
>>>>>> ---
>>>>>>     config/arm/meson.build | 20 ++++++++++++++++++++
>>>>>>     1 file changed, 20 insertions(+)
>>>>>>
>>>>>> diff --git a/config/arm/meson.build b/config/arm/meson.build index
>>>>>> 00bc461..3826900 100644
>>>>>> --- a/config/arm/meson.build
>>>>>> +++ b/config/arm/meson.build
>>>>>> @@ -133,6 +133,25 @@ implementer_cavium = {
>>>>>>     	}
>>>>>>     }
>>>>>>
>>>>>> +implementer_hisilicon = {
>>>>>> +	'description': 'Hisilicon',
>>>>>> +	'flags': [
>>>>>> +		['RTE_USE_C11_MEM_MODEL', true],
>>>>>> +		['RTE_CACHE_LINE_SIZE', 128],
>>>>>
>>>>> Just want to double check.
>>>>> One Kunpeng920 box I can access have cache line size 64B.
>>>>>
>>>> I have a question, which level does RTE_CACHE_LINE_SIZE refer to? For
>>>> kunpeng920, L1/L2 cache size is 64B  L3 is 128B
>>>
>>> Got it.
>>> I think RTE_CACHE_LINE_SIZE is not defined for a certain level of cache.
>>> Data can be prefetched into any level of cache by using different APIs.
>>>
>> So our current configuration should be fine.
> 
> Agree.
> 
>>>>> Thanks.
>>>>>> +		['RTE_MAX_NUMA_NODES', 4]
>>>>>> +	],
>>>>>> +	'part_number_config': {
>>>>>> +		'0xd01': {
>>>>>> +			'machine_args': ['-march=armv8.2-a+crypto',
>>>>>> +					 '-mtune=tsv110'],
>>>>>> +			'flag': [['RTE_MACHINE', '"kunpeng920"'],
>>>>>> +				 ['RTE_MAX_LCORE', 128],
>>>>>> +				 ['RTE_ARM_FEATURE_ATOMICS', true]
>>>>>> +			]
>>>>>> +		}
>>>>>> +	}
>>>>>> +}
>>>>>> +
>>>>>>     implementer_ampere = {
>>>>>>     	'description': 'Ampere Computing',
>>>>>>     	'flags': [
>>>>>> @@ -190,6 +209,7 @@ implementers = {
>>>>>>     	'generic': implementer_generic,
>>>>>>     	'0x41': implementer_arm,
>>>>>>     	'0x43': implementer_cavium,
>>>>>> +	'0x48': implementer_hisilicon,
>>>>>>     	'0x50': implementer_ampere,
>>>>>>     	'0x51': implementer_qualcomm,
>>>>>>     	'0x56': implementer_marvell,
>>>>>> --
>>>>>> 2.7.4
>>>>>
>>>>> .
>>>>>