From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3AAF045501; Wed, 26 Jun 2024 14:06:25 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 92C8D43458; Wed, 26 Jun 2024 13:57:29 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by mails.dpdk.org (Postfix) with ESMTP id 8CEB542E95 for ; Wed, 26 Jun 2024 13:45:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719402342; x=1750938342; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YkmEG+C04SBBEy4HiY0r1AP7YoZXB+LhLUymPA3Qeuo=; b=n9dLAgJ/bFoVQ3N5iXTd8nt260bTYWcMydbQDpAscvj2h3BdtC5Jbu0w Mqn+hqmJ1ZFh66NxDMaLnxCWFX0QVUG/JOtzTeZJzYxITFbN/K7RKIWSV mmcrwOZIe1cp1kHdu79JsUnK2jLW6WOYm00wELqGCR/o4DkYqyqo+mgdC O/uyWEPD9iDYRwDs7RIhE6tlI3aIOBoJBRCxo4cn5yv+mzIxQ53ECqbaD aqhRanNbgSYeloDsDwa7jQj2n71bwXTejatxn4WmxykiHk/NAxyAZGVrG OWJAxHFsb8/IjxwYR8cpluqTrUcP8x6Fx5yF8IXV23RGzDTTOkI1j61Jd A==; X-CSE-ConnectionGUID: sC4KOIjnSDiJHOPnG0pZhw== X-CSE-MsgGUID: O0Q0o+igT8WQoHhTeyBa6A== X-IronPort-AV: E=McAfee;i="6700,10204,11114"; a="38979605" X-IronPort-AV: E=Sophos;i="6.08,266,1712646000"; d="scan'208";a="38979605" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jun 2024 04:45:42 -0700 X-CSE-ConnectionGUID: gmKT5j5eQBuBgCvA/PBT3Q== X-CSE-MsgGUID: C5o+w6JrRlOGOKp6PUpfaA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,266,1712646000"; d="scan'208";a="43874613" Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167]) by orviesa010.jf.intel.com with ESMTP; 26 Jun 2024 04:45:41 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Jacob Keller , ian.stokes@intel.com, bruce.richardson@intel.com Subject: [PATCH v4 095/103] net/ice/base: rename SMA register macros Date: Wed, 26 Jun 2024 12:42:23 +0100 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Jacob Keller The macros used to define the bits for controlling the SMA are different to what was submitted to Linux. Correct the names to match. Signed-off-by: Jacob Keller Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_ptp_hw.c | 8 ++++---- drivers/net/ice/base/ice_ptp_hw.h | 26 ++++++++++++++++++-------- 2 files changed, 22 insertions(+), 12 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index cb689c1a25..50ffa7b796 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -5351,10 +5351,10 @@ int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data) *data = 0; - for (i = ICE_E810T_SMA_MIN_BIT; i <= ICE_E810T_SMA_MAX_BIT; i++) { + for (i = ICE_SMA_MIN_BIT_E810T; i <= ICE_SMA_MAX_BIT_E810T; i++) { bool pin; - status = ice_aq_get_gpio(hw, handle, i + ICE_E810T_P1_OFFSET, + status = ice_aq_get_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET, &pin, NULL); if (status) break; @@ -5381,11 +5381,11 @@ int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data) if (status) return status; - for (i = ICE_E810T_SMA_MIN_BIT; i <= ICE_E810T_SMA_MAX_BIT; i++) { + for (i = ICE_SMA_MIN_BIT_E810T; i <= ICE_SMA_MAX_BIT_E810T; i++) { bool pin; pin = !(data & (1 << i)); - status = ice_aq_set_gpio(hw, handle, i + ICE_E810T_P1_OFFSET, + status = ice_aq_set_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET, pin, NULL); if (status) break; diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index d40336072b..c4a5c030f1 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -661,6 +661,21 @@ ice_get_base_incval(struct ice_hw *hw, enum ice_src_tmr_mode src_tmr_mode) #define E830_HIGH_TX_MEMORY_BANK(slot, port) \ (E830_PRTTSYN_TXTIME_H(slot) + 0x8 * (port)) +/* E810T SMA controller pin control */ +#define ICE_SMA1_DIR_EN_E810T BIT(4) +#define ICE_SMA1_TX_EN_E810T BIT(5) +#define ICE_SMA2_UFL2_RX_DIS_E810T BIT(3) +#define ICE_SMA2_DIR_EN_E810T BIT(6) +#define ICE_SMA2_TX_EN_E810T BIT(7) + +#define ICE_SMA1_MASK_E810T (ICE_SMA1_DIR_EN_E810T | \ + ICE_SMA1_TX_EN_E810T) +#define ICE_SMA2_MASK_E810T (ICE_SMA2_UFL2_RX_DIS_E810T | \ + ICE_SMA2_DIR_EN_E810T | \ + ICE_SMA2_TX_EN_E810T) +#define ICE_ALL_SMA_MASK_E810T (ICE_SMA1_MASK_E810T | \ + ICE_SMA2_MASK_E810T) + /* E810T PCA9575 IO controller registers */ #define ICE_PCA9575_P0_IN 0x0 #define ICE_PCA9575_P1_IN 0x1 @@ -671,15 +686,10 @@ ice_get_base_incval(struct ice_hw *hw, enum ice_src_tmr_mode src_tmr_mode) /* E810T PCA9575 IO controller pin control */ #define ICE_E810T_P0_GNSS_PRSNT_N BIT(4) -#define ICE_E810T_P1_SMA1_DIR_EN BIT(4) -#define ICE_E810T_P1_SMA1_TX_EN BIT(5) -#define ICE_E810T_P1_SMA2_UFL2_RX_DIS BIT(3) -#define ICE_E810T_P1_SMA2_DIR_EN BIT(6) -#define ICE_E810T_P1_SMA2_TX_EN BIT(7) -#define ICE_E810T_SMA_MIN_BIT 3 -#define ICE_E810T_SMA_MAX_BIT 7 -#define ICE_E810T_P1_OFFSET 8 +#define ICE_SMA_MIN_BIT_E810T 3 +#define ICE_SMA_MAX_BIT_E810T 7 +#define ICE_PCA9575_P1_OFFSET 8 /* 56G PHY quad register base addresses */ #define ICE_PHY0_BASE 0x092000 #define ICE_PHY1_BASE 0x126000 -- 2.43.0