* [PATCH v6 0/7] Introduce support for LoongArch architecture
@ 2022-08-27 8:59 Min Zhou
2022-08-27 8:59 ` [PATCH v6 1/7] eal/loongarch: support " Min Zhou
` (9 more replies)
0 siblings, 10 replies; 12+ messages in thread
From: Min Zhou @ 2022-08-27 8:59 UTC (permalink / raw)
To: david.marchand, thomas, bruce.richardson, anatoly.burakov,
qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev,
zhoumin
Cc: dev, maobibo
Dear team,
The following patch set is intended to support DPDK running on LoongArch
architecture.
LoongArch is the general processor architecture of Loongson Corporation
and is a new RISC ISA, which is a bit like MIPS or RISC-V.
The online documents of LoongArch architecture are here:
https://loongson.github.io/LoongArch-Documentation/README-EN.html
The latest build tools for LoongArch (binary) can be downloaded from:
https://github.com/loongson/build-tools
v6:
- place some blocks for LoongArch in a pseudo alphabetical order
- remove some macros not used
- update release notes in the correct format
- remove some headers for LoongArch, including msclock, pflock and
ticketlock, which are now non-arch specific
- rename some helpers to make them more readable
- remove some copied comments
- force-set RTE_FORCE_INTRINSICS in config and remove non-arch
specific implementations
- fix format errors in meson file reported by check-meson.py
- rebase the patchset on the main repository
v5:
- merge all patches for supporting LoongArch EAL into one patch
- add LoongArch cross compilation document and update some documents
related to architecture
- remove vector stubs added for LoongArch in net/i40e and net/ixgbe
- add LOONGARCH64 cross compilation job in github ci
v4:
- rebase the patchset on the main repository of version 22.07.0
v3:
- add URL for cross compile tool chain
- remove rte_lpm_lsx.h which was a dummy vector implementation
because there is already a scalar implementation, thanks to
Michal Mazurek
- modify the name of compiler for cross compiling
- remove useless variable in meson.build
v2:
- use standard atomics of toolchain to implement
atomic operations
- implement spinlock based on standard atomics
*** BLURB HERE ***
Min Zhou (7):
eal/loongarch: support LoongArch architecture
net/ixgbe: add vector stubs for LoongArch
net/memif: set memfd syscall ID on LoongArch
net/tap: set BPF syscall ID for LoongArch
examples/l3fwd: enable LoongArch operation
test/cpuflags: add test for LoongArch cpu flag
ci: add LOONGARCH64 cross compilation job
.ci/linux-build.sh | 10 ++
.github/workflows/build.yml | 10 +-
MAINTAINERS | 6 ++
app/test/test_cpuflags.c | 41 ++++++++
app/test/test_xmmt_ops.h | 12 +++
.../loongarch/loongarch_loongarch64_linux_gcc | 16 ++++
config/loongarch/meson.build | 43 +++++++++
doc/guides/contributing/design.rst | 2 +-
.../cross_build_dpdk_for_loongarch.rst | 87 +++++++++++++++++
doc/guides/linux_gsg/index.rst | 1 +
doc/guides/nics/features.rst | 8 ++
doc/guides/nics/features/default.ini | 1 +
doc/guides/nics/features/ixgbe.ini | 1 +
doc/guides/rel_notes/release_22_11.rst | 7 ++
drivers/net/i40e/meson.build | 6 ++
drivers/net/ixgbe/ixgbe_rxtx.c | 7 +-
drivers/net/memif/rte_eth_memif.h | 2 +
drivers/net/tap/tap_bpf.h | 2 +
examples/l3fwd/l3fwd_em.c | 8 ++
lib/eal/linux/eal_memory.c | 4 +
lib/eal/loongarch/include/meson.build | 18 ++++
lib/eal/loongarch/include/rte_atomic.h | 47 ++++++++++
lib/eal/loongarch/include/rte_byteorder.h | 40 ++++++++
lib/eal/loongarch/include/rte_cpuflags.h | 39 ++++++++
lib/eal/loongarch/include/rte_cycles.h | 47 ++++++++++
lib/eal/loongarch/include/rte_io.h | 18 ++++
lib/eal/loongarch/include/rte_memcpy.h | 61 ++++++++++++
lib/eal/loongarch/include/rte_pause.h | 24 +++++
.../loongarch/include/rte_power_intrinsics.h | 20 ++++
lib/eal/loongarch/include/rte_prefetch.h | 47 ++++++++++
lib/eal/loongarch/include/rte_rwlock.h | 42 +++++++++
lib/eal/loongarch/include/rte_spinlock.h | 64 +++++++++++++
lib/eal/loongarch/include/rte_vect.h | 65 +++++++++++++
lib/eal/loongarch/meson.build | 11 +++
lib/eal/loongarch/rte_cpuflags.c | 93 +++++++++++++++++++
lib/eal/loongarch/rte_cycles.c | 45 +++++++++
lib/eal/loongarch/rte_hypervisor.c | 11 +++
lib/eal/loongarch/rte_power_intrinsics.c | 51 ++++++++++
meson.build | 2 +
39 files changed, 1015 insertions(+), 4 deletions(-)
create mode 100644 config/loongarch/loongarch_loongarch64_linux_gcc
create mode 100644 config/loongarch/meson.build
create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst
create mode 100644 lib/eal/loongarch/include/meson.build
create mode 100644 lib/eal/loongarch/include/rte_atomic.h
create mode 100644 lib/eal/loongarch/include/rte_byteorder.h
create mode 100644 lib/eal/loongarch/include/rte_cpuflags.h
create mode 100644 lib/eal/loongarch/include/rte_cycles.h
create mode 100644 lib/eal/loongarch/include/rte_io.h
create mode 100644 lib/eal/loongarch/include/rte_memcpy.h
create mode 100644 lib/eal/loongarch/include/rte_pause.h
create mode 100644 lib/eal/loongarch/include/rte_power_intrinsics.h
create mode 100644 lib/eal/loongarch/include/rte_prefetch.h
create mode 100644 lib/eal/loongarch/include/rte_rwlock.h
create mode 100644 lib/eal/loongarch/include/rte_spinlock.h
create mode 100644 lib/eal/loongarch/include/rte_vect.h
create mode 100644 lib/eal/loongarch/meson.build
create mode 100644 lib/eal/loongarch/rte_cpuflags.c
create mode 100644 lib/eal/loongarch/rte_cycles.c
create mode 100644 lib/eal/loongarch/rte_hypervisor.c
create mode 100644 lib/eal/loongarch/rte_power_intrinsics.c
--
2.32.1 (Apple Git-133)
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v6 1/7] eal/loongarch: support LoongArch architecture
2022-08-27 8:59 [PATCH v6 0/7] Introduce support for LoongArch architecture Min Zhou
@ 2022-08-27 8:59 ` Min Zhou
2022-08-27 8:59 ` [PATCH v6 2/7] net/ixgbe: add vector stubs for LoongArch Min Zhou
` (8 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Min Zhou @ 2022-08-27 8:59 UTC (permalink / raw)
To: david.marchand, thomas, bruce.richardson, anatoly.burakov,
qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev,
zhoumin
Cc: dev, maobibo
Add all necessary elements for DPDK to compile and run EAL on
LoongArch64 Soc.
This includes:
- EAL library implementation for LoongArch ISA.
- meson build structure for 'loongarch' architecture.
RTE_ARCH_LOONGARCH define is added for architecture identification.
- xmm_t structure operation stubs as there is no vector support in
the current version for LoongArch.
Compilation was tested on Debian and CentOS using loongarch64
cross-compile toolchain from x86 build hosts. Functions were tested
on Loongnix and Kylin which are two Linux distributions supported
LoongArch host based on Linux 4.19 maintained by Loongson
Corporation.
We also tested DPDK on LoongArch with some external applications,
including: Pktgen-DPDK, OVS, VPP.
The platform is currently marked as linux-only because there is no
other OS than Linux support LoongArch host currently.
The i40e PMD driver is disabled on LoongArch because of the absence
of vector support in the current version.
Similar to RISC-V, the compilation of following modules has been
disabled by this commit and will be re-enabled in later commits as
fixes are introduced:
net/ixgbe, net/memif, net/tap, example/l3fwd.
Signed-off-by: Min Zhou <zhoumin@loongson.cn>
---
MAINTAINERS | 6 ++
app/test/test_xmmt_ops.h | 12 +++
.../loongarch/loongarch_loongarch64_linux_gcc | 16 ++++
config/loongarch/meson.build | 43 +++++++++
doc/guides/contributing/design.rst | 2 +-
.../cross_build_dpdk_for_loongarch.rst | 87 +++++++++++++++++
doc/guides/linux_gsg/index.rst | 1 +
doc/guides/nics/features.rst | 8 ++
doc/guides/nics/features/default.ini | 1 +
doc/guides/rel_notes/release_22_11.rst | 7 ++
drivers/net/i40e/meson.build | 6 ++
drivers/net/ixgbe/meson.build | 6 ++
drivers/net/memif/meson.build | 6 ++
drivers/net/tap/meson.build | 6 ++
examples/l3fwd/meson.build | 6 ++
lib/eal/linux/eal_memory.c | 4 +
lib/eal/loongarch/include/meson.build | 18 ++++
lib/eal/loongarch/include/rte_atomic.h | 47 ++++++++++
lib/eal/loongarch/include/rte_byteorder.h | 40 ++++++++
lib/eal/loongarch/include/rte_cpuflags.h | 39 ++++++++
lib/eal/loongarch/include/rte_cycles.h | 47 ++++++++++
lib/eal/loongarch/include/rte_io.h | 18 ++++
lib/eal/loongarch/include/rte_memcpy.h | 61 ++++++++++++
lib/eal/loongarch/include/rte_pause.h | 24 +++++
.../loongarch/include/rte_power_intrinsics.h | 20 ++++
lib/eal/loongarch/include/rte_prefetch.h | 47 ++++++++++
lib/eal/loongarch/include/rte_rwlock.h | 42 +++++++++
lib/eal/loongarch/include/rte_spinlock.h | 64 +++++++++++++
lib/eal/loongarch/include/rte_vect.h | 65 +++++++++++++
lib/eal/loongarch/meson.build | 11 +++
lib/eal/loongarch/rte_cpuflags.c | 93 +++++++++++++++++++
lib/eal/loongarch/rte_cycles.c | 45 +++++++++
lib/eal/loongarch/rte_hypervisor.c | 11 +++
lib/eal/loongarch/rte_power_intrinsics.c | 51 ++++++++++
meson.build | 2 +
35 files changed, 961 insertions(+), 1 deletion(-)
create mode 100644 config/loongarch/loongarch_loongarch64_linux_gcc
create mode 100644 config/loongarch/meson.build
create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst
create mode 100644 lib/eal/loongarch/include/meson.build
create mode 100644 lib/eal/loongarch/include/rte_atomic.h
create mode 100644 lib/eal/loongarch/include/rte_byteorder.h
create mode 100644 lib/eal/loongarch/include/rte_cpuflags.h
create mode 100644 lib/eal/loongarch/include/rte_cycles.h
create mode 100644 lib/eal/loongarch/include/rte_io.h
create mode 100644 lib/eal/loongarch/include/rte_memcpy.h
create mode 100644 lib/eal/loongarch/include/rte_pause.h
create mode 100644 lib/eal/loongarch/include/rte_power_intrinsics.h
create mode 100644 lib/eal/loongarch/include/rte_prefetch.h
create mode 100644 lib/eal/loongarch/include/rte_rwlock.h
create mode 100644 lib/eal/loongarch/include/rte_spinlock.h
create mode 100644 lib/eal/loongarch/include/rte_vect.h
create mode 100644 lib/eal/loongarch/meson.build
create mode 100644 lib/eal/loongarch/rte_cpuflags.c
create mode 100644 lib/eal/loongarch/rte_cycles.c
create mode 100644 lib/eal/loongarch/rte_hypervisor.c
create mode 100644 lib/eal/loongarch/rte_power_intrinsics.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 32ffdd1a61..4700e58a5c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -295,6 +295,12 @@ F: app/*/*_neon.*
F: examples/*/*_neon.*
F: examples/common/neon/
+LoongArch
+M: Min Zhou <zhoumin@loongson.cn>
+F: config/loongarch/
+F: doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst
+F: lib/eal/loongarch/
+
IBM POWER (alpha)
M: David Christensen <drc@linux.vnet.ibm.com>
F: config/ppc/
diff --git a/app/test/test_xmmt_ops.h b/app/test/test_xmmt_ops.h
index 55f256599e..626aa9bcba 100644
--- a/app/test/test_xmmt_ops.h
+++ b/app/test/test_xmmt_ops.h
@@ -65,6 +65,18 @@ vect_set_epi32(int i3, int i2, int i1, int i0)
return data;
}
+#elif defined(RTE_ARCH_LOONGARCH)
+
+#define vect_loadu_sil128(p) vect_load_128(p)
+
+/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */
+static __rte_always_inline xmm_t
+vect_set_epi32(int i3, int i2, int i1, int i0)
+{
+ xmm_t data = (xmm_t){.u32 = {i0, i1, i2, i3}};
+
+ return data;
+}
#endif
#endif /* _TEST_XMMT_OPS_H_ */
diff --git a/config/loongarch/loongarch_loongarch64_linux_gcc b/config/loongarch/loongarch_loongarch64_linux_gcc
new file mode 100644
index 0000000000..0c44ae96e6
--- /dev/null
+++ b/config/loongarch/loongarch_loongarch64_linux_gcc
@@ -0,0 +1,16 @@
+[binaries]
+c = 'loongarch64-unknown-linux-gnu-gcc'
+cpp = 'loongarch64-unknown-linux-gnu-cpp'
+ar = 'loongarch64-unknown-linux-gnu-gcc-ar'
+strip = 'loongarch64-unknown-linux-gnu-strip'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'loongarch64'
+cpu = '3a5000'
+endian = 'little'
+
+[properties]
+implementor_id = 'generic'
+implementor_pn = 'default'
diff --git a/config/loongarch/meson.build b/config/loongarch/meson.build
new file mode 100644
index 0000000000..99dabef203
--- /dev/null
+++ b/config/loongarch/meson.build
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2022 Loongson Technology Corporation Limited
+
+if not dpdk_conf.get('RTE_ARCH_64')
+ error('Only 64-bit compiles are supported for this platform type')
+endif
+dpdk_conf.set('RTE_ARCH', 'loongarch')
+dpdk_conf.set('RTE_ARCH_LOONGARCH', 1)
+dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
+
+machine_args_generic = [
+ ['default', ['-march=loongarch64']],
+]
+
+flags_generic = [
+ ['RTE_MACHINE', '"loongarch64"'],
+ ['RTE_MAX_LCORE', 64],
+ ['RTE_MAX_NUMA_NODES', 16],
+ ['RTE_CACHE_LINE_SIZE', 64]]
+
+impl_generic = ['Generic loongarch', flags_generic, machine_args_generic]
+
+machine = []
+machine_args = []
+
+machine = impl_generic
+impl_pn = 'default'
+
+message('Implementer : ' + machine[0])
+foreach flag: machine[1]
+ if flag.length() > 0
+ dpdk_conf.set(flag[0], flag[1])
+ endif
+endforeach
+
+foreach marg: machine[2]
+ if marg[0] == impl_pn
+ foreach f: marg[1]
+ machine_args += f
+ endforeach
+ endif
+endforeach
+message(machine_args)
diff --git a/doc/guides/contributing/design.rst b/doc/guides/contributing/design.rst
index 0383afe5c8..d24a7ff6a0 100644
--- a/doc/guides/contributing/design.rst
+++ b/doc/guides/contributing/design.rst
@@ -42,7 +42,7 @@ Per Architecture Sources
The following macro options can be used:
* ``RTE_ARCH`` is a string that contains the name of the architecture.
-* ``RTE_ARCH_I686``, ``RTE_ARCH_X86_64``, ``RTE_ARCH_X86_X32``, ``RTE_ARCH_PPC_64``, ``RTE_ARCH_RISCV``, ``RTE_ARCH_ARM``, ``RTE_ARCH_ARMv7`` or ``RTE_ARCH_ARM64`` are defined only if we are building for those architectures.
+* ``RTE_ARCH_I686``, ``RTE_ARCH_X86_64``, ``RTE_ARCH_X86_X32``, ``RTE_ARCH_PPC_64``, ``RTE_ARCH_RISCV``, ``RTE_ARCH_LOONGARCH``, ``RTE_ARCH_ARM``, ``RTE_ARCH_ARMv7`` or ``RTE_ARCH_ARM64`` are defined only if we are building for those architectures.
Per Execution Environment Sources
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst b/doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst
new file mode 100644
index 0000000000..3afc6d4933
--- /dev/null
+++ b/doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst
@@ -0,0 +1,87 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+ Copyright(c) 2022 Loongson Technology Corporation Limited
+
+Cross compiling DPDK for LoongArch
+==================================
+
+This chapter describes how to cross compile DPDK for LoongArch from x86 build
+hosts.
+
+.. note::
+
+ Due to some of the code under review, the current Linux 5.19 cannot boot
+ on LoongArch system. There are still some Linux distributions that have
+ supported LoongArch host, such as Anolis OS, Kylin, Loongnix and UOS. These
+ distributions base on Linux kernel 4.19 supported by Loongson Corporation.
+ Because LoongArch is such a new platform with many fundamental pieces of
+ software still under development, it is currently recommended to cross
+ compile DPDK on x86 for LoongArch.
+
+
+Prerequisites
+-------------
+
+Ensure that you have all pre-requisites for building DPDK natively as those
+will be required also for cross-compilation.
+
+Linux kernel
+~~~~~~~~~~~~
+
+Make sure that LoongArch host is running Linux kernel 4.19 or newer supported
+by Loongson Corporation. The support for LoongArch in the current Linux 5.19
+is not complete because it still misses some patches to add for other
+subsystems.
+
+GNU toolchain
+-------------
+
+Obtain the cross toolchain
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The build process was tested using:
+
+* Latest `LoongArch GNU toolchain
+ <https://github.com/loongson/build-tools/releases/download/2022.08.11/loongarch64-clfs-5.1-cross-tools-gcc-glibc.tar.xz>`_
+ on Debian 10.4 or CentOS 8.
+
+Alternatively the toolchain may be built straight from the source via CLFS, to
+do that follow the instructions on `CLFS for LoongArch64
+<https://github.com/sunhaiyong1978/CLFS-for-LoongArch>`_ github page.
+
+To download cross tools from github we can use the following command:
+
+.. code-block:: console
+
+ wget -P /tmp/ https://github.com/loongson/build-tools/releases/download/2022.08.11/loongarch64-clfs-5.1-cross-tools-gcc-glibc.tar.xz
+
+Unzip and add into the PATH
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+After downloading the cross-tools file, we need unzip and add those executable
+binaries into the PATH as follows:
+
+.. code-block:: console
+
+ tar -xvf /tmp/loongarch64-clfs-5.1-cross-tools-gcc-glibc.tar.xz -C <cross_tool_install_dir> --strip-components 1
+ export PATH=$PATH:<cross_tool_install_dir>/bin
+
+
+Cross Compiling DPDK with GNU toolchain using Meson
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+To cross-compile DPDK for generic LoongArch we can use the following command:
+
+.. code-block:: console
+
+ meson cross-build --cross-file config/loongarch/loongarch_loongarch64_linux_gcc
+ ninja -C cross-build
+
+Supported cross-compilation targets
+-----------------------------------
+
+Currently the following target is supported:
+
+* Generic LoongArch64 ISA: ``config/loongarch/loongarch_loongarch64_linux_gcc``
+
+To add a new target support, a corresponding cross-file has to be added to
+``config/loongarch`` directory.
diff --git a/doc/guides/linux_gsg/index.rst b/doc/guides/linux_gsg/index.rst
index 747552c385..c3e67bf9ec 100644
--- a/doc/guides/linux_gsg/index.rst
+++ b/doc/guides/linux_gsg/index.rst
@@ -14,6 +14,7 @@ Getting Started Guide for Linux
sys_reqs
build_dpdk
cross_build_dpdk_for_arm64
+ cross_build_dpdk_for_loongarch
cross_build_dpdk_for_riscv
linux_drivers
build_sample_apps
diff --git a/doc/guides/nics/features.rst b/doc/guides/nics/features.rst
index 7f6cb914a5..a8bf7bccb6 100644
--- a/doc/guides/nics/features.rst
+++ b/doc/guides/nics/features.rst
@@ -832,6 +832,14 @@ ARMv8
Support armv8a (64bit) architecture.
+.. _nic_features_loongarch64:
+
+LoongArch64
+-----------
+
+Support 64-bit LoongArch architecture.
+
+
.. _nic_features_power8:
Power8
diff --git a/doc/guides/nics/features/default.ini b/doc/guides/nics/features/default.ini
index d1db0c256a..fd8b097e33 100644
--- a/doc/guides/nics/features/default.ini
+++ b/doc/guides/nics/features/default.ini
@@ -71,6 +71,7 @@ Linux =
Windows =
ARMv7 =
ARMv8 =
+LoongArch64 =
Power8 =
rv64 =
x86-32 =
diff --git a/doc/guides/rel_notes/release_22_11.rst b/doc/guides/rel_notes/release_22_11.rst
index 8c021cf050..ec74470744 100644
--- a/doc/guides/rel_notes/release_22_11.rst
+++ b/doc/guides/rel_notes/release_22_11.rst
@@ -55,6 +55,13 @@ New Features
Also, make sure to start the actual text at the margin.
=======================================================
+* **Added initial LoongArch architecture support.**
+
+ Added EAL implementation for LoongArch architecture. The initial devices
+ the porting was tested on included Loongson 3A5000, Loongson 3C5000 and
+ Loongson 3C5000L. In theory this implementation should work with any target
+ based on ``LoongArch`` ISA.
+
Removed Items
-------------
diff --git a/drivers/net/i40e/meson.build b/drivers/net/i40e/meson.build
index 84fd42754e..16fd491b9a 100644
--- a/drivers/net/i40e/meson.build
+++ b/drivers/net/i40e/meson.build
@@ -7,6 +7,12 @@ if arch_subdir == 'riscv'
subdir_done()
endif
+if arch_subdir == 'loongarch'
+ build = false
+ reason = 'not supported on LoongArch'
+ subdir_done()
+endif
+
cflags += ['-DPF_DRIVER',
'-DVF_DRIVER',
'-DINTEGRATED_VF',
diff --git a/drivers/net/ixgbe/meson.build b/drivers/net/ixgbe/meson.build
index 162f8d5f46..3282a826ca 100644
--- a/drivers/net/ixgbe/meson.build
+++ b/drivers/net/ixgbe/meson.build
@@ -1,6 +1,12 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017 Intel Corporation
+if arch_subdir == 'loongarch'
+ build = false
+ reason = 'not supported on LoongArch'
+ subdir_done()
+endif
+
cflags += ['-DRTE_LIBRTE_IXGBE_BYPASS']
subdir('base')
diff --git a/drivers/net/memif/meson.build b/drivers/net/memif/meson.build
index 680bc8631c..30c0fbc798 100644
--- a/drivers/net/memif/meson.build
+++ b/drivers/net/memif/meson.build
@@ -1,6 +1,12 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright 2018-2019 Cisco Systems, Inc. All rights reserved.
+if arch_subdir == 'loongarch'
+ build = false
+ reason = 'not supported on LoongArch'
+ subdir_done()
+endif
+
if not is_linux
build = false
reason = 'only supported on Linux'
diff --git a/drivers/net/tap/meson.build b/drivers/net/tap/meson.build
index c09713a67b..f0d03069cd 100644
--- a/drivers/net/tap/meson.build
+++ b/drivers/net/tap/meson.build
@@ -1,6 +1,12 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright 2018 Luca Boccassi <bluca@debian.org>
+if arch_subdir == 'loongarch'
+ build = false
+ reason = 'not supported on LoongArch'
+ subdir_done()
+endif
+
if not is_linux
build = false
reason = 'only supported on Linux'
diff --git a/examples/l3fwd/meson.build b/examples/l3fwd/meson.build
index b40244a941..d2f2d96099 100644
--- a/examples/l3fwd/meson.build
+++ b/examples/l3fwd/meson.build
@@ -6,6 +6,12 @@
# To build this example as a standalone application with an already-installed
# DPDK instance, use 'make'
+if arch_subdir == 'loongarch'
+ build = false
+ reason = 'not supported on LoongArch'
+ subdir_done()
+endif
+
allow_experimental_apis = true
deps += ['acl', 'hash', 'lpm', 'fib', 'eventdev']
sources = files(
diff --git a/lib/eal/linux/eal_memory.c b/lib/eal/linux/eal_memory.c
index c890c42106..60fc8cc6ca 100644
--- a/lib/eal/linux/eal_memory.c
+++ b/lib/eal/linux/eal_memory.c
@@ -77,7 +77,11 @@ uint64_t eal_get_baseaddr(void)
* rte_mem_check_dma_mask for ensuring all memory is within supported
* range.
*/
+#if defined(RTE_ARCH_LOONGARCH)
+ return 0x7000000000ULL;
+#else
return 0x100000000ULL;
+#endif
}
/*
diff --git a/lib/eal/loongarch/include/meson.build b/lib/eal/loongarch/include/meson.build
new file mode 100644
index 0000000000..6e8d12601a
--- /dev/null
+++ b/lib/eal/loongarch/include/meson.build
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2022 Loongson Technology Corporation Limited
+
+arch_headers = files(
+ 'rte_atomic.h',
+ 'rte_byteorder.h',
+ 'rte_cpuflags.h',
+ 'rte_cycles.h',
+ 'rte_io.h',
+ 'rte_memcpy.h',
+ 'rte_pause.h',
+ 'rte_power_intrinsics.h',
+ 'rte_prefetch.h',
+ 'rte_rwlock.h',
+ 'rte_spinlock.h',
+ 'rte_vect.h',
+)
+install_headers(arch_headers, subdir: get_option('include_subdir_arch'))
diff --git a/lib/eal/loongarch/include/rte_atomic.h b/lib/eal/loongarch/include/rte_atomic.h
new file mode 100644
index 0000000000..b0ddcab72e
--- /dev/null
+++ b/lib/eal/loongarch/include/rte_atomic.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_ATOMIC_LOONGARCH_H_
+#define _RTE_ATOMIC_LOONGARCH_H_
+
+#ifndef RTE_FORCE_INTRINSICS
+# error Platform must be built with RTE_FORCE_INTRINSICS
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rte_common.h>
+#include "generic/rte_atomic.h"
+
+#define rte_mb() do { asm volatile("dbar 0":::"memory"); } while (0)
+
+#define rte_wmb() rte_mb()
+
+#define rte_rmb() rte_mb()
+
+#define rte_smp_mb() rte_mb()
+
+#define rte_smp_wmb() rte_mb()
+
+#define rte_smp_rmb() rte_mb()
+
+#define rte_io_mb() rte_mb()
+
+#define rte_io_wmb() rte_mb()
+
+#define rte_io_rmb() rte_mb()
+
+static __rte_always_inline void
+rte_atomic_thread_fence(int memorder)
+{
+ __atomic_thread_fence(memorder);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_ATOMIC_LOONGARCH_H_ */
diff --git a/lib/eal/loongarch/include/rte_byteorder.h b/lib/eal/loongarch/include/rte_byteorder.h
new file mode 100644
index 0000000000..ba27998497
--- /dev/null
+++ b/lib/eal/loongarch/include/rte_byteorder.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_BYTEORDER_LOONGARCH_H_
+#define _RTE_BYTEORDER_LOONGARCH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_byteorder.h"
+
+#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
+
+#define rte_cpu_to_le_16(x) (x)
+#define rte_cpu_to_le_32(x) (x)
+#define rte_cpu_to_le_64(x) (x)
+
+#define rte_cpu_to_be_16(x) rte_bswap16(x)
+#define rte_cpu_to_be_32(x) rte_bswap32(x)
+#define rte_cpu_to_be_64(x) rte_bswap64(x)
+
+#define rte_le_to_cpu_16(x) (x)
+#define rte_le_to_cpu_32(x) (x)
+#define rte_le_to_cpu_64(x) (x)
+
+#define rte_be_to_cpu_16(x) rte_bswap16(x)
+#define rte_be_to_cpu_32(x) rte_bswap32(x)
+#define rte_be_to_cpu_64(x) rte_bswap64(x)
+
+#else /* RTE_BIG_ENDIAN */
+#error "LoongArch not support big endian!"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_BYTEORDER_LOONGARCH_H_ */
diff --git a/lib/eal/loongarch/include/rte_cpuflags.h b/lib/eal/loongarch/include/rte_cpuflags.h
new file mode 100644
index 0000000000..d9121a00a8
--- /dev/null
+++ b/lib/eal/loongarch/include/rte_cpuflags.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_CPUFLAGS_LOONGARCH_H_
+#define _RTE_CPUFLAGS_LOONGARCH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Enumeration of all CPU features supported
+ */
+enum rte_cpu_flag_t {
+ RTE_CPUFLAG_CPUCFG = 0,
+ RTE_CPUFLAG_LAM,
+ RTE_CPUFLAG_UAL,
+ RTE_CPUFLAG_FPU,
+ RTE_CPUFLAG_LSX,
+ RTE_CPUFLAG_LASX,
+ RTE_CPUFLAG_CRC32,
+ RTE_CPUFLAG_COMPLEX,
+ RTE_CPUFLAG_CRYPTO,
+ RTE_CPUFLAG_LVZ,
+ RTE_CPUFLAG_LBT_X86,
+ RTE_CPUFLAG_LBT_ARM,
+ RTE_CPUFLAG_LBT_MIPS,
+ /* The last item */
+ RTE_CPUFLAG_NUMFLAGS /**< This should always be the last! */
+};
+
+#include "generic/rte_cpuflags.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_CPUFLAGS_LOONGARCH_H_ */
diff --git a/lib/eal/loongarch/include/rte_cycles.h b/lib/eal/loongarch/include/rte_cycles.h
new file mode 100644
index 0000000000..0f1539be1b
--- /dev/null
+++ b/lib/eal/loongarch/include/rte_cycles.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_CYCLES_LOONGARCH_H_
+#define _RTE_CYCLES_LOONGARCH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_cycles.h"
+
+/**
+ * Read the time base register.
+ *
+ * @return
+ * The time base for this lcore.
+ */
+static inline uint64_t
+rte_rdtsc(void)
+{
+ uint64_t count;
+
+ __asm__ __volatile__ (
+ "rdtime.d %[cycles], $zero\n"
+ : [cycles] "=r" (count)
+ ::
+ );
+ return count;
+}
+
+static inline uint64_t
+rte_rdtsc_precise(void)
+{
+ rte_mb();
+ return rte_rdtsc();
+}
+
+static inline uint64_t
+rte_get_tsc_cycles(void) { return rte_rdtsc(); }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_CYCLES_LOONGARCH_H_ */
diff --git a/lib/eal/loongarch/include/rte_io.h b/lib/eal/loongarch/include/rte_io.h
new file mode 100644
index 0000000000..af152a727a
--- /dev/null
+++ b/lib/eal/loongarch/include/rte_io.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_IO_LOONGARCH_H_
+#define _RTE_IO_LOONGARCH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_io.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_IO_LOONGARCH_H_ */
diff --git a/lib/eal/loongarch/include/rte_memcpy.h b/lib/eal/loongarch/include/rte_memcpy.h
new file mode 100644
index 0000000000..e7b91e9ce4
--- /dev/null
+++ b/lib/eal/loongarch/include/rte_memcpy.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_MEMCPY_LOONGARCH_H_
+#define _RTE_MEMCPY_LOONGARCH_H_
+
+#include <stdint.h>
+#include <string.h>
+
+#include "rte_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_memcpy.h"
+
+static inline void
+rte_mov16(uint8_t *dst, const uint8_t *src)
+{
+ memcpy(dst, src, 16);
+}
+
+static inline void
+rte_mov32(uint8_t *dst, const uint8_t *src)
+{
+ memcpy(dst, src, 32);
+}
+
+static inline void
+rte_mov48(uint8_t *dst, const uint8_t *src)
+{
+ memcpy(dst, src, 48);
+}
+
+static inline void
+rte_mov64(uint8_t *dst, const uint8_t *src)
+{
+ memcpy(dst, src, 64);
+}
+
+static inline void
+rte_mov128(uint8_t *dst, const uint8_t *src)
+{
+ memcpy(dst, src, 128);
+}
+
+static inline void
+rte_mov256(uint8_t *dst, const uint8_t *src)
+{
+ memcpy(dst, src, 256);
+}
+
+#define rte_memcpy(d, s, n) memcpy((d), (s), (n))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_MEMCPY_LOONGARCH_H_ */
diff --git a/lib/eal/loongarch/include/rte_pause.h b/lib/eal/loongarch/include/rte_pause.h
new file mode 100644
index 0000000000..438de23128
--- /dev/null
+++ b/lib/eal/loongarch/include/rte_pause.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_PAUSE_LOONGARCH_H_
+#define _RTE_PAUSE_LOONGARCH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "rte_atomic.h"
+
+#include "generic/rte_pause.h"
+
+static inline void rte_pause(void)
+{
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_PAUSE_LOONGARCH_H_ */
diff --git a/lib/eal/loongarch/include/rte_power_intrinsics.h b/lib/eal/loongarch/include/rte_power_intrinsics.h
new file mode 100644
index 0000000000..b6a2c0d82e
--- /dev/null
+++ b/lib/eal/loongarch/include/rte_power_intrinsics.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_POWER_INTRINSIC_LOONGARCH_H_
+#define _RTE_POWER_INTRINSIC_LOONGARCH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rte_common.h>
+
+#include "generic/rte_power_intrinsics.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_POWER_INTRINSIC_LOONGARCH_H_ */
diff --git a/lib/eal/loongarch/include/rte_prefetch.h b/lib/eal/loongarch/include/rte_prefetch.h
new file mode 100644
index 0000000000..0fd9262ea8
--- /dev/null
+++ b/lib/eal/loongarch/include/rte_prefetch.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_PREFETCH_LOONGARCH_H_
+#define _RTE_PREFETCH_LOONGARCH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rte_common.h>
+#include "generic/rte_prefetch.h"
+
+static inline void rte_prefetch0(const volatile void *p)
+{
+ __builtin_prefetch((const void *)(uintptr_t)p, 0, 3);
+}
+
+static inline void rte_prefetch1(const volatile void *p)
+{
+ __builtin_prefetch((const void *)(uintptr_t)p, 0, 2);
+}
+
+static inline void rte_prefetch2(const volatile void *p)
+{
+ __builtin_prefetch((const void *)(uintptr_t)p, 0, 1);
+}
+
+static inline void rte_prefetch_non_temporal(const volatile void *p)
+{
+ /* non-temporal version not available, fallback to rte_prefetch0 */
+ rte_prefetch0(p);
+}
+
+__rte_experimental
+static inline void
+rte_cldemote(const volatile void *p)
+{
+ RTE_SET_USED(p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_PREFETCH_LOONGARCH_H_ */
diff --git a/lib/eal/loongarch/include/rte_rwlock.h b/lib/eal/loongarch/include/rte_rwlock.h
new file mode 100644
index 0000000000..aac6f60120
--- /dev/null
+++ b/lib/eal/loongarch/include/rte_rwlock.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_RWLOCK_LOONGARCH_H_
+#define _RTE_RWLOCK_LOONGARCH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_rwlock.h"
+
+static inline void
+rte_rwlock_read_lock_tm(rte_rwlock_t *rwl)
+{
+ rte_rwlock_read_lock(rwl);
+}
+
+static inline void
+rte_rwlock_read_unlock_tm(rte_rwlock_t *rwl)
+{
+ rte_rwlock_read_unlock(rwl);
+}
+
+static inline void
+rte_rwlock_write_lock_tm(rte_rwlock_t *rwl)
+{
+ rte_rwlock_write_lock(rwl);
+}
+
+static inline void
+rte_rwlock_write_unlock_tm(rte_rwlock_t *rwl)
+{
+ rte_rwlock_write_unlock(rwl);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_RWLOCK_LOONGARCH_H_ */
diff --git a/lib/eal/loongarch/include/rte_spinlock.h b/lib/eal/loongarch/include/rte_spinlock.h
new file mode 100644
index 0000000000..dd07538c7f
--- /dev/null
+++ b/lib/eal/loongarch/include/rte_spinlock.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_SPINLOCK_LOONGARCH_H_
+#define _RTE_SPINLOCK_LOONGARCH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rte_common.h>
+#include "generic/rte_spinlock.h"
+
+#ifndef RTE_FORCE_INTRINSICS
+# error Platform must be built with RTE_FORCE_INTRINSICS
+#endif
+
+static inline int rte_tm_supported(void)
+{
+ return 0;
+}
+
+static inline void
+rte_spinlock_lock_tm(rte_spinlock_t *sl)
+{
+ rte_spinlock_lock(sl); /* fall-back */
+}
+
+static inline int
+rte_spinlock_trylock_tm(rte_spinlock_t *sl)
+{
+ return rte_spinlock_trylock(sl);
+}
+
+static inline void
+rte_spinlock_unlock_tm(rte_spinlock_t *sl)
+{
+ rte_spinlock_unlock(sl);
+}
+
+static inline void
+rte_spinlock_recursive_lock_tm(rte_spinlock_recursive_t *slr)
+{
+ rte_spinlock_recursive_lock(slr); /* fall-back */
+}
+
+static inline void
+rte_spinlock_recursive_unlock_tm(rte_spinlock_recursive_t *slr)
+{
+ rte_spinlock_recursive_unlock(slr);
+}
+
+static inline int
+rte_spinlock_recursive_trylock_tm(rte_spinlock_recursive_t *slr)
+{
+ return rte_spinlock_recursive_trylock(slr);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_SPINLOCK_LOONGARCH_H_ */
diff --git a/lib/eal/loongarch/include/rte_vect.h b/lib/eal/loongarch/include/rte_vect.h
new file mode 100644
index 0000000000..5951a2674c
--- /dev/null
+++ b/lib/eal/loongarch/include/rte_vect.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#ifndef _RTE_VECT_LOONGARCH_H_
+#define _RTE_VECT_LOONGARCH_H_
+
+#include <stdint.h>
+#include "generic/rte_vect.h"
+#include "rte_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RTE_VECT_DEFAULT_SIMD_BITWIDTH RTE_VECT_SIMD_DISABLED
+
+typedef union xmm {
+ int8_t i8[16];
+ int16_t i16[8];
+ int32_t i32[4];
+ int64_t i64[2];
+ uint8_t u8[16];
+ uint16_t u16[8];
+ uint32_t u32[4];
+ uint64_t u64[2];
+ double pd[2];
+} __rte_aligned(16) xmm_t;
+
+#define XMM_SIZE (sizeof(xmm_t))
+#define XMM_MASK (XMM_SIZE - 1)
+
+typedef union rte_xmm {
+ xmm_t x;
+ uint8_t u8[XMM_SIZE / sizeof(uint8_t)];
+ uint16_t u16[XMM_SIZE / sizeof(uint16_t)];
+ uint32_t u32[XMM_SIZE / sizeof(uint32_t)];
+ uint64_t u64[XMM_SIZE / sizeof(uint64_t)];
+ double pd[XMM_SIZE / sizeof(double)];
+} __rte_aligned(16) rte_xmm_t;
+
+static inline xmm_t
+vect_load_128(void *p)
+{
+ xmm_t ret = *((xmm_t *)p);
+
+ return ret;
+}
+
+static inline xmm_t
+vect_and(xmm_t data, xmm_t mask)
+{
+ rte_xmm_t ret = {.x = data };
+ rte_xmm_t m = {.x = mask };
+ ret.u64[0] &= m.u64[0];
+ ret.u64[1] &= m.u64[1];
+
+ return ret.x;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/lib/eal/loongarch/meson.build b/lib/eal/loongarch/meson.build
new file mode 100644
index 0000000000..4dcc27babb
--- /dev/null
+++ b/lib/eal/loongarch/meson.build
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2022 Loongson Technology Corporation Limited
+
+subdir('include')
+
+sources += files(
+ 'rte_cpuflags.c',
+ 'rte_cycles.c',
+ 'rte_hypervisor.c',
+ 'rte_power_intrinsics.c',
+)
diff --git a/lib/eal/loongarch/rte_cpuflags.c b/lib/eal/loongarch/rte_cpuflags.c
new file mode 100644
index 0000000000..0a75ca58d4
--- /dev/null
+++ b/lib/eal/loongarch/rte_cpuflags.c
@@ -0,0 +1,93 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#include "rte_cpuflags.h"
+
+#include <elf.h>
+#include <fcntl.h>
+#include <assert.h>
+#include <unistd.h>
+#include <string.h>
+
+/* Symbolic values for the entries in the auxiliary table */
+#define AT_HWCAP 16
+
+/* software based registers */
+enum cpu_register_t {
+ REG_NONE = 0,
+ REG_HWCAP,
+ REG_MAX
+};
+
+typedef uint32_t hwcap_registers_t[REG_MAX];
+
+struct feature_entry {
+ uint32_t reg;
+ uint32_t bit;
+#define CPU_FLAG_NAME_MAX_LEN 64
+ char name[CPU_FLAG_NAME_MAX_LEN];
+};
+
+#define FEAT_DEF(name, reg, bit) \
+ [RTE_CPUFLAG_##name] = {reg, bit, #name},
+
+const struct feature_entry rte_cpu_feature_table[] = {
+ FEAT_DEF(CPUCFG, REG_HWCAP, 0)
+ FEAT_DEF(LAM, REG_HWCAP, 1)
+ FEAT_DEF(UAL, REG_HWCAP, 2)
+ FEAT_DEF(FPU, REG_HWCAP, 3)
+ FEAT_DEF(LSX, REG_HWCAP, 4)
+ FEAT_DEF(LASX, REG_HWCAP, 5)
+ FEAT_DEF(CRC32, REG_HWCAP, 6)
+ FEAT_DEF(COMPLEX, REG_HWCAP, 7)
+ FEAT_DEF(CRYPTO, REG_HWCAP, 8)
+ FEAT_DEF(LVZ, REG_HWCAP, 9)
+ FEAT_DEF(LBT_X86, REG_HWCAP, 10)
+ FEAT_DEF(LBT_ARM, REG_HWCAP, 11)
+ FEAT_DEF(LBT_MIPS, REG_HWCAP, 12)
+};
+
+/*
+ * Read AUXV software register and get cpu features for LoongArch
+ */
+static void
+rte_cpu_get_features(hwcap_registers_t out)
+{
+ out[REG_HWCAP] = rte_cpu_getauxval(AT_HWCAP);
+}
+
+/*
+ * Checks if a particular flag is available on current machine.
+ */
+int
+rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
+{
+ const struct feature_entry *feat;
+ hwcap_registers_t regs = {0};
+
+ if (feature >= RTE_CPUFLAG_NUMFLAGS)
+ return -ENOENT;
+
+ feat = &rte_cpu_feature_table[feature];
+ if (feat->reg == REG_NONE)
+ return -EFAULT;
+
+ rte_cpu_get_features(regs);
+ return (regs[feat->reg] >> feat->bit) & 1;
+}
+
+const char *
+rte_cpu_get_flag_name(enum rte_cpu_flag_t feature)
+{
+ if (feature >= RTE_CPUFLAG_NUMFLAGS)
+ return NULL;
+ return rte_cpu_feature_table[feature].name;
+}
+
+void
+rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics)
+{
+ memset(intrinsics, 0, sizeof(*intrinsics));
+}
diff --git a/lib/eal/loongarch/rte_cycles.c b/lib/eal/loongarch/rte_cycles.c
new file mode 100644
index 0000000000..582601d335
--- /dev/null
+++ b/lib/eal/loongarch/rte_cycles.c
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#include "eal_private.h"
+
+#define LOONGARCH_CPUCFG4 0x4
+#define CPUCFG4_CCFREQ_MASK 0xFFFFFFFF
+#define CPUCFG4_CCFREQ_SHIFT 0
+
+#define LOONGARCH_CPUCFG5 0x5
+#define CPUCFG5_CCMUL_MASK 0xFFFF
+#define CPUCFG5_CCMUL_SHIFT 0
+
+#define CPUCFG5_CCDIV_MASK 0xFFFF0000
+#define CPUCFG5_CCDIV_SHIFT 16
+
+static __rte_noinline uint32_t
+read_cpucfg(int arg)
+{
+ int ret = 0;
+
+ __asm__ __volatile__ (
+ "cpucfg %[var], %[index]\n"
+ : [var]"=r"(ret)
+ : [index]"r"(arg)
+ :
+ );
+
+ return ret;
+}
+
+uint64_t
+get_tsc_freq_arch(void)
+{
+ uint32_t base_freq, mul_factor, div_factor;
+
+ base_freq = read_cpucfg(LOONGARCH_CPUCFG4);
+ mul_factor = (read_cpucfg(LOONGARCH_CPUCFG5) & CPUCFG5_CCMUL_MASK) >>
+ CPUCFG5_CCMUL_SHIFT;
+ div_factor = (read_cpucfg(LOONGARCH_CPUCFG5) & CPUCFG5_CCDIV_MASK) >>
+ CPUCFG5_CCDIV_SHIFT;
+
+ return base_freq * mul_factor / div_factor;
+}
diff --git a/lib/eal/loongarch/rte_hypervisor.c b/lib/eal/loongarch/rte_hypervisor.c
new file mode 100644
index 0000000000..d044906f71
--- /dev/null
+++ b/lib/eal/loongarch/rte_hypervisor.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#include "rte_hypervisor.h"
+
+enum rte_hypervisor
+rte_hypervisor_get(void)
+{
+ return RTE_HYPERVISOR_UNKNOWN;
+}
diff --git a/lib/eal/loongarch/rte_power_intrinsics.c b/lib/eal/loongarch/rte_power_intrinsics.c
new file mode 100644
index 0000000000..3dd1375ce4
--- /dev/null
+++ b/lib/eal/loongarch/rte_power_intrinsics.c
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Loongson Technology Corporation Limited
+ */
+
+#include "rte_power_intrinsics.h"
+
+/**
+ * This function is not supported on LOONGARCH.
+ */
+int
+rte_power_monitor(const struct rte_power_monitor_cond *pmc,
+ const uint64_t tsc_timestamp)
+{
+ RTE_SET_USED(pmc);
+ RTE_SET_USED(tsc_timestamp);
+
+ return -ENOTSUP;
+}
+
+/**
+ * This function is not supported on LOONGARCH.
+ */
+int
+rte_power_pause(const uint64_t tsc_timestamp)
+{
+ RTE_SET_USED(tsc_timestamp);
+
+ return -ENOTSUP;
+}
+
+/**
+ * This function is not supported on LOONGARCH.
+ */
+int
+rte_power_monitor_wakeup(const unsigned int lcore_id)
+{
+ RTE_SET_USED(lcore_id);
+
+ return -ENOTSUP;
+}
+
+int
+rte_power_monitor_multi(const struct rte_power_monitor_cond pmc[],
+ const uint32_t num, const uint64_t tsc_timestamp)
+{
+ RTE_SET_USED(pmc);
+ RTE_SET_USED(num);
+ RTE_SET_USED(tsc_timestamp);
+
+ return -ENOTSUP;
+}
diff --git a/meson.build b/meson.build
index a32f14024b..027724a6e5 100644
--- a/meson.build
+++ b/meson.build
@@ -56,6 +56,8 @@ elif host_machine.cpu_family().startswith('ppc')
arch_subdir = 'ppc'
elif host_machine.cpu_family().startswith('riscv')
arch_subdir = 'riscv'
+elif host_machine.cpu_family().startswith('loongarch')
+ arch_subdir = 'loongarch'
endif
# configure the build, and make sure configs here and in config folder are
--
2.32.1 (Apple Git-133)
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v6 2/7] net/ixgbe: add vector stubs for LoongArch
2022-08-27 8:59 [PATCH v6 0/7] Introduce support for LoongArch architecture Min Zhou
2022-08-27 8:59 ` [PATCH v6 1/7] eal/loongarch: support " Min Zhou
@ 2022-08-27 8:59 ` Min Zhou
2022-08-27 8:59 ` [PATCH v6 3/7] net/memif: set memfd syscall ID on LoongArch Min Zhou
` (7 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Min Zhou @ 2022-08-27 8:59 UTC (permalink / raw)
To: david.marchand, thomas, bruce.richardson, anatoly.burakov,
qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev,
zhoumin
Cc: dev, maobibo
Similar to RISC-V, the current version for LoongArch do not support
vector. Re-use vector processing stubs in ixgbe PMD defined for PPC
for LoongArch. This enables ixgbe PMD usage in scalar mode on
LoongArch.
The ixgbe PMD driver was validated with Intel X520-DA2 NIC and the
test-pmd application, l2fwd, l3fwd examples.
Signed-off-by: Min Zhou <zhoumin@loongson.cn>
---
doc/guides/nics/features/ixgbe.ini | 1 +
drivers/net/ixgbe/ixgbe_rxtx.c | 7 +++++--
drivers/net/ixgbe/meson.build | 6 ------
3 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/doc/guides/nics/features/ixgbe.ini b/doc/guides/nics/features/ixgbe.ini
index ab759a6fb3..97c0a6af9e 100644
--- a/doc/guides/nics/features/ixgbe.ini
+++ b/doc/guides/nics/features/ixgbe.ini
@@ -52,6 +52,7 @@ FreeBSD = Y
Linux = Y
Windows = Y
ARMv8 = Y
+LoongArch64 = Y
rv64 = Y
x86-32 = Y
x86-64 = Y
diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c
index 009d9b624a..c9d6ca9efe 100644
--- a/drivers/net/ixgbe/ixgbe_rxtx.c
+++ b/drivers/net/ixgbe/ixgbe_rxtx.c
@@ -5957,8 +5957,11 @@ ixgbe_config_rss_filter(struct rte_eth_dev *dev,
return 0;
}
-/* Stubs needed for linkage when RTE_ARCH_PPC_64 or RTE_ARCH_RISCV is set */
-#if defined(RTE_ARCH_PPC_64) || defined(RTE_ARCH_RISCV)
+/* Stubs needed for linkage when RTE_ARCH_PPC_64, RTE_ARCH_RISCV or
+ * RTE_ARCH_LOONGARCH is set.
+ */
+#if defined(RTE_ARCH_PPC_64) || defined(RTE_ARCH_RISCV) || \
+ defined(RTE_ARCH_LOONGARCH)
int
ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
{
diff --git a/drivers/net/ixgbe/meson.build b/drivers/net/ixgbe/meson.build
index 3282a826ca..162f8d5f46 100644
--- a/drivers/net/ixgbe/meson.build
+++ b/drivers/net/ixgbe/meson.build
@@ -1,12 +1,6 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017 Intel Corporation
-if arch_subdir == 'loongarch'
- build = false
- reason = 'not supported on LoongArch'
- subdir_done()
-endif
-
cflags += ['-DRTE_LIBRTE_IXGBE_BYPASS']
subdir('base')
--
2.32.1 (Apple Git-133)
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v6 3/7] net/memif: set memfd syscall ID on LoongArch
2022-08-27 8:59 [PATCH v6 0/7] Introduce support for LoongArch architecture Min Zhou
2022-08-27 8:59 ` [PATCH v6 1/7] eal/loongarch: support " Min Zhou
2022-08-27 8:59 ` [PATCH v6 2/7] net/ixgbe: add vector stubs for LoongArch Min Zhou
@ 2022-08-27 8:59 ` Min Zhou
2022-08-27 8:59 ` [PATCH v6 4/7] net/tap: set BPF syscall ID for LoongArch Min Zhou
` (6 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Min Zhou @ 2022-08-27 8:59 UTC (permalink / raw)
To: david.marchand, thomas, bruce.richardson, anatoly.burakov,
qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev,
zhoumin
Cc: dev, maobibo
Define the missing __NR_memfd_create syscall id to enable the memif
PMD on LoongArch.
Signed-off-by: Min Zhou <zhoumin@loongson.cn>
---
drivers/net/memif/meson.build | 6 ------
drivers/net/memif/rte_eth_memif.h | 2 ++
2 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/net/memif/meson.build b/drivers/net/memif/meson.build
index 30c0fbc798..680bc8631c 100644
--- a/drivers/net/memif/meson.build
+++ b/drivers/net/memif/meson.build
@@ -1,12 +1,6 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright 2018-2019 Cisco Systems, Inc. All rights reserved.
-if arch_subdir == 'loongarch'
- build = false
- reason = 'not supported on LoongArch'
- subdir_done()
-endif
-
if not is_linux
build = false
reason = 'only supported on Linux'
diff --git a/drivers/net/memif/rte_eth_memif.h b/drivers/net/memif/rte_eth_memif.h
index 81e7dceae0..eb692aee68 100644
--- a/drivers/net/memif/rte_eth_memif.h
+++ b/drivers/net/memif/rte_eth_memif.h
@@ -182,6 +182,8 @@ const char *memif_version(void);
#define __NR_memfd_create 356
#elif defined __riscv
#define __NR_memfd_create 279
+#elif defined __loongarch__
+#define __NR_memfd_create 279
#else
#error "__NR_memfd_create unknown for this architecture"
#endif
--
2.32.1 (Apple Git-133)
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v6 4/7] net/tap: set BPF syscall ID for LoongArch
2022-08-27 8:59 [PATCH v6 0/7] Introduce support for LoongArch architecture Min Zhou
` (2 preceding siblings ...)
2022-08-27 8:59 ` [PATCH v6 3/7] net/memif: set memfd syscall ID on LoongArch Min Zhou
@ 2022-08-27 8:59 ` Min Zhou
2022-08-27 8:59 ` [PATCH v6 5/7] examples/l3fwd: enable LoongArch operation Min Zhou
` (5 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Min Zhou @ 2022-08-27 8:59 UTC (permalink / raw)
To: david.marchand, thomas, bruce.richardson, anatoly.burakov,
qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev,
zhoumin
Cc: dev, maobibo
Define the missing __NR_bpf syscall id to enable the tap PMD on
LoongArch.
Signed-off-by: Min Zhou <zhoumin@loongson.cn>
---
drivers/net/tap/meson.build | 6 ------
drivers/net/tap/tap_bpf.h | 2 ++
2 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/net/tap/meson.build b/drivers/net/tap/meson.build
index f0d03069cd..c09713a67b 100644
--- a/drivers/net/tap/meson.build
+++ b/drivers/net/tap/meson.build
@@ -1,12 +1,6 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright 2018 Luca Boccassi <bluca@debian.org>
-if arch_subdir == 'loongarch'
- build = false
- reason = 'not supported on LoongArch'
- subdir_done()
-endif
-
if not is_linux
build = false
reason = 'only supported on Linux'
diff --git a/drivers/net/tap/tap_bpf.h b/drivers/net/tap/tap_bpf.h
index 639bdf3a79..0d38bc111f 100644
--- a/drivers/net/tap/tap_bpf.h
+++ b/drivers/net/tap/tap_bpf.h
@@ -103,6 +103,8 @@ union bpf_attr {
# define __NR_bpf 361
# elif defined(__riscv)
# define __NR_bpf 280
+# elif defined(__loongarch__)
+# define __NR_bpf 280
# else
# error __NR_bpf not defined
# endif
--
2.32.1 (Apple Git-133)
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v6 5/7] examples/l3fwd: enable LoongArch operation
2022-08-27 8:59 [PATCH v6 0/7] Introduce support for LoongArch architecture Min Zhou
` (3 preceding siblings ...)
2022-08-27 8:59 ` [PATCH v6 4/7] net/tap: set BPF syscall ID for LoongArch Min Zhou
@ 2022-08-27 8:59 ` Min Zhou
2022-08-27 8:59 ` [PATCH v6 6/7] test/cpuflags: add test for LoongArch cpu flag Min Zhou
` (4 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Min Zhou @ 2022-08-27 8:59 UTC (permalink / raw)
To: david.marchand, thomas, bruce.richardson, anatoly.burakov,
qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev,
zhoumin
Cc: dev, maobibo
Add missing em_mask_key() implementation to enable the l3fwd to be
run on LoongArch.
Signed-off-by: Min Zhou <zhoumin@loongson.cn>
---
examples/l3fwd/l3fwd_em.c | 8 ++++++++
examples/l3fwd/meson.build | 6 ------
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
index 10be24c61d..ad7d82e916 100644
--- a/examples/l3fwd/l3fwd_em.c
+++ b/examples/l3fwd/l3fwd_em.c
@@ -247,6 +247,14 @@ em_mask_key(void *key, xmm_t mask)
return vect_and(data, mask);
}
+#elif defined(RTE_ARCH_LOONGARCH)
+static inline xmm_t
+em_mask_key(void *key, xmm_t mask)
+{
+ xmm_t data = vect_load_128(key);
+
+ return vect_and(data, mask);
+}
#else
#error No vector engine (SSE, NEON, ALTIVEC) available, check your toolchain
#endif
diff --git a/examples/l3fwd/meson.build b/examples/l3fwd/meson.build
index d2f2d96099..b40244a941 100644
--- a/examples/l3fwd/meson.build
+++ b/examples/l3fwd/meson.build
@@ -6,12 +6,6 @@
# To build this example as a standalone application with an already-installed
# DPDK instance, use 'make'
-if arch_subdir == 'loongarch'
- build = false
- reason = 'not supported on LoongArch'
- subdir_done()
-endif
-
allow_experimental_apis = true
deps += ['acl', 'hash', 'lpm', 'fib', 'eventdev']
sources = files(
--
2.32.1 (Apple Git-133)
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v6 6/7] test/cpuflags: add test for LoongArch cpu flag
2022-08-27 8:59 [PATCH v6 0/7] Introduce support for LoongArch architecture Min Zhou
` (4 preceding siblings ...)
2022-08-27 8:59 ` [PATCH v6 5/7] examples/l3fwd: enable LoongArch operation Min Zhou
@ 2022-08-27 8:59 ` Min Zhou
2022-08-27 8:59 ` [PATCH v6 7/7] ci: add LOONGARCH64 cross compilation job Min Zhou
` (3 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Min Zhou @ 2022-08-27 8:59 UTC (permalink / raw)
To: david.marchand, thomas, bruce.richardson, anatoly.burakov,
qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev,
zhoumin
Cc: dev, maobibo
Add checks for all flag values defined in the LoongArch cpu
feature table.
Signed-off-by: Min Zhou <zhoumin@loongson.cn>
---
app/test/test_cpuflags.c | 41 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/app/test/test_cpuflags.c b/app/test/test_cpuflags.c
index 98a99c2c7d..a0e342ae48 100644
--- a/app/test/test_cpuflags.c
+++ b/app/test/test_cpuflags.c
@@ -281,6 +281,47 @@ test_cpuflags(void)
CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Z);
#endif
+#if defined(RTE_ARCH_LOONGARCH)
+ printf("Check for CPUCFG:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_CPUCFG);
+
+ printf("Check for LAM:\t\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_LAM);
+
+ printf("Check for UAL:\t\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_UAL);
+
+ printf("Check for FPU:\t\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_FPU);
+
+ printf("Check for LSX:\t\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_LSX);
+
+ printf("Check for LASX:\t\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_LASX);
+
+ printf("Check for CRC32:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_CRC32);
+
+ printf("Check for COMPLEX:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_COMPLEX);
+
+ printf("Check for CRYPTO:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_CRYPTO);
+
+ printf("Check for LVZ:\t\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_LVZ);
+
+ printf("Check for LBT_X86:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_LBT_X86);
+
+ printf("Check for LBT_ARM:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_LBT_ARM);
+
+ printf("Check for LBT_MIPS:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_LBT_MIPS);
+#endif
+
/*
* Check if invalid data is handled properly
*/
--
2.32.1 (Apple Git-133)
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v6 7/7] ci: add LOONGARCH64 cross compilation job
2022-08-27 8:59 [PATCH v6 0/7] Introduce support for LoongArch architecture Min Zhou
` (5 preceding siblings ...)
2022-08-27 8:59 ` [PATCH v6 6/7] test/cpuflags: add test for LoongArch cpu flag Min Zhou
@ 2022-08-27 8:59 ` Min Zhou
2022-09-01 0:09 ` [PATCH v6 0/7] Introduce support for LoongArch architecture zhoumin
` (2 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Min Zhou @ 2022-08-27 8:59 UTC (permalink / raw)
To: david.marchand, thomas, bruce.richardson, anatoly.burakov,
qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev,
zhoumin
Cc: dev, maobibo
Checks cross-compilation using Ubuntu 20.04 x86 for LoongArch.
Signed-off-by: Min Zhou <zhoumin@loongson.cn>
---
.ci/linux-build.sh | 10 ++++++++++
.github/workflows/build.yml | 10 +++++++++-
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/.ci/linux-build.sh b/.ci/linux-build.sh
index 06104eca22..256cf9c400 100755
--- a/.ci/linux-build.sh
+++ b/.ci/linux-build.sh
@@ -66,6 +66,16 @@ if [ "$AARCH64" = "true" ]; then
fi
fi
+if [ "$LOONGARCH64" = "true" ]; then
+ cross_tools_tar="/tmp/loongarch64-clfs-5.1-cross-tools-gcc-glibc.tar.xz"
+ cross_tools_dir="/tmp/loongarch64-cross-tools"
+ rm -rf $cross_tools_dir
+ mkdir $cross_tools_dir
+ tar -xf $cross_tools_tar -C $cross_tools_dir --strip-components 1
+ export PATH=$PATH:$cross_tools_dir/bin
+ cross_file=config/loongarch/loongarch_loongarch64_linux_gcc
+fi
+
if [ "$MINGW" = "true" ]; then
cross_file=config/x86/cross-mingw
fi
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index bf17d2b278..28c7906ecb 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -22,6 +22,7 @@ jobs:
CC: ccache ${{ matrix.config.compiler }}
DEF_LIB: ${{ matrix.config.library }}
LIBABIGAIL_VERSION: libabigail-1.8
+ LOONGARCH64: ${{ matrix.config.cross == 'loongarch64' }}
MINGW: ${{ matrix.config.cross == 'mingw' }}
MINI: ${{ matrix.config.mini != '' }}
PPC64LE: ${{ matrix.config.cross == 'ppc64le' }}
@@ -67,6 +68,10 @@ jobs:
compiler: gcc
library: shared
cross: aarch64
+ - os: ubuntu-20.04
+ compiler: gcc
+ library: shared
+ cross: loongarch64
- os: ubuntu-20.04
compiler: gcc
library: static
@@ -118,7 +123,7 @@ jobs:
run: sudo apt install -y ccache libnuma-dev python3-setuptools
python3-wheel python3-pip python3-pyelftools ninja-build libbsd-dev
libpcap-dev libibverbs-dev libcrypto++-dev libfdt-dev libjansson-dev
- libarchive-dev
+ libarchive-dev wget
- name: Install libabigail build dependencies if no cache is available
if: env.ABI_CHECKS == 'true' && steps.libabigail-cache.outputs.cache-hit != 'true'
run: sudo apt install -y autoconf automake libtool pkg-config libxml2-dev
@@ -138,6 +143,9 @@ jobs:
- name: Install riscv64 cross compiling packages
if: env.RISCV64 == 'true'
run: sudo apt install -y crossbuild-essential-riscv64
+ - name: Install loongarch64 cross compiling packages
+ if: env.LOONGARCH64 == 'true'
+ run: sudo wget -P /tmp/ https://github.com/loongson/build-tools/releases/download/2022.08.11/loongarch64-clfs-5.1-cross-tools-gcc-glibc.tar.xz
- name: Install test tools packages
if: env.AARCH64 != 'true' || env.PPC64LE != 'true' || env.RISCV64 != 'true' || env.RUN_TESTS == 'true'
run: sudo apt install -y gdb jq
--
2.32.1 (Apple Git-133)
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v6 0/7] Introduce support for LoongArch architecture
2022-08-27 8:59 [PATCH v6 0/7] Introduce support for LoongArch architecture Min Zhou
` (6 preceding siblings ...)
2022-08-27 8:59 ` [PATCH v6 7/7] ci: add LOONGARCH64 cross compilation job Min Zhou
@ 2022-09-01 0:09 ` zhoumin
2022-09-06 1:30 ` maobibo
2022-09-09 9:08 ` zhoumin
2022-09-20 3:01 ` zhoumin
9 siblings, 1 reply; 12+ messages in thread
From: zhoumin @ 2022-09-01 0:09 UTC (permalink / raw)
To: david.marchand, thomas, bruce.richardson, anatoly.burakov,
qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev
Cc: dev, maobibo
Sincerely ping.
On Sat, 27 Aug, 2022 at 16:59 +0800, Min Zhou wrote:
> Dear team,
>
> The following patch set is intended to support DPDK running on LoongArch
> architecture.
>
> LoongArch is the general processor architecture of Loongson Corporation
> and is a new RISC ISA, which is a bit like MIPS or RISC-V.
>
> The online documents of LoongArch architecture are here:
> https://loongson.github.io/LoongArch-Documentation/README-EN.html
>
> The latest build tools for LoongArch (binary) can be downloaded from:
> https://github.com/loongson/build-tools
>
> v6:
> - place some blocks for LoongArch in a pseudo alphabetical order
> - remove some macros not used
> - update release notes in the correct format
> - remove some headers for LoongArch, including msclock, pflock and
> ticketlock, which are now non-arch specific
> - rename some helpers to make them more readable
> - remove some copied comments
> - force-set RTE_FORCE_INTRINSICS in config and remove non-arch
> specific implementations
> - fix format errors in meson file reported by check-meson.py
> - rebase the patchset on the main repository
>
> v5:
> - merge all patches for supporting LoongArch EAL into one patch
> - add LoongArch cross compilation document and update some documents
> related to architecture
> - remove vector stubs added for LoongArch in net/i40e and net/ixgbe
> - add LOONGARCH64 cross compilation job in github ci
>
> v4:
> - rebase the patchset on the main repository of version 22.07.0
>
> v3:
> - add URL for cross compile tool chain
> - remove rte_lpm_lsx.h which was a dummy vector implementation
> because there is already a scalar implementation, thanks to
> Michal Mazurek
> - modify the name of compiler for cross compiling
> - remove useless variable in meson.build
>
> v2:
> - use standard atomics of toolchain to implement
> atomic operations
> - implement spinlock based on standard atomics
>
> *** BLURB HERE ***
>
> Min Zhou (7):
> eal/loongarch: support LoongArch architecture
> net/ixgbe: add vector stubs for LoongArch
> net/memif: set memfd syscall ID on LoongArch
> net/tap: set BPF syscall ID for LoongArch
> examples/l3fwd: enable LoongArch operation
> test/cpuflags: add test for LoongArch cpu flag
> ci: add LOONGARCH64 cross compilation job
>
> .ci/linux-build.sh | 10 ++
> .github/workflows/build.yml | 10 +-
> MAINTAINERS | 6 ++
> app/test/test_cpuflags.c | 41 ++++++++
> app/test/test_xmmt_ops.h | 12 +++
> .../loongarch/loongarch_loongarch64_linux_gcc | 16 ++++
> config/loongarch/meson.build | 43 +++++++++
> doc/guides/contributing/design.rst | 2 +-
> .../cross_build_dpdk_for_loongarch.rst | 87 +++++++++++++++++
> doc/guides/linux_gsg/index.rst | 1 +
> doc/guides/nics/features.rst | 8 ++
> doc/guides/nics/features/default.ini | 1 +
> doc/guides/nics/features/ixgbe.ini | 1 +
> doc/guides/rel_notes/release_22_11.rst | 7 ++
> drivers/net/i40e/meson.build | 6 ++
> drivers/net/ixgbe/ixgbe_rxtx.c | 7 +-
> drivers/net/memif/rte_eth_memif.h | 2 +
> drivers/net/tap/tap_bpf.h | 2 +
> examples/l3fwd/l3fwd_em.c | 8 ++
> lib/eal/linux/eal_memory.c | 4 +
> lib/eal/loongarch/include/meson.build | 18 ++++
> lib/eal/loongarch/include/rte_atomic.h | 47 ++++++++++
> lib/eal/loongarch/include/rte_byteorder.h | 40 ++++++++
> lib/eal/loongarch/include/rte_cpuflags.h | 39 ++++++++
> lib/eal/loongarch/include/rte_cycles.h | 47 ++++++++++
> lib/eal/loongarch/include/rte_io.h | 18 ++++
> lib/eal/loongarch/include/rte_memcpy.h | 61 ++++++++++++
> lib/eal/loongarch/include/rte_pause.h | 24 +++++
> .../loongarch/include/rte_power_intrinsics.h | 20 ++++
> lib/eal/loongarch/include/rte_prefetch.h | 47 ++++++++++
> lib/eal/loongarch/include/rte_rwlock.h | 42 +++++++++
> lib/eal/loongarch/include/rte_spinlock.h | 64 +++++++++++++
> lib/eal/loongarch/include/rte_vect.h | 65 +++++++++++++
> lib/eal/loongarch/meson.build | 11 +++
> lib/eal/loongarch/rte_cpuflags.c | 93 +++++++++++++++++++
> lib/eal/loongarch/rte_cycles.c | 45 +++++++++
> lib/eal/loongarch/rte_hypervisor.c | 11 +++
> lib/eal/loongarch/rte_power_intrinsics.c | 51 ++++++++++
> meson.build | 2 +
> 39 files changed, 1015 insertions(+), 4 deletions(-)
> create mode 100644 config/loongarch/loongarch_loongarch64_linux_gcc
> create mode 100644 config/loongarch/meson.build
> create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst
> create mode 100644 lib/eal/loongarch/include/meson.build
> create mode 100644 lib/eal/loongarch/include/rte_atomic.h
> create mode 100644 lib/eal/loongarch/include/rte_byteorder.h
> create mode 100644 lib/eal/loongarch/include/rte_cpuflags.h
> create mode 100644 lib/eal/loongarch/include/rte_cycles.h
> create mode 100644 lib/eal/loongarch/include/rte_io.h
> create mode 100644 lib/eal/loongarch/include/rte_memcpy.h
> create mode 100644 lib/eal/loongarch/include/rte_pause.h
> create mode 100644 lib/eal/loongarch/include/rte_power_intrinsics.h
> create mode 100644 lib/eal/loongarch/include/rte_prefetch.h
> create mode 100644 lib/eal/loongarch/include/rte_rwlock.h
> create mode 100644 lib/eal/loongarch/include/rte_spinlock.h
> create mode 100644 lib/eal/loongarch/include/rte_vect.h
> create mode 100644 lib/eal/loongarch/meson.build
> create mode 100644 lib/eal/loongarch/rte_cpuflags.c
> create mode 100644 lib/eal/loongarch/rte_cycles.c
> create mode 100644 lib/eal/loongarch/rte_hypervisor.c
> create mode 100644 lib/eal/loongarch/rte_power_intrinsics.c
>
--
Thanks,
Min Zhou
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v6 0/7] Introduce support for LoongArch architecture
2022-09-01 0:09 ` [PATCH v6 0/7] Introduce support for LoongArch architecture zhoumin
@ 2022-09-06 1:30 ` maobibo
0 siblings, 0 replies; 12+ messages in thread
From: maobibo @ 2022-09-06 1:30 UTC (permalink / raw)
To: zhoumin, david.marchand, thomas, bruce.richardson,
anatoly.burakov, qiming.yang, Yuying.Zhang, jgrajcia,
konstantin.v.ananyev
Cc: dev
kindly ping, any comments is welcome.
Now linux kernel/gcc/binutils mainline branches have add support for Loongarch.
only there is no popular OS distribution.
regards
bibo,mao
在 2022/9/1 08:09, zhoumin 写道:
> Sincerely ping.
>
>
> On Sat, 27 Aug, 2022 at 16:59 +0800, Min Zhou wrote:
>> Dear team,
>>
>> The following patch set is intended to support DPDK running on LoongArch
>> architecture.
>>
>> LoongArch is the general processor architecture of Loongson Corporation
>> and is a new RISC ISA, which is a bit like MIPS or RISC-V.
>>
>> The online documents of LoongArch architecture are here:
>> https://loongson.github.io/LoongArch-Documentation/README-EN.html
>>
>> The latest build tools for LoongArch (binary) can be downloaded from:
>> https://github.com/loongson/build-tools
>>
>> v6:
>> - place some blocks for LoongArch in a pseudo alphabetical order
>> - remove some macros not used
>> - update release notes in the correct format
>> - remove some headers for LoongArch, including msclock, pflock and
>> ticketlock, which are now non-arch specific
>> - rename some helpers to make them more readable
>> - remove some copied comments
>> - force-set RTE_FORCE_INTRINSICS in config and remove non-arch
>> specific implementations
>> - fix format errors in meson file reported by check-meson.py
>> - rebase the patchset on the main repository
>>
>> v5:
>> - merge all patches for supporting LoongArch EAL into one patch
>> - add LoongArch cross compilation document and update some documents
>> related to architecture
>> - remove vector stubs added for LoongArch in net/i40e and net/ixgbe
>> - add LOONGARCH64 cross compilation job in github ci
>>
>> v4:
>> - rebase the patchset on the main repository of version 22.07.0
>>
>> v3:
>> - add URL for cross compile tool chain
>> - remove rte_lpm_lsx.h which was a dummy vector implementation
>> because there is already a scalar implementation, thanks to
>> Michal Mazurek
>> - modify the name of compiler for cross compiling
>> - remove useless variable in meson.build
>>
>> v2:
>> - use standard atomics of toolchain to implement
>> atomic operations
>> - implement spinlock based on standard atomics
>>
>> *** BLURB HERE ***
>>
>> Min Zhou (7):
>> eal/loongarch: support LoongArch architecture
>> net/ixgbe: add vector stubs for LoongArch
>> net/memif: set memfd syscall ID on LoongArch
>> net/tap: set BPF syscall ID for LoongArch
>> examples/l3fwd: enable LoongArch operation
>> test/cpuflags: add test for LoongArch cpu flag
>> ci: add LOONGARCH64 cross compilation job
>>
>> .ci/linux-build.sh | 10 ++
>> .github/workflows/build.yml | 10 +-
>> MAINTAINERS | 6 ++
>> app/test/test_cpuflags.c | 41 ++++++++
>> app/test/test_xmmt_ops.h | 12 +++
>> .../loongarch/loongarch_loongarch64_linux_gcc | 16 ++++
>> config/loongarch/meson.build | 43 +++++++++
>> doc/guides/contributing/design.rst | 2 +-
>> .../cross_build_dpdk_for_loongarch.rst | 87 +++++++++++++++++
>> doc/guides/linux_gsg/index.rst | 1 +
>> doc/guides/nics/features.rst | 8 ++
>> doc/guides/nics/features/default.ini | 1 +
>> doc/guides/nics/features/ixgbe.ini | 1 +
>> doc/guides/rel_notes/release_22_11.rst | 7 ++
>> drivers/net/i40e/meson.build | 6 ++
>> drivers/net/ixgbe/ixgbe_rxtx.c | 7 +-
>> drivers/net/memif/rte_eth_memif.h | 2 +
>> drivers/net/tap/tap_bpf.h | 2 +
>> examples/l3fwd/l3fwd_em.c | 8 ++
>> lib/eal/linux/eal_memory.c | 4 +
>> lib/eal/loongarch/include/meson.build | 18 ++++
>> lib/eal/loongarch/include/rte_atomic.h | 47 ++++++++++
>> lib/eal/loongarch/include/rte_byteorder.h | 40 ++++++++
>> lib/eal/loongarch/include/rte_cpuflags.h | 39 ++++++++
>> lib/eal/loongarch/include/rte_cycles.h | 47 ++++++++++
>> lib/eal/loongarch/include/rte_io.h | 18 ++++
>> lib/eal/loongarch/include/rte_memcpy.h | 61 ++++++++++++
>> lib/eal/loongarch/include/rte_pause.h | 24 +++++
>> .../loongarch/include/rte_power_intrinsics.h | 20 ++++
>> lib/eal/loongarch/include/rte_prefetch.h | 47 ++++++++++
>> lib/eal/loongarch/include/rte_rwlock.h | 42 +++++++++
>> lib/eal/loongarch/include/rte_spinlock.h | 64 +++++++++++++
>> lib/eal/loongarch/include/rte_vect.h | 65 +++++++++++++
>> lib/eal/loongarch/meson.build | 11 +++
>> lib/eal/loongarch/rte_cpuflags.c | 93 +++++++++++++++++++
>> lib/eal/loongarch/rte_cycles.c | 45 +++++++++
>> lib/eal/loongarch/rte_hypervisor.c | 11 +++
>> lib/eal/loongarch/rte_power_intrinsics.c | 51 ++++++++++
>> meson.build | 2 +
>> 39 files changed, 1015 insertions(+), 4 deletions(-)
>> create mode 100644 config/loongarch/loongarch_loongarch64_linux_gcc
>> create mode 100644 config/loongarch/meson.build
>> create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst
>> create mode 100644 lib/eal/loongarch/include/meson.build
>> create mode 100644 lib/eal/loongarch/include/rte_atomic.h
>> create mode 100644 lib/eal/loongarch/include/rte_byteorder.h
>> create mode 100644 lib/eal/loongarch/include/rte_cpuflags.h
>> create mode 100644 lib/eal/loongarch/include/rte_cycles.h
>> create mode 100644 lib/eal/loongarch/include/rte_io.h
>> create mode 100644 lib/eal/loongarch/include/rte_memcpy.h
>> create mode 100644 lib/eal/loongarch/include/rte_pause.h
>> create mode 100644 lib/eal/loongarch/include/rte_power_intrinsics.h
>> create mode 100644 lib/eal/loongarch/include/rte_prefetch.h
>> create mode 100644 lib/eal/loongarch/include/rte_rwlock.h
>> create mode 100644 lib/eal/loongarch/include/rte_spinlock.h
>> create mode 100644 lib/eal/loongarch/include/rte_vect.h
>> create mode 100644 lib/eal/loongarch/meson.build
>> create mode 100644 lib/eal/loongarch/rte_cpuflags.c
>> create mode 100644 lib/eal/loongarch/rte_cycles.c
>> create mode 100644 lib/eal/loongarch/rte_hypervisor.c
>> create mode 100644 lib/eal/loongarch/rte_power_intrinsics.c
>>
>
> --
> Thanks,
> Min Zhou
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v6 0/7] Introduce support for LoongArch architecture
2022-08-27 8:59 [PATCH v6 0/7] Introduce support for LoongArch architecture Min Zhou
` (7 preceding siblings ...)
2022-09-01 0:09 ` [PATCH v6 0/7] Introduce support for LoongArch architecture zhoumin
@ 2022-09-09 9:08 ` zhoumin
2022-09-20 3:01 ` zhoumin
9 siblings, 0 replies; 12+ messages in thread
From: zhoumin @ 2022-09-09 9:08 UTC (permalink / raw)
To: david.marchand, thomas, bruce.richardson, anatoly.burakov,
qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev
Cc: dev, maobibo
Kindly ping.
Any feedback is appreciated.
On 2022年08月27日 16:59, Min Zhou wrote:
> Dear team,
>
> The following patch set is intended to support DPDK running on LoongArch
> architecture.
>
> LoongArch is the general processor architecture of Loongson Corporation
> and is a new RISC ISA, which is a bit like MIPS or RISC-V.
>
> The online documents of LoongArch architecture are here:
> https://loongson.github.io/LoongArch-Documentation/README-EN.html
>
> The latest build tools for LoongArch (binary) can be downloaded from:
> https://github.com/loongson/build-tools
>
> v6:
> - place some blocks for LoongArch in a pseudo alphabetical order
> - remove some macros not used
> - update release notes in the correct format
> - remove some headers for LoongArch, including msclock, pflock and
> ticketlock, which are now non-arch specific
> - rename some helpers to make them more readable
> - remove some copied comments
> - force-set RTE_FORCE_INTRINSICS in config and remove non-arch
> specific implementations
> - fix format errors in meson file reported by check-meson.py
> - rebase the patchset on the main repository
>
> v5:
> - merge all patches for supporting LoongArch EAL into one patch
> - add LoongArch cross compilation document and update some documents
> related to architecture
> - remove vector stubs added for LoongArch in net/i40e and net/ixgbe
> - add LOONGARCH64 cross compilation job in github ci
>
> v4:
> - rebase the patchset on the main repository of version 22.07.0
>
> v3:
> - add URL for cross compile tool chain
> - remove rte_lpm_lsx.h which was a dummy vector implementation
> because there is already a scalar implementation, thanks to
> Michal Mazurek
> - modify the name of compiler for cross compiling
> - remove useless variable in meson.build
>
> v2:
> - use standard atomics of toolchain to implement
> atomic operations
> - implement spinlock based on standard atomics
>
> *** BLURB HERE ***
>
> Min Zhou (7):
> eal/loongarch: support LoongArch architecture
> net/ixgbe: add vector stubs for LoongArch
> net/memif: set memfd syscall ID on LoongArch
> net/tap: set BPF syscall ID for LoongArch
> examples/l3fwd: enable LoongArch operation
> test/cpuflags: add test for LoongArch cpu flag
> ci: add LOONGARCH64 cross compilation job
>
> .ci/linux-build.sh | 10 ++
> .github/workflows/build.yml | 10 +-
> MAINTAINERS | 6 ++
> app/test/test_cpuflags.c | 41 ++++++++
> app/test/test_xmmt_ops.h | 12 +++
> .../loongarch/loongarch_loongarch64_linux_gcc | 16 ++++
> config/loongarch/meson.build | 43 +++++++++
> doc/guides/contributing/design.rst | 2 +-
> .../cross_build_dpdk_for_loongarch.rst | 87 +++++++++++++++++
> doc/guides/linux_gsg/index.rst | 1 +
> doc/guides/nics/features.rst | 8 ++
> doc/guides/nics/features/default.ini | 1 +
> doc/guides/nics/features/ixgbe.ini | 1 +
> doc/guides/rel_notes/release_22_11.rst | 7 ++
> drivers/net/i40e/meson.build | 6 ++
> drivers/net/ixgbe/ixgbe_rxtx.c | 7 +-
> drivers/net/memif/rte_eth_memif.h | 2 +
> drivers/net/tap/tap_bpf.h | 2 +
> examples/l3fwd/l3fwd_em.c | 8 ++
> lib/eal/linux/eal_memory.c | 4 +
> lib/eal/loongarch/include/meson.build | 18 ++++
> lib/eal/loongarch/include/rte_atomic.h | 47 ++++++++++
> lib/eal/loongarch/include/rte_byteorder.h | 40 ++++++++
> lib/eal/loongarch/include/rte_cpuflags.h | 39 ++++++++
> lib/eal/loongarch/include/rte_cycles.h | 47 ++++++++++
> lib/eal/loongarch/include/rte_io.h | 18 ++++
> lib/eal/loongarch/include/rte_memcpy.h | 61 ++++++++++++
> lib/eal/loongarch/include/rte_pause.h | 24 +++++
> .../loongarch/include/rte_power_intrinsics.h | 20 ++++
> lib/eal/loongarch/include/rte_prefetch.h | 47 ++++++++++
> lib/eal/loongarch/include/rte_rwlock.h | 42 +++++++++
> lib/eal/loongarch/include/rte_spinlock.h | 64 +++++++++++++
> lib/eal/loongarch/include/rte_vect.h | 65 +++++++++++++
> lib/eal/loongarch/meson.build | 11 +++
> lib/eal/loongarch/rte_cpuflags.c | 93 +++++++++++++++++++
> lib/eal/loongarch/rte_cycles.c | 45 +++++++++
> lib/eal/loongarch/rte_hypervisor.c | 11 +++
> lib/eal/loongarch/rte_power_intrinsics.c | 51 ++++++++++
> meson.build | 2 +
> 39 files changed, 1015 insertions(+), 4 deletions(-)
> create mode 100644 config/loongarch/loongarch_loongarch64_linux_gcc
> create mode 100644 config/loongarch/meson.build
> create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst
> create mode 100644 lib/eal/loongarch/include/meson.build
> create mode 100644 lib/eal/loongarch/include/rte_atomic.h
> create mode 100644 lib/eal/loongarch/include/rte_byteorder.h
> create mode 100644 lib/eal/loongarch/include/rte_cpuflags.h
> create mode 100644 lib/eal/loongarch/include/rte_cycles.h
> create mode 100644 lib/eal/loongarch/include/rte_io.h
> create mode 100644 lib/eal/loongarch/include/rte_memcpy.h
> create mode 100644 lib/eal/loongarch/include/rte_pause.h
> create mode 100644 lib/eal/loongarch/include/rte_power_intrinsics.h
> create mode 100644 lib/eal/loongarch/include/rte_prefetch.h
> create mode 100644 lib/eal/loongarch/include/rte_rwlock.h
> create mode 100644 lib/eal/loongarch/include/rte_spinlock.h
> create mode 100644 lib/eal/loongarch/include/rte_vect.h
> create mode 100644 lib/eal/loongarch/meson.build
> create mode 100644 lib/eal/loongarch/rte_cpuflags.c
> create mode 100644 lib/eal/loongarch/rte_cycles.c
> create mode 100644 lib/eal/loongarch/rte_hypervisor.c
> create mode 100644 lib/eal/loongarch/rte_power_intrinsics.c
>
--
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v6 0/7] Introduce support for LoongArch architecture
2022-08-27 8:59 [PATCH v6 0/7] Introduce support for LoongArch architecture Min Zhou
` (8 preceding siblings ...)
2022-09-09 9:08 ` zhoumin
@ 2022-09-20 3:01 ` zhoumin
9 siblings, 0 replies; 12+ messages in thread
From: zhoumin @ 2022-09-20 3:01 UTC (permalink / raw)
To: david.marchand, thomas, bruce.richardson, anatoly.burakov,
qiming.yang, Yuying.Zhang, jgrajcia, konstantin.v.ananyev
Cc: dev, maobibo
Kindly ping.
Could anyone give some feedback? Thanks.
On 2022年08月27日 16:59, Min Zhou wrote:
> Dear team,
>
> The following patch set is intended to support DPDK running on LoongArch
> architecture.
>
> LoongArch is the general processor architecture of Loongson Corporation
> and is a new RISC ISA, which is a bit like MIPS or RISC-V.
>
> The online documents of LoongArch architecture are here:
> https://loongson.github.io/LoongArch-Documentation/README-EN.html
>
> The latest build tools for LoongArch (binary) can be downloaded from:
> https://github.com/loongson/build-tools
>
> v6:
> - place some blocks for LoongArch in a pseudo alphabetical order
> - remove some macros not used
> - update release notes in the correct format
> - remove some headers for LoongArch, including msclock, pflock and
> ticketlock, which are now non-arch specific
> - rename some helpers to make them more readable
> - remove some copied comments
> - force-set RTE_FORCE_INTRINSICS in config and remove non-arch
> specific implementations
> - fix format errors in meson file reported by check-meson.py
> - rebase the patchset on the main repository
>
> v5:
> - merge all patches for supporting LoongArch EAL into one patch
> - add LoongArch cross compilation document and update some documents
> related to architecture
> - remove vector stubs added for LoongArch in net/i40e and net/ixgbe
> - add LOONGARCH64 cross compilation job in github ci
>
> v4:
> - rebase the patchset on the main repository of version 22.07.0
>
> v3:
> - add URL for cross compile tool chain
> - remove rte_lpm_lsx.h which was a dummy vector implementation
> because there is already a scalar implementation, thanks to
> Michal Mazurek
> - modify the name of compiler for cross compiling
> - remove useless variable in meson.build
>
> v2:
> - use standard atomics of toolchain to implement
> atomic operations
> - implement spinlock based on standard atomics
>
> *** BLURB HERE ***
>
> Min Zhou (7):
> eal/loongarch: support LoongArch architecture
> net/ixgbe: add vector stubs for LoongArch
> net/memif: set memfd syscall ID on LoongArch
> net/tap: set BPF syscall ID for LoongArch
> examples/l3fwd: enable LoongArch operation
> test/cpuflags: add test for LoongArch cpu flag
> ci: add LOONGARCH64 cross compilation job
>
> .ci/linux-build.sh | 10 ++
> .github/workflows/build.yml | 10 +-
> MAINTAINERS | 6 ++
> app/test/test_cpuflags.c | 41 ++++++++
> app/test/test_xmmt_ops.h | 12 +++
> .../loongarch/loongarch_loongarch64_linux_gcc | 16 ++++
> config/loongarch/meson.build | 43 +++++++++
> doc/guides/contributing/design.rst | 2 +-
> .../cross_build_dpdk_for_loongarch.rst | 87 +++++++++++++++++
> doc/guides/linux_gsg/index.rst | 1 +
> doc/guides/nics/features.rst | 8 ++
> doc/guides/nics/features/default.ini | 1 +
> doc/guides/nics/features/ixgbe.ini | 1 +
> doc/guides/rel_notes/release_22_11.rst | 7 ++
> drivers/net/i40e/meson.build | 6 ++
> drivers/net/ixgbe/ixgbe_rxtx.c | 7 +-
> drivers/net/memif/rte_eth_memif.h | 2 +
> drivers/net/tap/tap_bpf.h | 2 +
> examples/l3fwd/l3fwd_em.c | 8 ++
> lib/eal/linux/eal_memory.c | 4 +
> lib/eal/loongarch/include/meson.build | 18 ++++
> lib/eal/loongarch/include/rte_atomic.h | 47 ++++++++++
> lib/eal/loongarch/include/rte_byteorder.h | 40 ++++++++
> lib/eal/loongarch/include/rte_cpuflags.h | 39 ++++++++
> lib/eal/loongarch/include/rte_cycles.h | 47 ++++++++++
> lib/eal/loongarch/include/rte_io.h | 18 ++++
> lib/eal/loongarch/include/rte_memcpy.h | 61 ++++++++++++
> lib/eal/loongarch/include/rte_pause.h | 24 +++++
> .../loongarch/include/rte_power_intrinsics.h | 20 ++++
> lib/eal/loongarch/include/rte_prefetch.h | 47 ++++++++++
> lib/eal/loongarch/include/rte_rwlock.h | 42 +++++++++
> lib/eal/loongarch/include/rte_spinlock.h | 64 +++++++++++++
> lib/eal/loongarch/include/rte_vect.h | 65 +++++++++++++
> lib/eal/loongarch/meson.build | 11 +++
> lib/eal/loongarch/rte_cpuflags.c | 93 +++++++++++++++++++
> lib/eal/loongarch/rte_cycles.c | 45 +++++++++
> lib/eal/loongarch/rte_hypervisor.c | 11 +++
> lib/eal/loongarch/rte_power_intrinsics.c | 51 ++++++++++
> meson.build | 2 +
> 39 files changed, 1015 insertions(+), 4 deletions(-)
> create mode 100644 config/loongarch/loongarch_loongarch64_linux_gcc
> create mode 100644 config/loongarch/meson.build
> create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst
> create mode 100644 lib/eal/loongarch/include/meson.build
> create mode 100644 lib/eal/loongarch/include/rte_atomic.h
> create mode 100644 lib/eal/loongarch/include/rte_byteorder.h
> create mode 100644 lib/eal/loongarch/include/rte_cpuflags.h
> create mode 100644 lib/eal/loongarch/include/rte_cycles.h
> create mode 100644 lib/eal/loongarch/include/rte_io.h
> create mode 100644 lib/eal/loongarch/include/rte_memcpy.h
> create mode 100644 lib/eal/loongarch/include/rte_pause.h
> create mode 100644 lib/eal/loongarch/include/rte_power_intrinsics.h
> create mode 100644 lib/eal/loongarch/include/rte_prefetch.h
> create mode 100644 lib/eal/loongarch/include/rte_rwlock.h
> create mode 100644 lib/eal/loongarch/include/rte_spinlock.h
> create mode 100644 lib/eal/loongarch/include/rte_vect.h
> create mode 100644 lib/eal/loongarch/meson.build
> create mode 100644 lib/eal/loongarch/rte_cpuflags.c
> create mode 100644 lib/eal/loongarch/rte_cycles.c
> create mode 100644 lib/eal/loongarch/rte_hypervisor.c
> create mode 100644 lib/eal/loongarch/rte_power_intrinsics.c
>
--
Thanks,
Min Zhou
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2022-09-20 3:01 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-08-27 8:59 [PATCH v6 0/7] Introduce support for LoongArch architecture Min Zhou
2022-08-27 8:59 ` [PATCH v6 1/7] eal/loongarch: support " Min Zhou
2022-08-27 8:59 ` [PATCH v6 2/7] net/ixgbe: add vector stubs for LoongArch Min Zhou
2022-08-27 8:59 ` [PATCH v6 3/7] net/memif: set memfd syscall ID on LoongArch Min Zhou
2022-08-27 8:59 ` [PATCH v6 4/7] net/tap: set BPF syscall ID for LoongArch Min Zhou
2022-08-27 8:59 ` [PATCH v6 5/7] examples/l3fwd: enable LoongArch operation Min Zhou
2022-08-27 8:59 ` [PATCH v6 6/7] test/cpuflags: add test for LoongArch cpu flag Min Zhou
2022-08-27 8:59 ` [PATCH v6 7/7] ci: add LOONGARCH64 cross compilation job Min Zhou
2022-09-01 0:09 ` [PATCH v6 0/7] Introduce support for LoongArch architecture zhoumin
2022-09-06 1:30 ` maobibo
2022-09-09 9:08 ` zhoumin
2022-09-20 3:01 ` zhoumin
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