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From: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
To: dev@dpdk.org
Cc: Nirranjan Kirubaharan <nirranjan@chelsio.com>,
	Indranil Choudhury <indranil@chelsio.com>,
	Kumar Sanghvi <kumaras@chelsio.com>,
	Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Subject: [dpdk-dev] [PATCH 06/13] cxgbe: add forward error correction support
Date: Sat, 27 May 2017 09:16:21 +0530	[thread overview]
Message-ID: <edb496b671a0e67508c4f54763f4f73376a38b85.1495856462.git.rahul.lakkireddy@chelsio.com> (raw)
In-Reply-To: <cover.1495856462.git.rahul.lakkireddy@chelsio.com>
In-Reply-To: <cover.1495856462.git.rahul.lakkireddy@chelsio.com>

Add forward error correction (FEC) support and update link
configuration.

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
---
 drivers/net/cxgbe/base/common.h         |  8 +++++
 drivers/net/cxgbe/base/t4_hw.c          | 57 ++++++++++++++++++++++++++-------
 drivers/net/cxgbe/base/t4fw_interface.h |  6 ++--
 3 files changed, 56 insertions(+), 15 deletions(-)

diff --git a/drivers/net/cxgbe/base/common.h b/drivers/net/cxgbe/base/common.h
index 73ec057..5db4ca8 100644
--- a/drivers/net/cxgbe/base/common.h
+++ b/drivers/net/cxgbe/base/common.h
@@ -68,6 +68,12 @@ enum {
 	PAUSE_AUTONEG = 1 << 2
 };
 
+enum {
+	FEC_RS        = 1 << 0,
+	FEC_BASER_RS  = 1 << 1,
+	FEC_RESERVED  = 1 << 2,
+};
+
 struct port_stats {
 	u64 tx_octets;            /* total # of octets in good frames */
 	u64 tx_frames;            /* all good frames */
@@ -235,6 +241,8 @@ struct link_config {
 	unsigned int   speed;            /* actual link speed */
 	unsigned char  requested_fc;     /* flow control user has requested */
 	unsigned char  fc;               /* actual link flow control */
+	unsigned char  requested_fec;    /* Forward Error Correction user */
+	unsigned char  fec;              /* has requested and actual FEC */
 	unsigned char  autoneg;          /* autonegotiating? */
 	unsigned char  link_ok;          /* link up? */
 };
diff --git a/drivers/net/cxgbe/base/t4_hw.c b/drivers/net/cxgbe/base/t4_hw.c
index 05bf1e8..053a2cd 100644
--- a/drivers/net/cxgbe/base/t4_hw.c
+++ b/drivers/net/cxgbe/base/t4_hw.c
@@ -57,7 +57,8 @@
 #include "t4_regs_values.h"
 #include "t4fw_interface.h"
 
-static void init_link_config(struct link_config *lc, unsigned int caps);
+static void init_link_config(struct link_config *lc, unsigned int pcaps,
+			     unsigned int acaps);
 
 /**
  * t4_read_mtu_tbl - returns the values in the HW path MTU table
@@ -2542,14 +2543,24 @@ int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
 		  struct link_config *lc)
 {
 	struct fw_port_cmd c;
-	unsigned int fc = 0, mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO);
+	unsigned int mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO);
+	unsigned int fc, fec;
 
 	lc->link_ok = 0;
+	fc = 0;
 	if (lc->requested_fc & PAUSE_RX)
 		fc |= FW_PORT_CAP_FC_RX;
 	if (lc->requested_fc & PAUSE_TX)
 		fc |= FW_PORT_CAP_FC_TX;
 
+	fec = 0;
+	if (lc->requested_fec & FEC_RS)
+		fec |= FW_PORT_CAP_FEC_RS;
+	if (lc->requested_fec & FEC_BASER_RS)
+		fec |= FW_PORT_CAP_FEC_BASER_RS;
+	if (lc->requested_fec & FEC_RESERVED)
+		fec |= FW_PORT_CAP_FEC_RESERVED;
+
 	memset(&c, 0, sizeof(c));
 	c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
 				     F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
@@ -2560,13 +2571,16 @@ int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
 
 	if (!(lc->supported & FW_PORT_CAP_ANEG)) {
 		c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
-					     fc);
-		lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
+					     fc | fec);
+		lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
+		lc->fec = lc->requested_fec;
 	} else if (lc->autoneg == AUTONEG_DISABLE) {
-		c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi);
-		lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
+		c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc |
+					     fec | mdi);
+		lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
+		lc->fec = lc->requested_fec;
 	} else {
-		c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi);
+		c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | fec | mdi);
 	}
 
 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
@@ -3831,19 +3845,37 @@ void t4_reset_link_config(struct adapter *adap, int idx)
 /**
  * init_link_config - initialize a link's SW state
  * @lc: structure holding the link state
- * @caps: link capabilities
+ * @pcaps: link Port Capabilities
+ * @acaps: link current Advertised Port Capabilities
  *
  * Initializes the SW state maintained for each link, including the link's
  * capabilities and default speed/flow-control/autonegotiation settings.
  */
-static void init_link_config(struct link_config *lc,
-			     unsigned int caps)
+static void init_link_config(struct link_config *lc, unsigned int pcaps,
+			     unsigned int acaps)
 {
-	lc->supported = caps;
+	unsigned int fec;
+
+	lc->supported = pcaps;
 	lc->requested_speed = 0;
 	lc->speed = 0;
 	lc->requested_fc = 0;
 	lc->fc = 0;
+
+	/**
+	 * For Forward Error Control, we default to whatever the Firmware
+	 * tells us the Link is currently advertising.
+	 */
+	fec = 0;
+	if (acaps & FW_PORT_CAP_FEC_RS)
+		fec |= FEC_RS;
+	if (acaps & FW_PORT_CAP_FEC_BASER_RS)
+		fec |= FEC_BASER_RS;
+	if (acaps & FW_PORT_CAP_FEC_RESERVED)
+		fec |= FEC_RESERVED;
+	lc->requested_fec = fec;
+	lc->fec = fec;
+
 	if (lc->supported & FW_PORT_CAP_ANEG) {
 		lc->advertising = lc->supported & ADVERT_MASK;
 		lc->autoneg = AUTONEG_ENABLE;
@@ -4399,7 +4431,8 @@ int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
 		p->port_type = G_FW_PORT_CMD_PTYPE(ret);
 		p->mod_type = FW_PORT_MOD_TYPE_NA;
 
-		init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap));
+		init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap),
+				 be16_to_cpu(c.u.info.acap));
 		j++;
 	}
 	return 0;
diff --git a/drivers/net/cxgbe/base/t4fw_interface.h b/drivers/net/cxgbe/base/t4fw_interface.h
index 43e8c0a..fcc61bf 100644
--- a/drivers/net/cxgbe/base/t4fw_interface.h
+++ b/drivers/net/cxgbe/base/t4fw_interface.h
@@ -1070,9 +1070,9 @@ enum fw_port_cap {
 	FW_PORT_CAP_ANEG		= 0x0100,
 	FW_PORT_CAP_MDIX		= 0x0200,
 	FW_PORT_CAP_MDIAUTO		= 0x0400,
-	FW_PORT_CAP_FEC			= 0x0800,
-	FW_PORT_CAP_TECHKR		= 0x1000,
-	FW_PORT_CAP_TECHKX4		= 0x2000,
+	FW_PORT_CAP_FEC_RS              = 0x0800,
+	FW_PORT_CAP_FEC_BASER_RS        = 0x1000,
+	FW_PORT_CAP_FEC_RESERVED        = 0x2000,
 	FW_PORT_CAP_802_3_PAUSE		= 0x4000,
 	FW_PORT_CAP_802_3_ASM_DIR	= 0x8000,
 };
-- 
2.5.3

  parent reply	other threads:[~2017-05-27  5:46 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-05-27  3:46 [dpdk-dev] [PATCH 00/13] cxgbe: add support for Chelsio T6 family of adapters Rahul Lakkireddy
2017-05-27  3:46 ` [dpdk-dev] [PATCH 01/13] cxgbe: add support to run Chelsio T6 cards Rahul Lakkireddy
2017-05-30 10:34   ` Ferruh Yigit
2017-05-27  3:46 ` [dpdk-dev] [PATCH 02/13] cxgbe: update register dump Rahul Lakkireddy
2017-05-27  3:46 ` [dpdk-dev] [PATCH 03/13] cxgbe: update flash part information Rahul Lakkireddy
2017-05-27  3:46 ` [dpdk-dev] [PATCH 04/13] cxgbe: grab available ports after firmware reset Rahul Lakkireddy
2017-05-27  3:46 ` [dpdk-dev] [PATCH 05/13] cxgbe: update link speeds and port modules Rahul Lakkireddy
2017-05-30 10:37   ` Ferruh Yigit
2017-05-27  3:46 ` Rahul Lakkireddy [this message]
2017-05-27  3:46 ` [dpdk-dev] [PATCH 07/13] cxgbe: update hardware info prints Rahul Lakkireddy
2017-05-27  3:46 ` [dpdk-dev] [PATCH 08/13] cxgbe: update TX path for Chelsio T6 Rahul Lakkireddy
2017-05-27  3:46 ` [dpdk-dev] [PATCH 09/13] cxgbe: update RXQ channel mapping " Rahul Lakkireddy
2017-05-27  3:46 ` [dpdk-dev] [PATCH 10/13] cxgbe: update RX path " Rahul Lakkireddy
2017-05-27  3:46 ` [dpdk-dev] [PATCH 11/13] cxgbe: add compressed error vector Rahul Lakkireddy
2017-05-27  3:46 ` [dpdk-dev] [PATCH 12/13] cxgbe: fix port statistics Rahul Lakkireddy
2017-05-27  3:46 ` [dpdk-dev] [PATCH 13/13] cxgbe: remove RTE_PCI_DRV_INTR_LSC from driver flags Rahul Lakkireddy
2017-05-30 10:28 ` [dpdk-dev] [PATCH 00/13] cxgbe: add support for Chelsio T6 family of adapters Thomas Monjalon
2017-06-01 16:02   ` Rahul Lakkireddy
2017-05-30 10:39 ` Ferruh Yigit

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