From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 577DD454EF; Tue, 25 Jun 2024 13:30:43 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5A85842E00; Tue, 25 Jun 2024 13:21:35 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by mails.dpdk.org (Postfix) with ESMTP id 9D99142FCB for ; Tue, 25 Jun 2024 13:18:21 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719314301; x=1750850301; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hAgE7EKWebOhFXDnikHUAamYn+sAQ+fJWAxS6LAuczY=; b=k1VEeNENvIoRG3OeM3fw6B4mWj8og4aCDeNXhm+uipNjnVf15WqAeHTd VWnkMDZzxrVpmIEM7bJUq2oolpscBKo23FBfgfoXTZ+6RPNOGubVFx3xB v3UOl70ky/Q5vccwy/Nm3ZCA453qUEXD91C4KtJd//R5uyooYjGhJd0dP SLctJPoJ+hz1mtQYulAaGjudhlKZJAtobu7VOYTYH0D1eO+vexT0pfbdJ nkdSEbN1/WKwHzxqc7uOE8ZqYfO1/nz7GtanPoSVIrGA5Uynq3LS3U5BV thO8LsmFR+zWZmAz+U13LXao4wZb3S6Bis2qfbt7t7Ag589yRPiQFpsMt g==; X-CSE-ConnectionGUID: U/Jzur4kRpKvccDNOVW5ow== X-CSE-MsgGUID: BNHucO7vToyaaUri8+PZIw== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16080677" X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="16080677" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2024 04:18:21 -0700 X-CSE-ConnectionGUID: I1iu3st6Q+2sjDEpuwRB+g== X-CSE-MsgGUID: UO2J7F8YTl+77RbRQ6sViA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="43719814" Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 25 Jun 2024 04:18:21 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Milena Olech , bruce.richardson@intel.com, ian.stokes@intel.com Subject: [PATCH v3 125/129] net/ice/base: change a method to get pca9575 handle Date: Tue, 25 Jun 2024 12:14:10 +0100 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Milena Olech More universal method for getting pca9575 handle is introduced. The first step is to look for CLK_MUX handle. Having that it is possible to find CLK_MUX GPIO pin. Provided data let check what is driving the pin - the expectation is that pca9575 node part number is returned. Signed-off-by: Milena Olech Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_ptp_hw.c | 46 +++++++++++++++++++++++++++---- 1 file changed, 41 insertions(+), 5 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 610512a8a9..b40daf9634 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -5122,10 +5122,11 @@ ice_get_phy_tx_tstamp_ready_e810(struct ice_hw *hw, u8 port, u64 *tstamp_ready) static int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) { + u8 node_part_number, idx, node_type_ctx_clk_mux, node_part_num_clk_mux; + struct ice_aqc_get_link_topo_pin cmd_pin; + u16 node_handle, clock_mux_handle; struct ice_aqc_get_link_topo cmd; - u8 node_part_number, idx; int status; - u16 node_handle; if (!hw || !pca9575_handle) return ICE_ERR_PARAM; @@ -5137,11 +5138,46 @@ ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) } memset(&cmd, 0, sizeof(cmd)); + memset(&cmd_pin, 0, sizeof(cmd_pin)); - /* Set node type to GPIO controller */ + node_type_ctx_clk_mux = (ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX << + ICE_AQC_LINK_TOPO_NODE_TYPE_S); + node_type_ctx_clk_mux |= (ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL << + ICE_AQC_LINK_TOPO_NODE_CTX_S); + node_part_num_clk_mux = ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX; + + /* Look for CLOCK MUX handle in the netlist */ + status = ice_find_netlist_node(hw, node_type_ctx_clk_mux, + node_part_num_clk_mux, + &clock_mux_handle); + if (status) + return ICE_ERR_NOT_SUPPORTED; + + /* Take CLOCK MUX GPIO pin */ + cmd_pin.input_io_params = (ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_GPIO << + ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S); + cmd_pin.input_io_params |= (ICE_AQC_LINK_TOPO_IO_FUNC_CLK_IN << + ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_S); + cmd_pin.addr.handle = CPU_TO_LE16(clock_mux_handle); + cmd_pin.addr.topo_params.node_type_ctx = + (ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX << + ICE_AQC_LINK_TOPO_NODE_TYPE_S); + cmd_pin.addr.topo_params.node_type_ctx |= + (ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED << + ICE_AQC_LINK_TOPO_NODE_CTX_S); + + status = ice_aq_get_netlist_node_pin(hw, &cmd_pin, &node_handle); + if (status) + return ICE_ERR_NOT_SUPPORTED; + + /* Check what is driving the pin */ cmd.addr.topo_params.node_type_ctx = - (ICE_AQC_LINK_TOPO_NODE_TYPE_M & - ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL); + (ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL << + ICE_AQC_LINK_TOPO_NODE_TYPE_S); + cmd.addr.topo_params.node_type_ctx |= + (ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL << + ICE_AQC_LINK_TOPO_NODE_CTX_S); + cmd.addr.handle = CPU_TO_LE16(node_handle); #define SW_PCA9575_SFP_TOPO_IDX 2 #define SW_PCA9575_QSFP_TOPO_IDX 1 -- 2.43.0