From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 752F0A04C3; Wed, 13 Nov 2019 15:50:15 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 28C932B8B; Wed, 13 Nov 2019 15:50:15 +0100 (CET) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id 111679E4 for ; Wed, 13 Nov 2019 15:50:12 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Nov 2019 06:50:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,300,1569308400"; d="scan'208";a="207471160" Received: from fyigit-mobl.ger.corp.intel.com (HELO [10.237.221.96]) ([10.237.221.96]) by orsmga003.jf.intel.com with ESMTP; 13 Nov 2019 06:50:10 -0800 To: Rosen Xu , dev@dpdk.org Cc: tianfei.zhang@intel.com, andy.pei@intel.com, xiaolong.ye@intel.com References: <1571917119-149534-2-git-send-email-andy.pei@intel.com> <1573628898-190337-1-git-send-email-rosen.xu@intel.com> <1573628898-190337-11-git-send-email-rosen.xu@intel.com> From: Ferruh Yigit Openpgp: preference=signencrypt Autocrypt: addr=ferruh.yigit@intel.com; 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charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH v16 10/19] raw/ifpga: add SEU error handler X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 11/13/2019 7:08 AM, Rosen Xu wrote: > Add SEU interrupt support for FPGA. > > Signed-off-by: Tianfei zhang > Signed-off-by: Rosen Xu > Signed-off-by: Andy Pei <...> > +static int > +fme_err_handle_error0(struct opae_manager *mgr) > +{ > + struct feature_fme_error0 fme_error0; > + u64 val; > + > + if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val)) > + return -EINVAL; > + > + fme_error0.csr = val; > + > + if (fme_error0.fabric_err) > + IFPGA_RAWDEV_PMD_ERR("Fabric error\n"); > + else if (fme_error0.fabfifo_overflow) > + IFPGA_RAWDEV_PMD_ERR("Fabric fifo under/overflow error\n"); > + else if (fme_error0.afu_acc_mode_err) > + IFPGA_RAWDEV_PMD_ERR("AFU PF/VF access mismatch detected\n"); > + else if (fme_error0.pcie0cdc_parity_err) > + IFPGA_RAWDEV_PMD_ERR("PCIe0 CDC Parity Error\n"); > + else if (fme_error0.cvlcdc_parity_err) > + IFPGA_RAWDEV_PMD_ERR("CVL CDC Parity Error\n"); > + else if (fme_error0.fpgaseuerr) { > + fme_err_read_seu_emr(mgr); > + rte_panic("SEU error occurred\n"); Hi Rosen, Andy, We are not allowed to call 'rte_panic()' from the drivers, can you please remove all instances?