From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by dpdk.org (Postfix) with ESMTP id 64E7CA48C; Fri, 12 Jan 2018 14:18:57 +0100 (CET) Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 2AD1BC0467E5; Fri, 12 Jan 2018 13:18:56 +0000 (UTC) Received: from [10.36.112.28] (ovpn-112-28.ams2.redhat.com [10.36.112.28]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 4407D859F7; Fri, 12 Jan 2018 13:18:48 +0000 (UTC) To: "Burakov, Anatoly" , dev@dpdk.org, stable@dpdk.org, jianfeng.tan@intel.com, qi.z.zhang@intel.com, stephen@networkplumber.org, santosh.shukla@caviumnetworks.com, thomas@monjalon.net Cc: peterx@redhat.com References: <20180112102220.20061-1-maxime.coquelin@redhat.com> <89c16dd0-3938-f9ae-cc9f-189388abc0a9@intel.com> From: Maxime Coquelin Message-ID: Date: Fri, 12 Jan 2018 14:18:47 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.2 MIME-Version: 1.0 In-Reply-To: <89c16dd0-3938-f9ae-cc9f-189388abc0a9@intel.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.31]); Fri, 12 Jan 2018 13:18:56 +0000 (UTC) Subject: Re: [dpdk-dev] [PATCH v3] bus/pci: forbid VA as IOVA mode if IOMMU address width too small X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Jan 2018 13:18:57 -0000 Hi Anatoly, On 01/12/2018 12:10 PM, Burakov, Anatoly wrote: > > >> +#if defined(RTE_ARCH_X86) >> +static bool >> +pci_one_device_iommu_support_va(struct rte_pci_device *dev) >> +{ >> +#define VTD_CAP_MGAW_SHIFT    16 >> +#define VTD_CAP_MGAW_MASK    (0x3fULL << VTD_CAP_MGAW_SHIFT) >> +#define X86_VA_WIDTH 47 /* From Documentation/x86/x86_64/mm.txt */ >> +    struct rte_pci_addr *addr = &dev->addr; >> +    char filename[PATH_MAX]; >> +    FILE *fp; >> +    uint64_t mgaw, vtd_cap_reg = 0; >> + >> +    snprintf(filename, sizeof(filename), >> +         "%s/" PCI_PRI_FMT "/iommu/intel-iommu/cap", >> +         rte_pci_get_sysfs_path(), addr->domain, addr->bus, addr->devid, >> +         addr->function); >> +    if (access(filename, F_OK) == -1) { >> +        /* We don't have an Intel IOMMU, assume VA supported*/ >> +        return true; >> +    } >> + >> +    /* We have an intel IOMMU */ >> +    fp = fopen(filename, "r"); >> +    if (fp == NULL) { >> +        RTE_LOG(ERR, EAL, "%s(): can't open %s\n", __func__, filename); >> +        return false; >> +    } >> + >> +    if (fscanf(fp, "%lx", &vtd_cap_reg) != 1) { >> +        RTE_LOG(ERR, EAL, "%s(): can't read %s\n", __func__, filename); >> +        fclose(fp); >> +        return false; >> +    } >> + >> +    fclose(fp); > > Hi Maxime, > > You probably want to use eal_parse_sysfs_value() for this. I initially planned to use it, but the sysfs value is hexadecimal, but not prefixed with "0x". For example: # cat /sys/devices/pci0000\:00/0000\:00\:02.0/iommu/intel-iommu/cap 1c0000c40660462 So strtoul() assumes the value is decimal in this case, as explained in its man page: " DESCRIPTION If base is zero or 16, the string may then include a "0x" prefix, and the number will be read in base 16; otherwise, a zero base is taken as 10 (decimal) " Thanks, Maxime