From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B6DCF454EF; Tue, 25 Jun 2024 13:25:39 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 040C44326E; Tue, 25 Jun 2024 13:18:40 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by mails.dpdk.org (Postfix) with ESMTP id 60EE342F0C for ; Tue, 25 Jun 2024 13:17:17 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719314237; x=1750850237; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3g+EB/wcKNQ+zqY1TsaqpqB+FM0kYCVEliXB1mp97RY=; b=RZ2lF+YwyY5cML1st8EMAaB2THGX1QGoP2PHLHZeRklQHCodr8ZdRbjO Uljx0Q7g4xpGj3dMGJs6YdJJH8WaAfGWPBAnSnYgKyXHhzd2K+LAHaCRQ kJmNUEU78t4NXInaMa5petwNPM4/lGcexVrtG6Ptc4Uf+6qy5HndQavW/ C8jEkRLuMw3ksUonEipdfjH3ZLIkQegF9bPvIMp4bLD4r5Y7KWu//ujWf WHvE1he3pJrexCgL1WkpbYkioylYRmpDRiI7Pq4DkjAiAe7NnVKG5U9VN cHW7KxNgksP8jGTCRepAZYw9yImDTPgZuty0uTUe5K0zBOjhgA0X8qk+Q A==; X-CSE-ConnectionGUID: azh4flTTTrKZlxhpO2C03Q== X-CSE-MsgGUID: oQCVimBRQ+O0mWTEuwDPEg== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16080423" X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="16080423" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2024 04:17:17 -0700 X-CSE-ConnectionGUID: gsq/QaynSIigo5BD/2eu0w== X-CSE-MsgGUID: QJe+0z6RTTa/6oxNV80iZQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="43719537" Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 25 Jun 2024 04:17:16 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Karol Kolacinski , bruce.richardson@intel.com, ian.stokes@intel.com Subject: [PATCH v3 086/129] net/ice/base: implement interface to reset timestamp memory Date: Tue, 25 Jun 2024 12:13:31 +0100 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Karol Kolacinski Add an interface to clear the timestamp memory block for E822 and ETH56G based devices. Signed-off-by: Karol Kolacinski Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_ptp_hw.c | 65 +++++++++++++++++++++++++++++++ drivers/net/ice/base/ice_ptp_hw.h | 2 + 2 files changed, 67 insertions(+) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 52ce4720b8..d3ad51f3ef 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -1481,6 +1481,25 @@ ice_clear_phy_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx) return 0; } +/** + * ice_ptp_reset_ts_memory_eth56g - Clear all timestamps from the port block + * @hw: pointer to the HW struct + */ +static void ice_ptp_reset_ts_memory_eth56g(struct ice_hw *hw) +{ + unsigned int port; + + for (port = 0; port < hw->max_phy_port; port++) { + if (!(hw->ena_lports & BIT(port))) + continue; + + ice_write_phy_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L, + 0); + ice_write_phy_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_U, + 0); + } +} + /** * ice_ptp_prep_port_phy_time_eth56g - Prepare one PHY port with initial time * @hw: pointer to the HW struct @@ -2989,6 +3008,33 @@ ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx) return 0; } +/** + * ice_ptp_reset_ts_memory_quad_e822 - Clear all timestamps from the quad block + * @hw: pointer to the HW struct + * @quad: the quad to read from + * + * Clear all timestamps from the PHY quad block that is shared between the + * internal PHYs on the E822 devices. + */ +void ice_ptp_reset_ts_memory_quad_e822(struct ice_hw *hw, u8 quad) +{ + ice_write_quad_reg_e822(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M); + ice_write_quad_reg_e822(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M); +} + +/** + * ice_ptp_reset_ts_memory_e822 - Clear all timestamps from all quad blocks + * @hw: pointer to the HW struct + */ +static void ice_ptp_reset_ts_memory_e822(struct ice_hw *hw) +{ + u8 quad; + + for (quad = 0; quad < ICE_MAX_QUAD; quad++) { + ice_ptp_reset_ts_memory_quad_e822(hw, quad); + } +} + /** * ice_ptp_set_vernier_wl - Set the window length for vernier calibration * @hw: pointer to the HW struct @@ -6045,6 +6091,25 @@ ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx) return err; } +/** + * ice_ptp_reset_ts_memory - Reset timestamp memory for all blocks + * @hw: pointer to the HW struct + */ +void ice_ptp_reset_ts_memory(struct ice_hw *hw) +{ + switch (hw->phy_model) { + case ICE_PHY_ETH56G: + ice_ptp_reset_ts_memory_eth56g(hw); + break; + case ICE_PHY_E822: + ice_ptp_reset_ts_memory_e822(hw); + break; + case ICE_PHY_E810: + default: + return; + } +} + /** * ice_ptp_init_phc - Initialize PTP hardware clock * @hw: pointer to the HW struct diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index 5b6a729e94..58aa45596a 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -142,6 +142,7 @@ int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp); int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx); +void ice_ptp_reset_ts_memory(struct ice_hw *hw); int ice_ptp_init_phc(struct ice_hw *hw); bool refsync_pin_id_valid(struct ice_hw *hw, u8 id); int @@ -165,6 +166,7 @@ ice_ptp_read_phy_incval_e822(struct ice_hw *hw, u8 port, u64 *incval); int ice_ptp_read_port_capture_e822(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts); +void ice_ptp_reset_ts_memory_quad_e822(struct ice_hw *hw, u8 quad); int ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq, enum ice_clk_src *clk_src); -- 2.43.0