From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5FDC54404F; Wed, 12 Jun 2024 17:27:38 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7DDD44334E; Wed, 12 Jun 2024 17:07:27 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mails.dpdk.org (Postfix) with ESMTP id 97E8543318 for ; Wed, 12 Jun 2024 17:07:16 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718204837; x=1749740837; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Hkl7RR7XIyEjoAqX5XLE0VY+X2I83Q+R3wREKOkRg3g=; b=A9w09y5eSal/Mf0GJ8I7tnXHx1MBhAoyeozojypXtZV0RyakNU/3SCnv a5wbcM45t4AmAdikdHjlPKFD4MSFaXOk5U7UCIqswl6q/VsMFOHMTyS0R QK7H0TQ+PUD8Aah6/lRT0BNun+WwK0MpVlSrJS5ukOpuy5RU5H0MKbWua lbs5nlrWJ4BFIzzicwTZN5KfEB59n+028UAShXCWJrVeGWmFag5AV9ot9 g9YjqNwiCzCbIt/cMrpV7whVDeUKmikAwN/Unt3NNyScNSWGPRbnY+G9z On/iDd0heqKnX5REAmPFfGea9QDQWl56GS7r61uCLiKJmWxIV9UwLntp3 A==; X-CSE-ConnectionGUID: WLryeqrXSgmwfasFWA2MZA== X-CSE-MsgGUID: 0+zzlXWFSUGp528MjNx/Bw== X-IronPort-AV: E=McAfee;i="6700,10204,11101"; a="32460176" X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="32460176" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2024 08:07:16 -0700 X-CSE-ConnectionGUID: SOHQdtjrSlStqQu3WvLukg== X-CSE-MsgGUID: tANF7wQoRoewn1uFZdw55g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="39926092" Received: from silpixa00401119.ir.intel.com ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 12 Jun 2024 08:07:15 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Ian Stokes , bruce.richardson@intel.com, Milena Olech Subject: [PATCH v2 143/148] net/ice/base: change a method to get pca9575 handle Date: Wed, 12 Jun 2024 16:02:17 +0100 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: <20240430154014.1026-1-ian.stokes@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Ian Stokes More universal method for getting pca9575 handle is introduced. The first step is to look for CLK_MUX handle. Having that it is possible to find CLK_MUX GPIO pin. Provided data let check what is driving the pin - the expectation is that pca9575 node part number is returned. Signed-off-by: Milena Olech Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_ptp_hw.c | 46 +++++++++++++++++++++++++++---- 1 file changed, 41 insertions(+), 5 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index f7d397ae51..3e6ce8331f 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -5123,10 +5123,11 @@ ice_get_phy_tx_tstamp_ready_e810(struct ice_hw *hw, u8 port, u64 *tstamp_ready) static int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) { + u8 node_part_number, idx, node_type_ctx_clk_mux, node_part_num_clk_mux; + struct ice_aqc_get_link_topo_pin cmd_pin; + u16 node_handle, clock_mux_handle; struct ice_aqc_get_link_topo cmd; - u8 node_part_number, idx; int status; - u16 node_handle; if (!hw || !pca9575_handle) return ICE_ERR_PARAM; @@ -5138,11 +5139,46 @@ ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) } memset(&cmd, 0, sizeof(cmd)); + memset(&cmd_pin, 0, sizeof(cmd_pin)); - /* Set node type to GPIO controller */ + node_type_ctx_clk_mux = (ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX << + ICE_AQC_LINK_TOPO_NODE_TYPE_S); + node_type_ctx_clk_mux |= (ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL << + ICE_AQC_LINK_TOPO_NODE_CTX_S); + node_part_num_clk_mux = ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX; + + /* Look for CLOCK MUX handle in the netlist */ + status = ice_find_netlist_node(hw, node_type_ctx_clk_mux, + node_part_num_clk_mux, + &clock_mux_handle); + if (status) + return ICE_ERR_NOT_SUPPORTED; + + /* Take CLOCK MUX GPIO pin */ + cmd_pin.input_io_params = (ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_GPIO << + ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S); + cmd_pin.input_io_params |= (ICE_AQC_LINK_TOPO_IO_FUNC_CLK_IN << + ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_S); + cmd_pin.addr.handle = CPU_TO_LE16(clock_mux_handle); + cmd_pin.addr.topo_params.node_type_ctx = + (ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX << + ICE_AQC_LINK_TOPO_NODE_TYPE_S); + cmd_pin.addr.topo_params.node_type_ctx |= + (ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED << + ICE_AQC_LINK_TOPO_NODE_CTX_S); + + status = ice_aq_get_netlist_node_pin(hw, &cmd_pin, &node_handle); + if (status) + return ICE_ERR_NOT_SUPPORTED; + + /* Check what is driving the pin */ cmd.addr.topo_params.node_type_ctx = - (ICE_AQC_LINK_TOPO_NODE_TYPE_M & - ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL); + (ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL << + ICE_AQC_LINK_TOPO_NODE_TYPE_S); + cmd.addr.topo_params.node_type_ctx |= + (ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL << + ICE_AQC_LINK_TOPO_NODE_CTX_S); + cmd.addr.handle = CPU_TO_LE16(node_handle); #define SW_PCA9575_SFP_TOPO_IDX 2 #define SW_PCA9575_QSFP_TOPO_IDX 1 -- 2.43.0