From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 6630F2BE1 for ; Fri, 24 Mar 2017 12:58:58 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1490356738; x=1521892738; h=subject:to:references:cc:from:message-id:date: mime-version:in-reply-to:content-transfer-encoding; bh=rpqJMFwDX1WSqXXzChiGkSaAt/xUwjnuHZO83w4HF3A=; b=M44Kanl0n/lO+Z0dvEWonzSrlRXYz+UIj6x0+q9mMuLuEAfm1qk2z3Ot ua5d8OkSVYvGG6EZ1gqKV0pA3D9S/A==; Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Mar 2017 04:58:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,214,1486454400"; d="scan'208";a="1146463268" Received: from fyigit-mobl1.ger.corp.intel.com (HELO [10.237.220.122]) ([10.237.220.122]) by fmsmga002.fm.intel.com with ESMTP; 24 Mar 2017 04:58:55 -0700 To: Rasesh Mody , dev@dpdk.org References: <162b5be7-d8a5-0e89-a32f-b1a992aef2a3@intel.com> <1489820786-14226-62-git-send-email-rasesh.mody@cavium.com> Cc: Harish Patil , Dept-EngDPDKDev@cavium.com From: Ferruh Yigit Message-ID: Date: Fri, 24 Mar 2017 11:58:55 +0000 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: <1489820786-14226-62-git-send-email-rasesh.mody@cavium.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH v2 61/61] net/qede: add LRO/TSO offloads support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 24 Mar 2017 11:58:58 -0000 On 3/18/2017 7:06 AM, Rasesh Mody wrote: > From: Harish Patil > > This patch includes slowpath configuration and fastpath changes > to support LRO and TSO. A bit of revamping is needed in order > to make use of existing packet classification schemes in Rx fastpath > and for SG element processing in Tx. > > Signed-off-by: Harish Patil This patch is giving following checkpatch errors [1], I can see the reason of the multiline dereference is to fit into 80 column line limit, and those lines are not easy to escape from line limit. But eventually if we get a checkpatch warning, I prefer it to be from long line, multiline dereference makes code harder to read. What do you think? [1] WARNING:MULTILINE_DEREFERENCE: Avoid multiple line dereference - prefer 'cqe_start_tpa->len_on_first_bd' #450: FILE: drivers/net/qede/qede_rxtx.c:1045: + rte_le_to_cpu_16(cqe_start_tpa-> + len_on_first_bd), WARNING:MULTILINE_DEREFERENCE: Avoid multiple line dereference - prefer 'cqe_start_tpa->ext_bd_len_list[0]' #453: FILE: drivers/net/qede/qede_rxtx.c:1048: + rte_le_to_cpu_16(cqe_start_tpa-> + ext_bd_len_list[0]), WARNING:MULTILINE_DEREFERENCE: Avoid multiple line dereference - prefer 'rxq->tpa_info[cqe->fast_path_tpa_end.tpa_agg_index].mbuf' #465: FILE: drivers/net/qede/qede_rxtx.c:1060: + rx_mb = rxq-> + tpa_info[cqe->fast_path_tpa_end.tpa_agg_index].mbuf; WARNING:MULTILINE_DEREFERENCE: Avoid multiple line dereference - prefer 'cqe_start_tpa->pars_flags.flags' #512: FILE: drivers/net/qede/qede_rxtx.c:1087: + parse_flag = rte_le_to_cpu_16(cqe_start_tpa-> + pars_flags.flags); WARNING:MULTILINE_DEREFERENCE: Avoid multiple line dereference - prefer 'cqe_start_tpa->tunnel_pars_flags.flags' #541: FILE: drivers/net/qede/qede_rxtx.c:1108: + tunn_parse_flag = cqe_start_tpa-> + tunnel_pars_flags.flags; WARNING:MULTILINE_DEREFERENCE: Avoid multiple line dereference - prefer 'fp_cqe->tunnel_pars_flags.flags' #544: FILE: drivers/net/qede/qede_rxtx.c:1111: + tunn_parse_flag = fp_cqe-> + tunnel_pars_flags.flags; <...>