Hi Honnappa,

The attachment is our current r8168pmd code for RTL8111/8168 Giga series

(currently 8111G, 8111H are supported, we will add others later)

I will contact the SoC vendor to consult you about this issue and let you know some details about that SoC

Thanks a lot!

BRs

Xing Wang

发件人: Honnappa Nagarahalli [mailto:Honnappa.Nagarahalli@arm.com]
发送时间: 2022年8月25日 22:41
收件人: 王星 <xing_wang@realsil.com.cn>; dev@dpdk.org
抄送: 陈立 <dali_chen@realsil.com.cn>; 王颢 <howard_wang@realsil.com.cn>; Ruifeng Wang <Ruifeng.Wang@arm.com>; nd <nd@arm.com>; nd <nd@arm.com>
主题: RE: about RTL8168 PMD on ARM SoC

Hello,

               I cannot find many details of the SoC on the internet. Does it use coherent IO? Depending on that, different barriers might be needed. Other than this, I would not think it needs anything special.

If you could send an RFC to the DPDK mailing list, I am happy to review and provide any feedback.

Thanks,

Honnappa

From: 王星 <xing_wang@realsil.com.cn>
Sent: Wednesday, August 24, 2022 9:53 PM
To: dev@dpdk.org
Cc: 陈立 <dali_chen@realsil.com.cn>; 王颢 <howard_wang@realsil.com.cn>
Subject: about RTL8168 PMD on ARM SoC

Hi DPDK,

I am a pmd driver developer from Realtek NIC department,

when I was porting r8168pmd already verified on x86 to an ARM64 SoC Unisoc: UIS8650

I found that after NIC Rx init (in general, Rx ring and buffers should have been prepared for NIC to DMA read),

the NIC status reg showed RDU (Rx Descriptor Unavailable), which means NIC cannot read the proper desc content,

later I sended some packets to NIC hold by testpmd rx_only mode, HW internal Rx packet counter can grow to some value, then stuck, 8168pmd Rx debug print reported it received less packets than that value, and the print showed up even some minutes later!

I doubt the phenomenon is caused by improper HW-based IO coherency support on this ARM SoC,

I have read the ARM SoC support list on DPDK website, to name it: NV Bluefield, NXP DPAA, Marvell Octeon TX …

Does DPDK (or UIO/VFIO driver or hugetlb driver) need special HW IO cache coherency support on ARM platform, say, ACE and Device side MMU etc?

Should the SoC provide specialized UIO/VFIO driver or hugetlb driver and/or specific DPDK lib to support such user mode DMA?

Will you please give suggestions, thanks a lot!

BRs

------Please consider the environment before printing this e-mail.