From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id ECA38A0524; Fri, 23 Apr 2021 14:32:10 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7419D410EB; Fri, 23 Apr 2021 14:32:10 +0200 (CEST) Received: from dal3relay44.mxroute.com (dal3relay44.mxroute.com [64.40.27.44]) by mails.dpdk.org (Postfix) with ESMTP id AF919410D8 for ; Fri, 23 Apr 2021 14:32:09 +0200 (CEST) Received: from filter004.mxroute.com ([149.28.56.236] filter004.mxroute.com) (Authenticated sender: mN4UYu2MZsgR) by dal3relay44.mxroute.com (ZoneMTA) with ESMTPSA id 178feb74add000881b.001 for (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES128-GCM-SHA256); Fri, 23 Apr 2021 12:32:08 +0000 X-Zone-Loop: fb895f2cbecfb9f6b64f8d8d47a6feb283ad87489905 X-Originating-IP: [149.28.56.236] DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=ashroe.eu; s=x; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:MIME-Version:Date: Message-ID:From:References:Cc:To:Subject:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=8xE18dzRFpYHAB8C/BTKNyHtNcp9/z0/pyqmBDzN1Ro=; b=cikCW9474U8vdCVpcKSKLbR/+2 dG19Kx7C2KDqxY2v4EI+i01m074MvLbIkxwLyE3n1cbxBSMjxpLIoUrs3GyKcwRn4T/mOPdvdi4Ys HM9AlR4M5OO+hpzSYIwmPBOMZatjmn/gCdwOGrjmDrHj2V8pyNLCfhp3W/23DKPVzXJg2trhOwr6o LEPwAwPp/Do7rG4S+H5/h57Ox4u0cENWps1SAnnhq/6upZzFByYJMO6ukqX0LN0+rmPQ8XiTjWXbF SQV4nQRMPJY7yBHZRUiXb9ztfLgLJAhaI0FkbViT5io+njqU49TROjKONWRVHigUndXkfDwMEI7rQ Tt+uqcLQ==; To: Haiyue Wang , dev@dpdk.org Cc: qi.z.zhang@intel.com, liang-min.wang@intel.com, Neil Horman , Gaetan Rivet References: <20210421050243.130585-1-haiyue.wang@intel.com> <20210423114001.174723-1-haiyue.wang@intel.com> <20210423114001.174723-2-haiyue.wang@intel.com> From: "Kinsella, Ray" Message-ID: Date: Fri, 23 Apr 2021 13:32:04 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.9.1 MIME-Version: 1.0 In-Reply-To: <20210423114001.174723-2-haiyue.wang@intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-AuthUser: mdr@ashroe.eu Subject: Re: [dpdk-dev] [PATCH v3 1/3] bus/pci: enable PCI master in command register X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 23/04/2021 12:39, Haiyue Wang wrote: > This adds the support to set 'Bus Master Enable' bit in the PCI command > register. > > Signed-off-by: Haiyue Wang > Tested-by: Qi Zhang > --- > drivers/bus/pci/pci_common.c | 20 ++++++++++++++++++++ > drivers/bus/pci/rte_bus_pci.h | 12 ++++++++++++ > drivers/bus/pci/version.map | 3 +++ > lib/pci/rte_pci.h | 4 ++++ > 4 files changed, 39 insertions(+) > > diff --git a/drivers/bus/pci/pci_common.c b/drivers/bus/pci/pci_common.c > index ee7f96635..b631cb9c7 100644 > --- a/drivers/bus/pci/pci_common.c > +++ b/drivers/bus/pci/pci_common.c > @@ -746,6 +746,26 @@ rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap) > return 0; > } > > +int > +rte_pci_enable_bus_master(struct rte_pci_device *dev) > +{ > + uint16_t cmd; > + > + if (rte_pci_read_config(dev, &cmd, sizeof(cmd), RTE_PCI_COMMAND) < 0) { > + RTE_LOG(ERR, EAL, "error in reading PCI command register\n"); > + return -1; > + } > + > + cmd |= RTE_PCI_COMMAND_MASTER; > + > + if (rte_pci_write_config(dev, &cmd, sizeof(cmd), RTE_PCI_COMMAND) < 0) { > + RTE_LOG(ERR, EAL, "error in writing PCI command register\n"); > + return -1; > + } > + > + return 0; > +} > + > struct rte_pci_bus rte_pci_bus = { > .bus = { > .scan = rte_pci_scan, > diff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h > index 64886b473..83caf477b 100644 > --- a/drivers/bus/pci/rte_bus_pci.h > +++ b/drivers/bus/pci/rte_bus_pci.h > @@ -249,6 +249,18 @@ void rte_pci_dump(FILE *f); > __rte_experimental > off_t rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap); > > +/** > + * Enables Bus Master for device's PCI command register. > + * > + * @param dev > + * A pointer to rte_pci_device structure. > + * > + * @return > + * 0 on success, -1 on error in PCI config space read/write. > + */ > +__rte_experimental > +int rte_pci_enable_bus_master(struct rte_pci_device *dev); > + > /** > * Register a PCI driver. > * > diff --git a/drivers/bus/pci/version.map b/drivers/bus/pci/version.map > index f33ed0abd..9dbec12a0 100644 > --- a/drivers/bus/pci/version.map > +++ b/drivers/bus/pci/version.map > @@ -21,4 +21,7 @@ EXPERIMENTAL { > global: > > rte_pci_find_ext_capability; > + > + # added in 21.05 > + rte_pci_enable_bus_master; > }; > diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h > index a8f8e404a..1f33d687f 100644 > --- a/lib/pci/rte_pci.h > +++ b/lib/pci/rte_pci.h > @@ -32,6 +32,10 @@ extern "C" { > > #define RTE_PCI_VENDOR_ID 0x00 /* 16 bits */ > #define RTE_PCI_DEVICE_ID 0x02 /* 16 bits */ > +#define RTE_PCI_COMMAND 0x04 /* 16 bits */ > + > +/* PCI Command Register */ > +#define RTE_PCI_COMMAND_MASTER 0x4 /* Bus Master Enable */ > > /* PCI Express capability registers */ > #define RTE_PCI_EXP_DEVCTL 8 /* Device Control */ > Acked-by: Ray Kinsella