From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C1B14454EF; Tue, 25 Jun 2024 13:30:31 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1CAEB43357; Tue, 25 Jun 2024 13:21:14 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by mails.dpdk.org (Postfix) with ESMTP id 7555042FB5 for ; Tue, 25 Jun 2024 13:18:18 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719314298; x=1750850298; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7GZ/LlWrHLxxsBrdHyv7PVksgCmNxdXuyfAIx34x98M=; b=P39qwiAUcavB16WA4cQ7Eglp3kN/AxBqfXcskNzwE1KGxt6n5co8fabV 84+dz1Aq+t0GvYGB38NnsvxRwhJxnY+DZ/pHXxojMNzRzXC6KtTeAeDpB K567J/JsD/TpU+fPwH4Og5sPL7XCQAj3DHIajMCegKCF/+D8Od1g5zI9d 1ENhbZBeTrvZcyal/W7/kPboAZ17pPIdUac/SsCEMQDv+Han4GGM3Q+8F rn7p3a8S5qY4SxZHs0uujUsZT6GvaFYmI3KmlDwTmKEkUpg9BbiWZkrZe zeq3kJC0DofVHYj+DhflFbve1dYfTHfNLT7n17VexfRSzat80Ynhwf2kX Q==; X-CSE-ConnectionGUID: jmhyda3iRCu+DmE0N0qO4Q== X-CSE-MsgGUID: HIgcyVoZQcuPdc1QIvvPXA== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16080670" X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="16080670" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2024 04:18:18 -0700 X-CSE-ConnectionGUID: yMK0OzbVTRmPmo7P2DyJJA== X-CSE-MsgGUID: CCSl3u33SUqjbg/2HBmghw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="43719801" Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 25 Jun 2024 04:18:17 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Sergey Temerkhanov , bruce.richardson@intel.com, ian.stokes@intel.com Subject: [PATCH v3 123/129] net/ice/base: implement TX interrupt enablement functions Date: Tue, 25 Jun 2024 12:14:08 +0100 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sergey Temerkhanov Introduce functions enabling/disabling TX TS interrupts for the E822 and ETH56G PHYs Signed-off-by: Sergey Temerkhanov Signed-off-by: Anatoly Burakov --- drivers/net/ice/base/ice_ptp_hw.c | 73 +++++++++++++++++++++++++++++++ drivers/net/ice/base/ice_ptp_hw.h | 4 ++ 2 files changed, 77 insertions(+) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 2d042367a7..8f25d79a53 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -2040,6 +2040,41 @@ int ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port) return ice_write_phy_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 1); } +/** + * ice_phy_cfg_intr_eth56g - Configure TX timestamp interrupt + * @hw: pointer to the HW struct + * @port: the timestamp port + * @ena: enable or disable interrupt + * @threshold: interrupt threshold + * + * Configure TX timestamp interrupt for the specified port + */ + +int +ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold) +{ + int err; + u32 val; + + err = ice_read_phy_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, + &val); + if (err) + return err; + + if (ena) { + val |= PHY_TS_INT_CONFIG_ENA_M; + val &= ~PHY_TS_INT_CONFIG_THRESHOLD_M; + val |= ((threshold << PHY_TS_INT_CONFIG_THRESHOLD_S) & + PHY_TS_INT_CONFIG_THRESHOLD_M); + } else { + val &= ~PHY_TS_INT_CONFIG_ENA_M; + } + + err = ice_write_phy_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, + val); + return err; +} + /** * ice_ptp_clear_phy_offset_ready_eth56g - Clear PHY OFFSET_READY registers * @hw: pointer to the HW struct @@ -4502,6 +4537,44 @@ ice_get_phy_tx_tstamp_ready_e822(struct ice_hw *hw, u8 quad, u64 *tstamp_ready) return 0; } +/** + * ice_phy_cfg_intr_e822 - Configure TX timestamp interrupt + * @hw: pointer to the HW struct + * @quad: the timestamp quad + * @ena: enable or disable interrupt + * @threshold: interrupt threshold + * + * Configure TX timestamp interrupt for the specified quad + */ + +int +ice_phy_cfg_intr_e822(struct ice_hw *hw, u8 quad, bool ena, u8 threshold) +{ + int err; + u32 val; + + err = ice_read_quad_reg_e822(hw, quad, + Q_REG_TX_MEM_GBL_CFG, + &val); + if (err) + return err; + + if (ena) { + val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; + val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M; + val |= ((threshold << Q_REG_TX_MEM_GBL_CFG_INTR_THR_S) & + Q_REG_TX_MEM_GBL_CFG_INTR_THR_M); + } else { + val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; + } + + err = ice_write_quad_reg_e822(hw, quad, + Q_REG_TX_MEM_GBL_CFG, + val); + + return err; +} + /* E810 functions * * The following functions operate on the E810 series devices which use diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index 686246ab92..345d343a5a 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -259,6 +259,8 @@ ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset); int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port); int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port); int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port); +int +ice_phy_cfg_intr_e822(struct ice_hw *hw, u8 quad, bool ena, u8 threshold); /* E810 family functions */ int ice_ptp_init_phy_e810(struct ice_hw *hw); @@ -302,6 +304,8 @@ int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port); int ice_phy_cfg_tx_offset_eth56g(struct ice_hw *hw, u8 port); int ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port); +int +ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold); #define ICE_ETH56G_PLL_FREQ 800000000 #define ICE_ETH56G_NOMINAL_INCVAL 0x140000000ULL -- 2.43.0