* [PATCH v2 0/3] Add RISC-V V extension detection and LPM optimization
2025-05-28 16:57 [PATCH 1/3] config/riscv: detect V extension uk7b
@ 2025-06-04 11:49 ` uk7b
2025-06-04 11:49 ` [PATCH v2 1/3] config/riscv: detect V extension uk7b
` (10 subsequent siblings)
11 siblings, 0 replies; 19+ messages in thread
From: uk7b @ 2025-06-04 11:49 UTC (permalink / raw)
To: dev; +Cc: sunyuechi
From: sunyuechi <sunyuechi@iscas.ac.cn>
This patch series adds support for the RISC-V Vector (V) extension and provides
an optimized implementation of `rte_lpm_lookupx4` using RVV. It includes runtime
detection of the V extension, conditional compilation based on compiler support
for RVV intrinsics.
Test results using lpm_perf_autotest on BPI-F3:
scalar: 5.7 cycles
rvv: 2.4 cycles
### v2:
- Improved commit messages.
sunyuechi (3):
config/riscv: detect V extension
lib/lpm: R-V V rte_lpm_lookupx4
riscv: override machine_args only when default
MAINTAINERS | 2 +
config/riscv/meson.build | 27 ++++++++++++
lib/lpm/meson.build | 1 +
lib/lpm/rte_lpm.h | 2 +
lib/lpm/rte_lpm_rvv.h | 91 ++++++++++++++++++++++++++++++++++++++++
5 files changed, 123 insertions(+)
create mode 100644 lib/lpm/rte_lpm_rvv.h
--
2.49.0
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 1/3] config/riscv: detect V extension
2025-05-28 16:57 [PATCH 1/3] config/riscv: detect V extension uk7b
2025-06-04 11:49 ` [PATCH v2 0/3] Add RISC-V V extension detection and LPM optimization uk7b
@ 2025-06-04 11:49 ` uk7b
2025-06-04 19:54 ` Stephen Hemminger
2025-06-04 11:49 ` [PATCH v2 2/3] lib/lpm: R-V V rte_lpm_lookupx4 uk7b
` (9 subsequent siblings)
11 siblings, 1 reply; 19+ messages in thread
From: uk7b @ 2025-06-04 11:49 UTC (permalink / raw)
To: dev; +Cc: sunyuechi, Stanislaw Kardach, Bruce Richardson
From: sunyuechi <sunyuechi@iscas.ac.cn>
This patch is derived from "config/riscv: detect presence of Zbc
extension with modifications".
The RISC-V C api defines architecture extension test macros
These let us detect whether the V extension is supported on the
compiler and -march we're building with. The C api also defines V
intrinsics we can use rather than inline assembly on newer versions of
GCC (14.1.0+) and Clang (18.1.0+).
If the V extension and intrinsics are both present and we can detect
the V extension at runtime, we define a flag, RTE_RISCV_FEATURE_V.
Signed-off-by: sunyuechi <sunyuechi@iscas.ac.cn>
---
config/riscv/meson.build | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/config/riscv/meson.build b/config/riscv/meson.build
index 7562c6cb99..e3694cf2e6 100644
--- a/config/riscv/meson.build
+++ b/config/riscv/meson.build
@@ -119,6 +119,31 @@ foreach flag: arch_config['machine_args']
endif
endforeach
+# check if we can do buildtime detection of extensions supported by the target
+riscv_extension_macros = false
+if (cc.get_define('__riscv_arch_test', args: machine_args) == '1')
+ message('Detected architecture extension test macros')
+ riscv_extension_macros = true
+else
+ warning('RISC-V architecture extension test macros not available. Build-time detection of extensions not possible')
+endif
+
+# detect extensions
+# Requires intrinsics available in GCC 14.1.0+ and Clang 18.1.0+
+if (riscv_extension_macros and
+ (cc.get_define('__riscv_vector', args: machine_args) != ''))
+ if ((cc.get_id() == 'gcc' and cc.version().version_compare('>=14.1.0'))
+ or (cc.get_id() == 'clang' and cc.version().version_compare('>=18.1.0')))
+ if (cc.compiles('''#include <riscv_vector.h>
+ int main(void) { size_t vl = __riscv_vsetvl_e32m1(1); }''', args: machine_args))
+ message('Compiling with the V extension')
+ machine_args += ['-DRTE_RISCV_FEATURE_V']
+ endif
+ else
+ warning('Detected V extension but cannot use because intrinsics are not available (present in GCC 14.1.0+ and Clang 18.1.0+)')
+ endif
+endif
+
# apply flags
foreach flag: dpdk_flags
if flag.length() > 0
--
2.49.0
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v2 1/3] config/riscv: detect V extension
2025-06-04 11:49 ` [PATCH v2 1/3] config/riscv: detect V extension uk7b
@ 2025-06-04 19:54 ` Stephen Hemminger
0 siblings, 0 replies; 19+ messages in thread
From: Stephen Hemminger @ 2025-06-04 19:54 UTC (permalink / raw)
To: uk7b; +Cc: dev, sunyuechi, Stanislaw Kardach, Bruce Richardson
On Wed, 4 Jun 2025 19:49:16 +0800
uk7b@foxmail.com wrote:
> From: sunyuechi <sunyuechi@iscas.ac.cn>
>
> This patch is derived from "config/riscv: detect presence of Zbc
> extension with modifications".
>
> The RISC-V C api defines architecture extension test macros
> These let us detect whether the V extension is supported on the
> compiler and -march we're building with. The C api also defines V
> intrinsics we can use rather than inline assembly on newer versions of
> GCC (14.1.0+) and Clang (18.1.0+).
>
> If the V extension and intrinsics are both present and we can detect
> the V extension at runtime, we define a flag, RTE_RISCV_FEATURE_V.
>
> Signed-off-by: sunyuechi <sunyuechi@iscas.ac.cn>
Need entry in .mailmap as first patch, we keep track of contributions.
Since Signed-off-by has legal meaning you need to use full legal name.
By giving Signed-off-by you are saying that "yes, I have full legal right
to open source this".
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 2/3] lib/lpm: R-V V rte_lpm_lookupx4
2025-05-28 16:57 [PATCH 1/3] config/riscv: detect V extension uk7b
2025-06-04 11:49 ` [PATCH v2 0/3] Add RISC-V V extension detection and LPM optimization uk7b
2025-06-04 11:49 ` [PATCH v2 1/3] config/riscv: detect V extension uk7b
@ 2025-06-04 11:49 ` uk7b
2025-06-04 11:49 ` [PATCH v2 3/3] riscv: override machine_args only when default uk7b
` (8 subsequent siblings)
11 siblings, 0 replies; 19+ messages in thread
From: uk7b @ 2025-06-04 11:49 UTC (permalink / raw)
To: dev
Cc: sunyuechi, Thomas Monjalon, Bruce Richardson, Vladimir Medvedkin,
Stanislaw Kardach
From: sunyuechi <sunyuechi@iscas.ac.cn>
Test results using lpm_perf_autotest on BPI-F3:
scalar: 5.7 cycles
rvv: 2.4 cycles
The best way to call this RVV function is to follow the approach used in
lib/fib, where all architectures initialize a function pointer in a
unified way. However, other architectures in lib/lpm do not follow this
pattern. Therefore, to avoid affecting other architectures, this commit
does not modify lib/lpm/rte_lpm.c.
Unifying the code style between lpm and fib may be worth considering
in the future.
Signed-off-by: sunyuechi <sunyuechi@iscas.ac.cn>
---
MAINTAINERS | 2 +
lib/lpm/meson.build | 1 +
lib/lpm/rte_lpm.h | 2 +
lib/lpm/rte_lpm_rvv.h | 91 +++++++++++++++++++++++++++++++++++++++++++
4 files changed, 96 insertions(+)
create mode 100644 lib/lpm/rte_lpm_rvv.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 3e16789250..0f207ac129 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -340,6 +340,8 @@ M: Stanislaw Kardach <stanislaw.kardach@gmail.com>
F: config/riscv/
F: doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
F: lib/eal/riscv/
+M: sunyuechi <sunyuechi@iscas.ac.cn>
+F: lib/**/*rvv*
Intel x86
M: Bruce Richardson <bruce.richardson@intel.com>
diff --git a/lib/lpm/meson.build b/lib/lpm/meson.build
index fae4f79fb9..09133061e5 100644
--- a/lib/lpm/meson.build
+++ b/lib/lpm/meson.build
@@ -17,6 +17,7 @@ indirect_headers += files(
'rte_lpm_scalar.h',
'rte_lpm_sse.h',
'rte_lpm_sve.h',
+ 'rte_lpm_rvv.h',
)
deps += ['hash']
deps += ['rcu']
diff --git a/lib/lpm/rte_lpm.h b/lib/lpm/rte_lpm.h
index 7df64f06b1..b06517206f 100644
--- a/lib/lpm/rte_lpm.h
+++ b/lib/lpm/rte_lpm.h
@@ -408,6 +408,8 @@ rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4],
#include "rte_lpm_altivec.h"
#elif defined(RTE_ARCH_X86)
#include "rte_lpm_sse.h"
+#elif defined(RTE_ARCH_RISCV) && defined(RTE_RISCV_FEATURE_V)
+#include "rte_lpm_rvv.h"
#else
#include "rte_lpm_scalar.h"
#endif
diff --git a/lib/lpm/rte_lpm_rvv.h b/lib/lpm/rte_lpm_rvv.h
new file mode 100644
index 0000000000..e39ade3f07
--- /dev/null
+++ b/lib/lpm/rte_lpm_rvv.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) 2025 Institute of Software Chinese Academy of Sciences (ISCAS).
+ */
+
+#ifndef _RTE_LPM_RVV_H_
+#define _RTE_LPM_RVV_H_
+
+#include <rte_vect.h>
+
+#include <rte_cpuflags.h>
+#include <riscv_vector.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RTE_LPM_LOOKUP_SUCCESS 0x01000000
+#define RTE_LPM_VALID_EXT_ENTRY_BITMASK 0x03000000
+
+typedef void (*lpm_lookupx4_fn)(const struct rte_lpm *, xmm_t, uint32_t *, uint32_t);
+
+static lpm_lookupx4_fn lpm_lookupx4_impl;
+
+static inline void rte_lpm_lookupx4_scalar(
+ const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], uint32_t defv)
+{
+ uint32_t nh;
+ int ret;
+
+ for (int i = 0; i < 4; i++) {
+ ret = rte_lpm_lookup(lpm, ip[i], &nh);
+ hop[i] = (ret == 0) ? nh : defv;
+ }
+}
+
+static inline void rte_lpm_lookupx4_rvv(
+ const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], uint32_t defv)
+{
+ size_t vl = 4;
+
+ const uint32_t *tbl24_p = (const uint32_t *)lpm->tbl24;
+ uint32_t tbl_entries[4] = {
+ tbl24_p[((uint32_t)ip[0]) >> 8],
+ tbl24_p[((uint32_t)ip[1]) >> 8],
+ tbl24_p[((uint32_t)ip[2]) >> 8],
+ tbl24_p[((uint32_t)ip[3]) >> 8],
+ };
+ vuint32m1_t vtbl_entry = __riscv_vle32_v_u32m1(tbl_entries, vl);
+
+ vbool32_t mask = __riscv_vmseq_vx_u32m1_b32(
+ __riscv_vand_vx_u32m1(vtbl_entry, RTE_LPM_VALID_EXT_ENTRY_BITMASK, vl),
+ RTE_LPM_VALID_EXT_ENTRY_BITMASK, vl);
+
+ vuint32m1_t vtbl8_index = __riscv_vsll_vx_u32m1(
+ __riscv_vadd_vv_u32m1(
+ __riscv_vsll_vx_u32m1(__riscv_vand_vx_u32m1(vtbl_entry, 0x00FFFFFF, vl), 8, vl),
+ __riscv_vand_vx_u32m1(
+ __riscv_vle32_v_u32m1((const uint32_t *)&ip, vl), 0x000000FF, vl),
+ vl),
+ 2, vl);
+
+ vtbl_entry = __riscv_vluxei32_v_u32m1_mu(
+ mask, vtbl_entry, (const uint32_t *)(lpm->tbl8), vtbl8_index, vl);
+
+ vuint32m1_t vnext_hop = __riscv_vand_vx_u32m1(vtbl_entry, 0x00FFFFFF, vl);
+ mask = __riscv_vmseq_vx_u32m1_b32(
+ __riscv_vand_vx_u32m1(vtbl_entry, RTE_LPM_LOOKUP_SUCCESS, vl), 0, vl);
+
+ vnext_hop = __riscv_vmerge_vxm_u32m1(vnext_hop, defv, mask, vl);
+
+ __riscv_vse32_v_u32m1(hop, vnext_hop, vl);
+}
+
+static inline void rte_lpm_lookupx4(
+ const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], uint32_t defv)
+{
+ lpm_lookupx4_impl(lpm, ip, hop, defv);
+}
+
+RTE_INIT(rte_lpm_init_alg)
+{
+ lpm_lookupx4_impl = rte_cpu_get_flag_enabled(RTE_CPUFLAG_RISCV_ISA_V)
+ ? rte_lpm_lookupx4_rvv
+ : rte_lpm_lookupx4_scalar;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_LPM_RVV_H_ */
--
2.49.0
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 3/3] riscv: override machine_args only when default
2025-05-28 16:57 [PATCH 1/3] config/riscv: detect V extension uk7b
` (2 preceding siblings ...)
2025-06-04 11:49 ` [PATCH v2 2/3] lib/lpm: R-V V rte_lpm_lookupx4 uk7b
@ 2025-06-04 11:49 ` uk7b
2025-06-04 13:07 ` [PATCH v2 0/3] Add RISC-V V extension detection and LPM optimization uk7b
` (7 subsequent siblings)
11 siblings, 0 replies; 19+ messages in thread
From: uk7b @ 2025-06-04 11:49 UTC (permalink / raw)
To: dev; +Cc: sunyuechi, Stanislaw Kardach, Bruce Richardson
From: sunyuechi <sunyuechi@iscas.ac.cn>
Support using -Dcpu_instruction_set=rv64gcv to enable V extension.
Signed-off-by: sunyuechi <sunyuechi@iscas.ac.cn>
---
config/riscv/meson.build | 2 ++
1 file changed, 2 insertions(+)
diff --git a/config/riscv/meson.build b/config/riscv/meson.build
index e3694cf2e6..1036a86d05 100644
--- a/config/riscv/meson.build
+++ b/config/riscv/meson.build
@@ -111,6 +111,7 @@ arch_config = arch_config[arch_id]
# Concatenate flags respecting priorities.
dpdk_flags = flags_common + vendor_config['flags'] + arch_config.get('flags', [])
+if (cpu_instruction_set == 'rv64gc')
# apply supported machine args
machine_args = [] # Clear previous machine args
foreach flag: arch_config['machine_args']
@@ -118,6 +119,7 @@ foreach flag: arch_config['machine_args']
machine_args += flag
endif
endforeach
+endif
# check if we can do buildtime detection of extensions supported by the target
riscv_extension_macros = false
--
2.49.0
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 0/3] Add RISC-V V extension detection and LPM optimization
2025-05-28 16:57 [PATCH 1/3] config/riscv: detect V extension uk7b
` (3 preceding siblings ...)
2025-06-04 11:49 ` [PATCH v2 3/3] riscv: override machine_args only when default uk7b
@ 2025-06-04 13:07 ` uk7b
2025-06-04 13:16 ` 孙越池
2025-06-04 13:07 ` [PATCH v2 1/3] config/riscv: detect V extension uk7b
` (6 subsequent siblings)
11 siblings, 1 reply; 19+ messages in thread
From: uk7b @ 2025-06-04 13:07 UTC (permalink / raw)
To: dev; +Cc: sunyuechi
From: sunyuechi <sunyuechi@iscas.ac.cn>
This patch series adds support for the RISC-V Vector (V) extension and provides
an optimized implementation of `rte_lpm_lookupx4` using RVV. It includes runtime
detection of the V extension, conditional compilation based on compiler support
for RVV intrinsics.
Test results using lpm_perf_autotest on BPI-F3:
scalar: 5.7 cycles
rvv: 2.4 cycles
### v2:
- Improved commit messages.
sunyuechi (3):
config/riscv: detect V extension
lib/lpm: R-V V rte_lpm_lookupx4
riscv: override machine_args only when default
MAINTAINERS | 2 +
config/riscv/meson.build | 27 ++++++++++++
lib/lpm/meson.build | 1 +
lib/lpm/rte_lpm.h | 2 +
lib/lpm/rte_lpm_rvv.h | 91 ++++++++++++++++++++++++++++++++++++++++
5 files changed, 123 insertions(+)
create mode 100644 lib/lpm/rte_lpm_rvv.h
--
2.49.0
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v2 0/3] Add RISC-V V extension detection and LPM optimization
2025-06-04 13:07 ` [PATCH v2 0/3] Add RISC-V V extension detection and LPM optimization uk7b
@ 2025-06-04 13:16 ` 孙越池
0 siblings, 0 replies; 19+ messages in thread
From: 孙越池 @ 2025-06-04 13:16 UTC (permalink / raw)
To: uk7b, dev
The previous v2 patch incorrectly used --in-reply-to, which caused a warning on Patchwork. This update only corrects the Reply-To field.
> -----原始邮件-----
> 发件人: uk7b@foxmail.com
> 发送时间: 2025-06-04 21:07:33 (星期三)
> 收件人: dev@dpdk.org
> 抄送: sunyuechi <sunyuechi@iscas.ac.cn>
> 主题: [PATCH v2 0/3] Add RISC-V V extension detection and LPM optimization
>
> From: sunyuechi <sunyuechi@iscas.ac.cn>
>
> This patch series adds support for the RISC-V Vector (V) extension and provides
> an optimized implementation of `rte_lpm_lookupx4` using RVV. It includes runtime
> detection of the V extension, conditional compilation based on compiler support
> for RVV intrinsics.
>
> Test results using lpm_perf_autotest on BPI-F3:
> scalar: 5.7 cycles
> rvv: 2.4 cycles
>
> ### v2:
> - Improved commit messages.
>
> sunyuechi (3):
> config/riscv: detect V extension
> lib/lpm: R-V V rte_lpm_lookupx4
> riscv: override machine_args only when default
>
> MAINTAINERS | 2 +
> config/riscv/meson.build | 27 ++++++++++++
> lib/lpm/meson.build | 1 +
> lib/lpm/rte_lpm.h | 2 +
> lib/lpm/rte_lpm_rvv.h | 91 ++++++++++++++++++++++++++++++++++++++++
> 5 files changed, 123 insertions(+)
> create mode 100644 lib/lpm/rte_lpm_rvv.h
>
> --
> 2.49.0
</sunyuechi@iscas.ac.cn></sunyuechi@iscas.ac.cn>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 1/3] config/riscv: detect V extension
2025-05-28 16:57 [PATCH 1/3] config/riscv: detect V extension uk7b
` (4 preceding siblings ...)
2025-06-04 13:07 ` [PATCH v2 0/3] Add RISC-V V extension detection and LPM optimization uk7b
@ 2025-06-04 13:07 ` uk7b
2025-06-04 13:07 ` [PATCH v2 2/3] lib/lpm: R-V V rte_lpm_lookupx4 uk7b
` (5 subsequent siblings)
11 siblings, 0 replies; 19+ messages in thread
From: uk7b @ 2025-06-04 13:07 UTC (permalink / raw)
To: dev; +Cc: sunyuechi, Stanislaw Kardach, Bruce Richardson
From: sunyuechi <sunyuechi@iscas.ac.cn>
This patch is derived from "config/riscv: detect presence of Zbc
extension with modifications".
The RISC-V C api defines architecture extension test macros
These let us detect whether the V extension is supported on the
compiler and -march we're building with. The C api also defines V
intrinsics we can use rather than inline assembly on newer versions of
GCC (14.1.0+) and Clang (18.1.0+).
If the V extension and intrinsics are both present and we can detect
the V extension at runtime, we define a flag, RTE_RISCV_FEATURE_V.
Signed-off-by: sunyuechi <sunyuechi@iscas.ac.cn>
---
config/riscv/meson.build | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/config/riscv/meson.build b/config/riscv/meson.build
index 7562c6cb99..e3694cf2e6 100644
--- a/config/riscv/meson.build
+++ b/config/riscv/meson.build
@@ -119,6 +119,31 @@ foreach flag: arch_config['machine_args']
endif
endforeach
+# check if we can do buildtime detection of extensions supported by the target
+riscv_extension_macros = false
+if (cc.get_define('__riscv_arch_test', args: machine_args) == '1')
+ message('Detected architecture extension test macros')
+ riscv_extension_macros = true
+else
+ warning('RISC-V architecture extension test macros not available. Build-time detection of extensions not possible')
+endif
+
+# detect extensions
+# Requires intrinsics available in GCC 14.1.0+ and Clang 18.1.0+
+if (riscv_extension_macros and
+ (cc.get_define('__riscv_vector', args: machine_args) != ''))
+ if ((cc.get_id() == 'gcc' and cc.version().version_compare('>=14.1.0'))
+ or (cc.get_id() == 'clang' and cc.version().version_compare('>=18.1.0')))
+ if (cc.compiles('''#include <riscv_vector.h>
+ int main(void) { size_t vl = __riscv_vsetvl_e32m1(1); }''', args: machine_args))
+ message('Compiling with the V extension')
+ machine_args += ['-DRTE_RISCV_FEATURE_V']
+ endif
+ else
+ warning('Detected V extension but cannot use because intrinsics are not available (present in GCC 14.1.0+ and Clang 18.1.0+)')
+ endif
+endif
+
# apply flags
foreach flag: dpdk_flags
if flag.length() > 0
--
2.49.0
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 2/3] lib/lpm: R-V V rte_lpm_lookupx4
2025-05-28 16:57 [PATCH 1/3] config/riscv: detect V extension uk7b
` (5 preceding siblings ...)
2025-06-04 13:07 ` [PATCH v2 1/3] config/riscv: detect V extension uk7b
@ 2025-06-04 13:07 ` uk7b
2025-06-04 13:07 ` [PATCH v2 3/3] riscv: override machine_args only when default uk7b
` (4 subsequent siblings)
11 siblings, 0 replies; 19+ messages in thread
From: uk7b @ 2025-06-04 13:07 UTC (permalink / raw)
To: dev
Cc: sunyuechi, Thomas Monjalon, Bruce Richardson, Vladimir Medvedkin,
Stanislaw Kardach
From: sunyuechi <sunyuechi@iscas.ac.cn>
Test results using lpm_perf_autotest on BPI-F3:
scalar: 5.7 cycles
rvv: 2.4 cycles
The best way to call this RVV function is to follow the approach used in
lib/fib, where all architectures initialize a function pointer in a
unified way. However, other architectures in lib/lpm do not follow this
pattern. Therefore, to avoid affecting other architectures, this commit
does not modify lib/lpm/rte_lpm.c.
Unifying the code style between lpm and fib may be worth considering
in the future.
Signed-off-by: sunyuechi <sunyuechi@iscas.ac.cn>
---
MAINTAINERS | 2 +
lib/lpm/meson.build | 1 +
lib/lpm/rte_lpm.h | 2 +
lib/lpm/rte_lpm_rvv.h | 91 +++++++++++++++++++++++++++++++++++++++++++
4 files changed, 96 insertions(+)
create mode 100644 lib/lpm/rte_lpm_rvv.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 3e16789250..0f207ac129 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -340,6 +340,8 @@ M: Stanislaw Kardach <stanislaw.kardach@gmail.com>
F: config/riscv/
F: doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
F: lib/eal/riscv/
+M: sunyuechi <sunyuechi@iscas.ac.cn>
+F: lib/**/*rvv*
Intel x86
M: Bruce Richardson <bruce.richardson@intel.com>
diff --git a/lib/lpm/meson.build b/lib/lpm/meson.build
index fae4f79fb9..09133061e5 100644
--- a/lib/lpm/meson.build
+++ b/lib/lpm/meson.build
@@ -17,6 +17,7 @@ indirect_headers += files(
'rte_lpm_scalar.h',
'rte_lpm_sse.h',
'rte_lpm_sve.h',
+ 'rte_lpm_rvv.h',
)
deps += ['hash']
deps += ['rcu']
diff --git a/lib/lpm/rte_lpm.h b/lib/lpm/rte_lpm.h
index 7df64f06b1..b06517206f 100644
--- a/lib/lpm/rte_lpm.h
+++ b/lib/lpm/rte_lpm.h
@@ -408,6 +408,8 @@ rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4],
#include "rte_lpm_altivec.h"
#elif defined(RTE_ARCH_X86)
#include "rte_lpm_sse.h"
+#elif defined(RTE_ARCH_RISCV) && defined(RTE_RISCV_FEATURE_V)
+#include "rte_lpm_rvv.h"
#else
#include "rte_lpm_scalar.h"
#endif
diff --git a/lib/lpm/rte_lpm_rvv.h b/lib/lpm/rte_lpm_rvv.h
new file mode 100644
index 0000000000..e39ade3f07
--- /dev/null
+++ b/lib/lpm/rte_lpm_rvv.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) 2025 Institute of Software Chinese Academy of Sciences (ISCAS).
+ */
+
+#ifndef _RTE_LPM_RVV_H_
+#define _RTE_LPM_RVV_H_
+
+#include <rte_vect.h>
+
+#include <rte_cpuflags.h>
+#include <riscv_vector.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RTE_LPM_LOOKUP_SUCCESS 0x01000000
+#define RTE_LPM_VALID_EXT_ENTRY_BITMASK 0x03000000
+
+typedef void (*lpm_lookupx4_fn)(const struct rte_lpm *, xmm_t, uint32_t *, uint32_t);
+
+static lpm_lookupx4_fn lpm_lookupx4_impl;
+
+static inline void rte_lpm_lookupx4_scalar(
+ const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], uint32_t defv)
+{
+ uint32_t nh;
+ int ret;
+
+ for (int i = 0; i < 4; i++) {
+ ret = rte_lpm_lookup(lpm, ip[i], &nh);
+ hop[i] = (ret == 0) ? nh : defv;
+ }
+}
+
+static inline void rte_lpm_lookupx4_rvv(
+ const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], uint32_t defv)
+{
+ size_t vl = 4;
+
+ const uint32_t *tbl24_p = (const uint32_t *)lpm->tbl24;
+ uint32_t tbl_entries[4] = {
+ tbl24_p[((uint32_t)ip[0]) >> 8],
+ tbl24_p[((uint32_t)ip[1]) >> 8],
+ tbl24_p[((uint32_t)ip[2]) >> 8],
+ tbl24_p[((uint32_t)ip[3]) >> 8],
+ };
+ vuint32m1_t vtbl_entry = __riscv_vle32_v_u32m1(tbl_entries, vl);
+
+ vbool32_t mask = __riscv_vmseq_vx_u32m1_b32(
+ __riscv_vand_vx_u32m1(vtbl_entry, RTE_LPM_VALID_EXT_ENTRY_BITMASK, vl),
+ RTE_LPM_VALID_EXT_ENTRY_BITMASK, vl);
+
+ vuint32m1_t vtbl8_index = __riscv_vsll_vx_u32m1(
+ __riscv_vadd_vv_u32m1(
+ __riscv_vsll_vx_u32m1(__riscv_vand_vx_u32m1(vtbl_entry, 0x00FFFFFF, vl), 8, vl),
+ __riscv_vand_vx_u32m1(
+ __riscv_vle32_v_u32m1((const uint32_t *)&ip, vl), 0x000000FF, vl),
+ vl),
+ 2, vl);
+
+ vtbl_entry = __riscv_vluxei32_v_u32m1_mu(
+ mask, vtbl_entry, (const uint32_t *)(lpm->tbl8), vtbl8_index, vl);
+
+ vuint32m1_t vnext_hop = __riscv_vand_vx_u32m1(vtbl_entry, 0x00FFFFFF, vl);
+ mask = __riscv_vmseq_vx_u32m1_b32(
+ __riscv_vand_vx_u32m1(vtbl_entry, RTE_LPM_LOOKUP_SUCCESS, vl), 0, vl);
+
+ vnext_hop = __riscv_vmerge_vxm_u32m1(vnext_hop, defv, mask, vl);
+
+ __riscv_vse32_v_u32m1(hop, vnext_hop, vl);
+}
+
+static inline void rte_lpm_lookupx4(
+ const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], uint32_t defv)
+{
+ lpm_lookupx4_impl(lpm, ip, hop, defv);
+}
+
+RTE_INIT(rte_lpm_init_alg)
+{
+ lpm_lookupx4_impl = rte_cpu_get_flag_enabled(RTE_CPUFLAG_RISCV_ISA_V)
+ ? rte_lpm_lookupx4_rvv
+ : rte_lpm_lookupx4_scalar;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_LPM_RVV_H_ */
--
2.49.0
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 3/3] riscv: override machine_args only when default
2025-05-28 16:57 [PATCH 1/3] config/riscv: detect V extension uk7b
` (6 preceding siblings ...)
2025-06-04 13:07 ` [PATCH v2 2/3] lib/lpm: R-V V rte_lpm_lookupx4 uk7b
@ 2025-06-04 13:07 ` uk7b
2025-06-04 15:47 ` [PATCH v3 0/3] Add RISC-V V extension detection and LPM optimization uk7b
` (3 subsequent siblings)
11 siblings, 0 replies; 19+ messages in thread
From: uk7b @ 2025-06-04 13:07 UTC (permalink / raw)
To: dev; +Cc: sunyuechi, Stanislaw Kardach, Bruce Richardson
From: sunyuechi <sunyuechi@iscas.ac.cn>
Support using -Dcpu_instruction_set=rv64gcv to enable V extension.
Signed-off-by: sunyuechi <sunyuechi@iscas.ac.cn>
---
config/riscv/meson.build | 2 ++
1 file changed, 2 insertions(+)
diff --git a/config/riscv/meson.build b/config/riscv/meson.build
index e3694cf2e6..1036a86d05 100644
--- a/config/riscv/meson.build
+++ b/config/riscv/meson.build
@@ -111,6 +111,7 @@ arch_config = arch_config[arch_id]
# Concatenate flags respecting priorities.
dpdk_flags = flags_common + vendor_config['flags'] + arch_config.get('flags', [])
+if (cpu_instruction_set == 'rv64gc')
# apply supported machine args
machine_args = [] # Clear previous machine args
foreach flag: arch_config['machine_args']
@@ -118,6 +119,7 @@ foreach flag: arch_config['machine_args']
machine_args += flag
endif
endforeach
+endif
# check if we can do buildtime detection of extensions supported by the target
riscv_extension_macros = false
--
2.49.0
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 0/3] Add RISC-V V extension detection and LPM optimization
2025-05-28 16:57 [PATCH 1/3] config/riscv: detect V extension uk7b
` (7 preceding siblings ...)
2025-06-04 13:07 ` [PATCH v2 3/3] riscv: override machine_args only when default uk7b
@ 2025-06-04 15:47 ` uk7b
[not found] ` <20250604154720.3078131-1-uk7b@foxmail.com>
` (2 subsequent siblings)
11 siblings, 0 replies; 19+ messages in thread
From: uk7b @ 2025-06-04 15:47 UTC (permalink / raw)
To: dev; +Cc: sunyuechi
From: sunyuechi <sunyuechi@iscas.ac.cn>
This patch series adds support for the RISC-V Vector (V) extension and provides
an optimized implementation of `rte_lpm_lookupx4` using RVV. It includes runtime
detection of the V extension, conditional compilation based on compiler support
for RVV intrinsics.
Test results using lpm_perf_autotest on BPI-F3:
scalar: 5.7 cycles
rvv: 2.4 cycles
v3:
- Due to previous SMTP server restrictions, patches could not be sent as a proper series.
This version re-sends the same patches as a series. No code changes.
v2:
- Improved commit messages.
sunyuechi (3):
config/riscv: detect V extension
lib/lpm: R-V V rte_lpm_lookupx4
riscv: override machine_args only when default
MAINTAINERS | 2 +
config/riscv/meson.build | 27 ++++++++++++
lib/lpm/meson.build | 1 +
lib/lpm/rte_lpm.h | 2 +
lib/lpm/rte_lpm_rvv.h | 91 ++++++++++++++++++++++++++++++++++++++++
5 files changed, 123 insertions(+)
create mode 100644 lib/lpm/rte_lpm_rvv.h
--
2.49.0
^ permalink raw reply [flat|nested] 19+ messages in thread
[parent not found: <20250604154720.3078131-1-uk7b@foxmail.com>]
* [PATCH v3 1/3] config/riscv: detect V extension
[not found] ` <20250604154720.3078131-1-uk7b@foxmail.com>
@ 2025-06-04 15:47 ` uk7b
2025-06-04 15:47 ` [PATCH v3 2/3] lib/lpm: R-V V rte_lpm_lookupx4 uk7b
2025-06-04 15:47 ` [PATCH v3 3/3] riscv: override machine_args only when default uk7b
2 siblings, 0 replies; 19+ messages in thread
From: uk7b @ 2025-06-04 15:47 UTC (permalink / raw)
To: dev; +Cc: sunyuechi, Stanislaw Kardach, Bruce Richardson
From: sunyuechi <sunyuechi@iscas.ac.cn>
This patch is derived from "config/riscv: detect presence of Zbc
extension with modifications".
The RISC-V C api defines architecture extension test macros
These let us detect whether the V extension is supported on the
compiler and -march we're building with. The C api also defines V
intrinsics we can use rather than inline assembly on newer versions of
GCC (14.1.0+) and Clang (18.1.0+).
If the V extension and intrinsics are both present and we can detect
the V extension at runtime, we define a flag, RTE_RISCV_FEATURE_V.
Signed-off-by: sunyuechi <sunyuechi@iscas.ac.cn>
---
config/riscv/meson.build | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/config/riscv/meson.build b/config/riscv/meson.build
index 7562c6cb99..e3694cf2e6 100644
--- a/config/riscv/meson.build
+++ b/config/riscv/meson.build
@@ -119,6 +119,31 @@ foreach flag: arch_config['machine_args']
endif
endforeach
+# check if we can do buildtime detection of extensions supported by the target
+riscv_extension_macros = false
+if (cc.get_define('__riscv_arch_test', args: machine_args) == '1')
+ message('Detected architecture extension test macros')
+ riscv_extension_macros = true
+else
+ warning('RISC-V architecture extension test macros not available. Build-time detection of extensions not possible')
+endif
+
+# detect extensions
+# Requires intrinsics available in GCC 14.1.0+ and Clang 18.1.0+
+if (riscv_extension_macros and
+ (cc.get_define('__riscv_vector', args: machine_args) != ''))
+ if ((cc.get_id() == 'gcc' and cc.version().version_compare('>=14.1.0'))
+ or (cc.get_id() == 'clang' and cc.version().version_compare('>=18.1.0')))
+ if (cc.compiles('''#include <riscv_vector.h>
+ int main(void) { size_t vl = __riscv_vsetvl_e32m1(1); }''', args: machine_args))
+ message('Compiling with the V extension')
+ machine_args += ['-DRTE_RISCV_FEATURE_V']
+ endif
+ else
+ warning('Detected V extension but cannot use because intrinsics are not available (present in GCC 14.1.0+ and Clang 18.1.0+)')
+ endif
+endif
+
# apply flags
foreach flag: dpdk_flags
if flag.length() > 0
--
2.49.0
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 2/3] lib/lpm: R-V V rte_lpm_lookupx4
[not found] ` <20250604154720.3078131-1-uk7b@foxmail.com>
2025-06-04 15:47 ` [PATCH v3 1/3] config/riscv: detect V extension uk7b
@ 2025-06-04 15:47 ` uk7b
2025-06-04 15:47 ` [PATCH v3 3/3] riscv: override machine_args only when default uk7b
2 siblings, 0 replies; 19+ messages in thread
From: uk7b @ 2025-06-04 15:47 UTC (permalink / raw)
To: dev
Cc: sunyuechi, Thomas Monjalon, Bruce Richardson, Vladimir Medvedkin,
Stanislaw Kardach
From: sunyuechi <sunyuechi@iscas.ac.cn>
Test results using lpm_perf_autotest on BPI-F3:
scalar: 5.7 cycles
rvv: 2.4 cycles
The best way to call this RVV function is to follow the approach used in
lib/fib, where all architectures initialize a function pointer in a
unified way. However, other architectures in lib/lpm do not follow this
pattern. Therefore, to avoid affecting other architectures, this commit
does not modify lib/lpm/rte_lpm.c.
Unifying the code style between lpm and fib may be worth considering
in the future.
Signed-off-by: sunyuechi <sunyuechi@iscas.ac.cn>
---
MAINTAINERS | 2 +
lib/lpm/meson.build | 1 +
lib/lpm/rte_lpm.h | 2 +
lib/lpm/rte_lpm_rvv.h | 91 +++++++++++++++++++++++++++++++++++++++++++
4 files changed, 96 insertions(+)
create mode 100644 lib/lpm/rte_lpm_rvv.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 3e16789250..0f207ac129 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -340,6 +340,8 @@ M: Stanislaw Kardach <stanislaw.kardach@gmail.com>
F: config/riscv/
F: doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
F: lib/eal/riscv/
+M: sunyuechi <sunyuechi@iscas.ac.cn>
+F: lib/**/*rvv*
Intel x86
M: Bruce Richardson <bruce.richardson@intel.com>
diff --git a/lib/lpm/meson.build b/lib/lpm/meson.build
index fae4f79fb9..09133061e5 100644
--- a/lib/lpm/meson.build
+++ b/lib/lpm/meson.build
@@ -17,6 +17,7 @@ indirect_headers += files(
'rte_lpm_scalar.h',
'rte_lpm_sse.h',
'rte_lpm_sve.h',
+ 'rte_lpm_rvv.h',
)
deps += ['hash']
deps += ['rcu']
diff --git a/lib/lpm/rte_lpm.h b/lib/lpm/rte_lpm.h
index 7df64f06b1..b06517206f 100644
--- a/lib/lpm/rte_lpm.h
+++ b/lib/lpm/rte_lpm.h
@@ -408,6 +408,8 @@ rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4],
#include "rte_lpm_altivec.h"
#elif defined(RTE_ARCH_X86)
#include "rte_lpm_sse.h"
+#elif defined(RTE_ARCH_RISCV) && defined(RTE_RISCV_FEATURE_V)
+#include "rte_lpm_rvv.h"
#else
#include "rte_lpm_scalar.h"
#endif
diff --git a/lib/lpm/rte_lpm_rvv.h b/lib/lpm/rte_lpm_rvv.h
new file mode 100644
index 0000000000..e39ade3f07
--- /dev/null
+++ b/lib/lpm/rte_lpm_rvv.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) 2025 Institute of Software Chinese Academy of Sciences (ISCAS).
+ */
+
+#ifndef _RTE_LPM_RVV_H_
+#define _RTE_LPM_RVV_H_
+
+#include <rte_vect.h>
+
+#include <rte_cpuflags.h>
+#include <riscv_vector.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RTE_LPM_LOOKUP_SUCCESS 0x01000000
+#define RTE_LPM_VALID_EXT_ENTRY_BITMASK 0x03000000
+
+typedef void (*lpm_lookupx4_fn)(const struct rte_lpm *, xmm_t, uint32_t *, uint32_t);
+
+static lpm_lookupx4_fn lpm_lookupx4_impl;
+
+static inline void rte_lpm_lookupx4_scalar(
+ const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], uint32_t defv)
+{
+ uint32_t nh;
+ int ret;
+
+ for (int i = 0; i < 4; i++) {
+ ret = rte_lpm_lookup(lpm, ip[i], &nh);
+ hop[i] = (ret == 0) ? nh : defv;
+ }
+}
+
+static inline void rte_lpm_lookupx4_rvv(
+ const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], uint32_t defv)
+{
+ size_t vl = 4;
+
+ const uint32_t *tbl24_p = (const uint32_t *)lpm->tbl24;
+ uint32_t tbl_entries[4] = {
+ tbl24_p[((uint32_t)ip[0]) >> 8],
+ tbl24_p[((uint32_t)ip[1]) >> 8],
+ tbl24_p[((uint32_t)ip[2]) >> 8],
+ tbl24_p[((uint32_t)ip[3]) >> 8],
+ };
+ vuint32m1_t vtbl_entry = __riscv_vle32_v_u32m1(tbl_entries, vl);
+
+ vbool32_t mask = __riscv_vmseq_vx_u32m1_b32(
+ __riscv_vand_vx_u32m1(vtbl_entry, RTE_LPM_VALID_EXT_ENTRY_BITMASK, vl),
+ RTE_LPM_VALID_EXT_ENTRY_BITMASK, vl);
+
+ vuint32m1_t vtbl8_index = __riscv_vsll_vx_u32m1(
+ __riscv_vadd_vv_u32m1(
+ __riscv_vsll_vx_u32m1(__riscv_vand_vx_u32m1(vtbl_entry, 0x00FFFFFF, vl), 8, vl),
+ __riscv_vand_vx_u32m1(
+ __riscv_vle32_v_u32m1((const uint32_t *)&ip, vl), 0x000000FF, vl),
+ vl),
+ 2, vl);
+
+ vtbl_entry = __riscv_vluxei32_v_u32m1_mu(
+ mask, vtbl_entry, (const uint32_t *)(lpm->tbl8), vtbl8_index, vl);
+
+ vuint32m1_t vnext_hop = __riscv_vand_vx_u32m1(vtbl_entry, 0x00FFFFFF, vl);
+ mask = __riscv_vmseq_vx_u32m1_b32(
+ __riscv_vand_vx_u32m1(vtbl_entry, RTE_LPM_LOOKUP_SUCCESS, vl), 0, vl);
+
+ vnext_hop = __riscv_vmerge_vxm_u32m1(vnext_hop, defv, mask, vl);
+
+ __riscv_vse32_v_u32m1(hop, vnext_hop, vl);
+}
+
+static inline void rte_lpm_lookupx4(
+ const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], uint32_t defv)
+{
+ lpm_lookupx4_impl(lpm, ip, hop, defv);
+}
+
+RTE_INIT(rte_lpm_init_alg)
+{
+ lpm_lookupx4_impl = rte_cpu_get_flag_enabled(RTE_CPUFLAG_RISCV_ISA_V)
+ ? rte_lpm_lookupx4_rvv
+ : rte_lpm_lookupx4_scalar;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_LPM_RVV_H_ */
--
2.49.0
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 3/3] riscv: override machine_args only when default
[not found] ` <20250604154720.3078131-1-uk7b@foxmail.com>
2025-06-04 15:47 ` [PATCH v3 1/3] config/riscv: detect V extension uk7b
2025-06-04 15:47 ` [PATCH v3 2/3] lib/lpm: R-V V rte_lpm_lookupx4 uk7b
@ 2025-06-04 15:47 ` uk7b
2 siblings, 0 replies; 19+ messages in thread
From: uk7b @ 2025-06-04 15:47 UTC (permalink / raw)
To: dev; +Cc: sunyuechi, Stanislaw Kardach, Bruce Richardson
From: sunyuechi <sunyuechi@iscas.ac.cn>
Support using -Dcpu_instruction_set=rv64gcv to enable V extension.
Signed-off-by: sunyuechi <sunyuechi@iscas.ac.cn>
---
config/riscv/meson.build | 2 ++
1 file changed, 2 insertions(+)
diff --git a/config/riscv/meson.build b/config/riscv/meson.build
index e3694cf2e6..1036a86d05 100644
--- a/config/riscv/meson.build
+++ b/config/riscv/meson.build
@@ -111,6 +111,7 @@ arch_config = arch_config[arch_id]
# Concatenate flags respecting priorities.
dpdk_flags = flags_common + vendor_config['flags'] + arch_config.get('flags', [])
+if (cpu_instruction_set == 'rv64gc')
# apply supported machine args
machine_args = [] # Clear previous machine args
foreach flag: arch_config['machine_args']
@@ -118,6 +119,7 @@ foreach flag: arch_config['machine_args']
machine_args += flag
endif
endforeach
+endif
# check if we can do buildtime detection of extensions supported by the target
riscv_extension_macros = false
--
2.49.0
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v4 0/3] [PATCH v4 0/3] Add RISC-V V extension detection and LPM optimization
2025-05-28 16:57 [PATCH 1/3] config/riscv: detect V extension uk7b
` (9 preceding siblings ...)
[not found] ` <20250604154720.3078131-1-uk7b@foxmail.com>
@ 2025-06-05 10:58 ` uk7b
[not found] ` <20250605105844.3931758-1-uk7b@foxmail.com>
11 siblings, 0 replies; 19+ messages in thread
From: uk7b @ 2025-06-05 10:58 UTC (permalink / raw)
To: dev; +Cc: Sun Yuechi
From: Sun Yuechi <sunyuechi@iscas.ac.cn>
This patch series adds support for the RISC-V Vector (V) extension and
provides an optimized implementation of `rte_lpm_lookupx4` using RVV.
- Test: app/test/lpm_perf_autotest
- Platform: Banana Pi BPI-F3
- SoC: Spacemit X60 (8 cores with Vector extension)
- CPU Frequency: up to 1.6 GHz
- Cache: 256 KiB L1d ×8, 256 KiB L1i ×8, 1 MiB L2 ×2
- Memory: 16 GiB
- Kernel: Linux 6.6.36
- Compiler: GCC 14.2.0 (with RVV intrinsic support)
Test results(LPM LookupX4):
scalar: 5.7 cycles
rvv: 4.6 cycles
v4:
- Keep the LPM code consistent, use a static inline function instead of runtime detection.
- Update the commit message.
- Update the .mailmap file.
v3:
- Due to previous SMTP server restrictions, patches could not be sent as a proper series.
This version re-sends the same patches as a series. No code changes.
v2:
- Improved commit messages.
Sun Yuechi (3):
config/riscv: detect V extension
lib/lpm: R-V V rte_lpm_lookupx4
riscv: override machine_args only when default
.mailmap | 1 +
MAINTAINERS | 2 ++
config/riscv/meson.build | 27 +++++++++++++++++
lib/lpm/meson.build | 1 +
lib/lpm/rte_lpm.h | 2 ++
lib/lpm/rte_lpm_rvv.h | 62 ++++++++++++++++++++++++++++++++++++++++
6 files changed, 95 insertions(+)
create mode 100644 lib/lpm/rte_lpm_rvv.h
--
2.49.0
^ permalink raw reply [flat|nested] 19+ messages in thread
[parent not found: <20250605105844.3931758-1-uk7b@foxmail.com>]
* [PATCH v4 1/3] config/riscv: detect V extension
[not found] ` <20250605105844.3931758-1-uk7b@foxmail.com>
@ 2025-06-05 10:58 ` uk7b
2025-06-05 10:58 ` [PATCH v4 2/3] lib/lpm: R-V V rte_lpm_lookupx4 uk7b
2025-06-05 10:58 ` [PATCH v4 3/3] riscv: override machine_args only when default uk7b
2 siblings, 0 replies; 19+ messages in thread
From: uk7b @ 2025-06-05 10:58 UTC (permalink / raw)
To: dev; +Cc: Sun Yuechi, Thomas Monjalon, Stanislaw Kardach, Bruce Richardson
From: Sun Yuechi <sunyuechi@iscas.ac.cn>
This patch is derived from "config/riscv: detect presence of Zbc
extension with modifications".
The RISC-V C api defines architecture extension test macros
These let us detect whether the V extension is supported on the
compiler and -march we're building with. The C api also defines V
intrinsics we can use rather than inline assembly on newer versions of
GCC (14.1.0+) and Clang (18.1.0+).
If the V extension and intrinsics are both present and we can detect
the V extension at runtime, we define a flag, RTE_RISCV_FEATURE_V.
Signed-off-by: Sun Yuechi <sunyuechi@iscas.ac.cn>
---
.mailmap | 1 +
config/riscv/meson.build | 25 +++++++++++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/.mailmap b/.mailmap
index c65872cd9f..b635eb645a 100644
--- a/.mailmap
+++ b/.mailmap
@@ -1508,6 +1508,7 @@ Sunil Kumar Kori <skori@marvell.com> <skori@mavell.com> <sunil.kori@nxp.com>
Sunil Pai G <sunil.pai.g@intel.com>
Sunil Uttarwar <sunilprakashrao.uttarwar@amd.com>
Sun Jiajia <sunx.jiajia@intel.com>
+Sun Yuechi <sunyuechi@iscas.ac.cn> <uk7b@foxmail.com>
Sunyang Wu <sunyang.wu@jaguarmicro.com>
Surabhi Boob <surabhi.boob@intel.com>
Suyang Ju <sju@paloaltonetworks.com>
diff --git a/config/riscv/meson.build b/config/riscv/meson.build
index 7562c6cb99..e3694cf2e6 100644
--- a/config/riscv/meson.build
+++ b/config/riscv/meson.build
@@ -119,6 +119,31 @@ foreach flag: arch_config['machine_args']
endif
endforeach
+# check if we can do buildtime detection of extensions supported by the target
+riscv_extension_macros = false
+if (cc.get_define('__riscv_arch_test', args: machine_args) == '1')
+ message('Detected architecture extension test macros')
+ riscv_extension_macros = true
+else
+ warning('RISC-V architecture extension test macros not available. Build-time detection of extensions not possible')
+endif
+
+# detect extensions
+# Requires intrinsics available in GCC 14.1.0+ and Clang 18.1.0+
+if (riscv_extension_macros and
+ (cc.get_define('__riscv_vector', args: machine_args) != ''))
+ if ((cc.get_id() == 'gcc' and cc.version().version_compare('>=14.1.0'))
+ or (cc.get_id() == 'clang' and cc.version().version_compare('>=18.1.0')))
+ if (cc.compiles('''#include <riscv_vector.h>
+ int main(void) { size_t vl = __riscv_vsetvl_e32m1(1); }''', args: machine_args))
+ message('Compiling with the V extension')
+ machine_args += ['-DRTE_RISCV_FEATURE_V']
+ endif
+ else
+ warning('Detected V extension but cannot use because intrinsics are not available (present in GCC 14.1.0+ and Clang 18.1.0+)')
+ endif
+endif
+
# apply flags
foreach flag: dpdk_flags
if flag.length() > 0
--
2.49.0
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v4 2/3] lib/lpm: R-V V rte_lpm_lookupx4
[not found] ` <20250605105844.3931758-1-uk7b@foxmail.com>
2025-06-05 10:58 ` [PATCH v4 1/3] config/riscv: detect V extension uk7b
@ 2025-06-05 10:58 ` uk7b
2025-06-05 10:58 ` [PATCH v4 3/3] riscv: override machine_args only when default uk7b
2 siblings, 0 replies; 19+ messages in thread
From: uk7b @ 2025-06-05 10:58 UTC (permalink / raw)
To: dev
Cc: Sun Yuechi, Thomas Monjalon, Bruce Richardson,
Vladimir Medvedkin, Stanislaw Kardach
From: Sun Yuechi <sunyuechi@iscas.ac.cn>
The initialization of vtbl_entry is not fully vectorized here because
doing so would require __riscv_vluxei32_v_u32m1, which is slower
than the scalar approach in this small-scale scenario.
- Test: app/test/lpm_perf_autotest
- Platform: Banana Pi(BPI-F3)
- SoC: Spacemit X60 (8 cores with Vector extension)
- CPU Frequency: up to 1.6 GHz
- Cache: 256 KiB L1d ×8, 256 KiB L1i ×8, 1 MiB L2 ×2
- Memory: 16 GiB
- Kernel: Linux 6.6.36
- Compiler: GCC 14.2.0 (with RVV intrinsic support)
Test results(LPM LookupX4):
scalar: 5.7 cycles
rvv: 4.6 cycles
Signed-off-by: Sun Yuechi <sunyuechi@iscas.ac.cn>
---
MAINTAINERS | 2 ++
lib/lpm/meson.build | 1 +
lib/lpm/rte_lpm.h | 2 ++
lib/lpm/rte_lpm_rvv.h | 62 +++++++++++++++++++++++++++++++++++++++++++
4 files changed, 67 insertions(+)
create mode 100644 lib/lpm/rte_lpm_rvv.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 3e16789250..0f207ac129 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -340,6 +340,8 @@ M: Stanislaw Kardach <stanislaw.kardach@gmail.com>
F: config/riscv/
F: doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
F: lib/eal/riscv/
+M: sunyuechi <sunyuechi@iscas.ac.cn>
+F: lib/**/*rvv*
Intel x86
M: Bruce Richardson <bruce.richardson@intel.com>
diff --git a/lib/lpm/meson.build b/lib/lpm/meson.build
index fae4f79fb9..09133061e5 100644
--- a/lib/lpm/meson.build
+++ b/lib/lpm/meson.build
@@ -17,6 +17,7 @@ indirect_headers += files(
'rte_lpm_scalar.h',
'rte_lpm_sse.h',
'rte_lpm_sve.h',
+ 'rte_lpm_rvv.h',
)
deps += ['hash']
deps += ['rcu']
diff --git a/lib/lpm/rte_lpm.h b/lib/lpm/rte_lpm.h
index 7df64f06b1..b06517206f 100644
--- a/lib/lpm/rte_lpm.h
+++ b/lib/lpm/rte_lpm.h
@@ -408,6 +408,8 @@ rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4],
#include "rte_lpm_altivec.h"
#elif defined(RTE_ARCH_X86)
#include "rte_lpm_sse.h"
+#elif defined(RTE_ARCH_RISCV) && defined(RTE_RISCV_FEATURE_V)
+#include "rte_lpm_rvv.h"
#else
#include "rte_lpm_scalar.h"
#endif
diff --git a/lib/lpm/rte_lpm_rvv.h b/lib/lpm/rte_lpm_rvv.h
new file mode 100644
index 0000000000..5f48fb2b32
--- /dev/null
+++ b/lib/lpm/rte_lpm_rvv.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) 2025 Institute of Software Chinese Academy of Sciences (ISCAS).
+ */
+
+#ifndef _RTE_LPM_RVV_H_
+#define _RTE_LPM_RVV_H_
+
+#include <rte_vect.h>
+
+#include <rte_cpuflags.h>
+#include <riscv_vector.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RTE_LPM_LOOKUP_SUCCESS 0x01000000
+#define RTE_LPM_VALID_EXT_ENTRY_BITMASK 0x03000000
+
+static inline void rte_lpm_lookupx4(
+ const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], uint32_t defv)
+{
+ size_t vl = 4;
+
+ const uint32_t *tbl24_p = (const uint32_t *)lpm->tbl24;
+ uint32_t tbl_entries[4] = {
+ tbl24_p[((uint32_t)ip[0]) >> 8],
+ tbl24_p[((uint32_t)ip[1]) >> 8],
+ tbl24_p[((uint32_t)ip[2]) >> 8],
+ tbl24_p[((uint32_t)ip[3]) >> 8],
+ };
+ vuint32m1_t vtbl_entry = __riscv_vle32_v_u32m1(tbl_entries, vl);
+
+ vbool32_t mask = __riscv_vmseq_vx_u32m1_b32(
+ __riscv_vand_vx_u32m1(vtbl_entry, RTE_LPM_VALID_EXT_ENTRY_BITMASK, vl),
+ RTE_LPM_VALID_EXT_ENTRY_BITMASK, vl);
+
+ vuint32m1_t vtbl8_index = __riscv_vsll_vx_u32m1(
+ __riscv_vadd_vv_u32m1(
+ __riscv_vsll_vx_u32m1(__riscv_vand_vx_u32m1(vtbl_entry, 0x00FFFFFF, vl), 8, vl),
+ __riscv_vand_vx_u32m1(
+ __riscv_vle32_v_u32m1((const uint32_t *)&ip, vl), 0x000000FF, vl),
+ vl),
+ 2, vl);
+
+ vtbl_entry = __riscv_vluxei32_v_u32m1_mu(
+ mask, vtbl_entry, (const uint32_t *)(lpm->tbl8), vtbl8_index, vl);
+
+ vuint32m1_t vnext_hop = __riscv_vand_vx_u32m1(vtbl_entry, 0x00FFFFFF, vl);
+ mask = __riscv_vmseq_vx_u32m1_b32(
+ __riscv_vand_vx_u32m1(vtbl_entry, RTE_LPM_LOOKUP_SUCCESS, vl), 0, vl);
+
+ vnext_hop = __riscv_vmerge_vxm_u32m1(vnext_hop, defv, mask, vl);
+
+ __riscv_vse32_v_u32m1(hop, vnext_hop, vl);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_LPM_RVV_H_ */
--
2.49.0
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v4 3/3] riscv: override machine_args only when default
[not found] ` <20250605105844.3931758-1-uk7b@foxmail.com>
2025-06-05 10:58 ` [PATCH v4 1/3] config/riscv: detect V extension uk7b
2025-06-05 10:58 ` [PATCH v4 2/3] lib/lpm: R-V V rte_lpm_lookupx4 uk7b
@ 2025-06-05 10:58 ` uk7b
2 siblings, 0 replies; 19+ messages in thread
From: uk7b @ 2025-06-05 10:58 UTC (permalink / raw)
To: dev; +Cc: Sun Yuechi, Stanislaw Kardach, Bruce Richardson
From: Sun Yuechi <sunyuechi@iscas.ac.cn>
Support using -Dcpu_instruction_set=rv64gcv to enable V extension.
Signed-off-by: Sun Yuechi <sunyuechi@iscas.ac.cn>
---
config/riscv/meson.build | 2 ++
1 file changed, 2 insertions(+)
diff --git a/config/riscv/meson.build b/config/riscv/meson.build
index e3694cf2e6..1036a86d05 100644
--- a/config/riscv/meson.build
+++ b/config/riscv/meson.build
@@ -111,6 +111,7 @@ arch_config = arch_config[arch_id]
# Concatenate flags respecting priorities.
dpdk_flags = flags_common + vendor_config['flags'] + arch_config.get('flags', [])
+if (cpu_instruction_set == 'rv64gc')
# apply supported machine args
machine_args = [] # Clear previous machine args
foreach flag: arch_config['machine_args']
@@ -118,6 +119,7 @@ foreach flag: arch_config['machine_args']
machine_args += flag
endif
endforeach
+endif
# check if we can do buildtime detection of extensions supported by the target
riscv_extension_macros = false
--
2.49.0
^ permalink raw reply [flat|nested] 19+ messages in thread