From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AAA9B4677C; Wed, 4 Jun 2025 13:33:51 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3298542D83; Wed, 4 Jun 2025 13:33:50 +0200 (CEST) Received: from out162-62-57-49.mail.qq.com (out162-62-57-49.mail.qq.com [162.62.57.49]) by mails.dpdk.org (Postfix) with UTF8SMTP id 8B86442D7B for ; Wed, 4 Jun 2025 13:33:47 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foxmail.com; s=s201512; t=1749036820; bh=yCM3ebb0HBzSlvM4xEXYz6MBcD70ZkSKjlMZj32w5MM=; h=From:To:Cc:Subject:Date; b=hXx5RtC1bcRcGQr7oaWvVbHfvv5LuuDqE+XAD+GgfBRFiK4k6ARL7hGt099ubUuXs DhgcZciJ2WSo3Y/oMK9eBdJCb3db//ToUtKRHj8zhZWqMwUMDY22lBL/Z4MNxdb4Ik sgw0QzSuVgkUzRHrrEBIIsGd/wekonLZLNSQCtSQ= Received: from localhost.localdomain ([116.139.97.45]) by newxmesmtplogicsvrszgpua8-0.qq.com (NewEsmtp) with SMTP id 866B8A8E; Wed, 04 Jun 2025 19:33:38 +0800 X-QQ-mid: xmsmtpt1749036818tkjnloujm Message-ID: X-QQ-XMAILINFO: NbgegmlEc3JuijsCuJX2N5Ht8kGyFHtu+1e0tax+ipChq/DzX36SMhu5NOPMZG VfFnsZAPq0oou7/qIS40zTENSNdA3A/8uzhZIcGYPyEBezF5Jug223DtolCcAeeaNvxuvS5aYbA4 h1UP/fjhEPIrhudzVoLKTRYEAL9lQ5O8OJmUeKuYmXRjuJ9MMhCJUXJVyCePZ1mV2j3b5pqU0n11 ym0uU83+YHXydARAeOxEgwYXO+BLpuccQjU5PQWn4QrRdsAtgOaqXze/6aQ0qKZ23MEFEnxLWaRV QftdZwjTjPV5WyBrtgcG5mFucKcgN05gfDjoJyXtzxNm37MCZhOC2X1jy/KLt7MgNjezvE/0UwS0 9sEkyEOjI3bejMjg/tLmhAkXHZ0cCBeuF2IjyXy/Ut69oXMzppRpu3oeqRenYCeQYtMDVUBCSuNV Mb8xYVkv6psINWm2t5yeHOiW/b4XLzx4KanxmoOSLY1tHDaYgJkVzXvFllvuS4PVpALseVN+uo9S eaodMtSfpcRG5fbffJXNmASpglp7UWpuXQ9zqkQkE5DOGYwHHmIvV/hkdHFSiyIf5UAY/OyrrbXB 2yq5NaHBvd8St/KKpmL+BLsavfNOatChgdIu++SdmnKBAFlVAubcxQ2fcExCK4ESd3PbnPxznhTj zdXyoKPSiA0gKyPV5vmbFhBhzi9lAMNNFq6U1DkPL83sYHfZYNmUteyGTTbniHa63CCOstQ4AN5v 5MKPHyp6ty5AgPIF6S9TFIucB3nbiQCDdUxvq8mhzq8mLNWj6MXOlP/XCmExR/l31fB17RwFz6UV RxnG0yPHqFIDxKo68s26zdHE5qT739TJnHjp3USsA9k72sV/g5mHtmmx4JvVhff1DYccYyN3OcoH VYK3cfh1fUegNe7qDmvpiWy9CriLB9ldYZn8s4iKtr4+ok11ISptgSBUhlRV8uogHXwhPI6QHLmu naJpn0TuzWJea86h7v0oRrAB/wNR4shrCOmXPpsdMtzJ8TmHbRpJYDX6iUPAYiMGgaGrE9ppvPci h895EDqHvEN6E3B6Ut X-QQ-XMRINFO: MPJ6Tf5t3I/ycC2BItcBVIA= From: uk7b@foxmail.com To: dev@dpdk.org Cc: sunyuechi , Thomas Monjalon , Bruce Richardson , Vladimir Medvedkin , Stanislaw Kardach Subject: [PATCH v2 2/3] lib/lpm: R-V V rte_lpm_lookupx4 Date: Wed, 4 Jun 2025 19:33:32 +0800 X-OQ-MSGID: <20250604113332.1876239-1-uk7b@foxmail.com> X-Mailer: git-send-email 2.49.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: sunyuechi Test results using lpm_perf_autotest on BPI-F3: scalar: 5.7 cycles rvv: 2.4 cycles The best way to call this RVV function is to follow the approach used in lib/fib, where all architectures initialize a function pointer in a unified way. However, other architectures in lib/lpm do not follow this pattern. Therefore, to avoid affecting other architectures, this commit does not modify lib/lpm/rte_lpm.c. Unifying the code style between lpm and fib may be worth considering in the future. Signed-off-by: sunyuechi --- MAINTAINERS | 2 + lib/lpm/meson.build | 1 + lib/lpm/rte_lpm.h | 2 + lib/lpm/rte_lpm_rvv.h | 91 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 96 insertions(+) create mode 100644 lib/lpm/rte_lpm_rvv.h diff --git a/MAINTAINERS b/MAINTAINERS index 3e16789250..0f207ac129 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -340,6 +340,8 @@ M: Stanislaw Kardach F: config/riscv/ F: doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst F: lib/eal/riscv/ +M: sunyuechi +F: lib/**/*rvv* Intel x86 M: Bruce Richardson diff --git a/lib/lpm/meson.build b/lib/lpm/meson.build index fae4f79fb9..09133061e5 100644 --- a/lib/lpm/meson.build +++ b/lib/lpm/meson.build @@ -17,6 +17,7 @@ indirect_headers += files( 'rte_lpm_scalar.h', 'rte_lpm_sse.h', 'rte_lpm_sve.h', + 'rte_lpm_rvv.h', ) deps += ['hash'] deps += ['rcu'] diff --git a/lib/lpm/rte_lpm.h b/lib/lpm/rte_lpm.h index 7df64f06b1..b06517206f 100644 --- a/lib/lpm/rte_lpm.h +++ b/lib/lpm/rte_lpm.h @@ -408,6 +408,8 @@ rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], #include "rte_lpm_altivec.h" #elif defined(RTE_ARCH_X86) #include "rte_lpm_sse.h" +#elif defined(RTE_ARCH_RISCV) && defined(RTE_RISCV_FEATURE_V) +#include "rte_lpm_rvv.h" #else #include "rte_lpm_scalar.h" #endif diff --git a/lib/lpm/rte_lpm_rvv.h b/lib/lpm/rte_lpm_rvv.h new file mode 100644 index 0000000000..e39ade3f07 --- /dev/null +++ b/lib/lpm/rte_lpm_rvv.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2025 Institute of Software Chinese Academy of Sciences (ISCAS). + */ + +#ifndef _RTE_LPM_RVV_H_ +#define _RTE_LPM_RVV_H_ + +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define RTE_LPM_LOOKUP_SUCCESS 0x01000000 +#define RTE_LPM_VALID_EXT_ENTRY_BITMASK 0x03000000 + +typedef void (*lpm_lookupx4_fn)(const struct rte_lpm *, xmm_t, uint32_t *, uint32_t); + +static lpm_lookupx4_fn lpm_lookupx4_impl; + +static inline void rte_lpm_lookupx4_scalar( + const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], uint32_t defv) +{ + uint32_t nh; + int ret; + + for (int i = 0; i < 4; i++) { + ret = rte_lpm_lookup(lpm, ip[i], &nh); + hop[i] = (ret == 0) ? nh : defv; + } +} + +static inline void rte_lpm_lookupx4_rvv( + const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], uint32_t defv) +{ + size_t vl = 4; + + const uint32_t *tbl24_p = (const uint32_t *)lpm->tbl24; + uint32_t tbl_entries[4] = { + tbl24_p[((uint32_t)ip[0]) >> 8], + tbl24_p[((uint32_t)ip[1]) >> 8], + tbl24_p[((uint32_t)ip[2]) >> 8], + tbl24_p[((uint32_t)ip[3]) >> 8], + }; + vuint32m1_t vtbl_entry = __riscv_vle32_v_u32m1(tbl_entries, vl); + + vbool32_t mask = __riscv_vmseq_vx_u32m1_b32( + __riscv_vand_vx_u32m1(vtbl_entry, RTE_LPM_VALID_EXT_ENTRY_BITMASK, vl), + RTE_LPM_VALID_EXT_ENTRY_BITMASK, vl); + + vuint32m1_t vtbl8_index = __riscv_vsll_vx_u32m1( + __riscv_vadd_vv_u32m1( + __riscv_vsll_vx_u32m1(__riscv_vand_vx_u32m1(vtbl_entry, 0x00FFFFFF, vl), 8, vl), + __riscv_vand_vx_u32m1( + __riscv_vle32_v_u32m1((const uint32_t *)&ip, vl), 0x000000FF, vl), + vl), + 2, vl); + + vtbl_entry = __riscv_vluxei32_v_u32m1_mu( + mask, vtbl_entry, (const uint32_t *)(lpm->tbl8), vtbl8_index, vl); + + vuint32m1_t vnext_hop = __riscv_vand_vx_u32m1(vtbl_entry, 0x00FFFFFF, vl); + mask = __riscv_vmseq_vx_u32m1_b32( + __riscv_vand_vx_u32m1(vtbl_entry, RTE_LPM_LOOKUP_SUCCESS, vl), 0, vl); + + vnext_hop = __riscv_vmerge_vxm_u32m1(vnext_hop, defv, mask, vl); + + __riscv_vse32_v_u32m1(hop, vnext_hop, vl); +} + +static inline void rte_lpm_lookupx4( + const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], uint32_t defv) +{ + lpm_lookupx4_impl(lpm, ip, hop, defv); +} + +RTE_INIT(rte_lpm_init_alg) +{ + lpm_lookupx4_impl = rte_cpu_get_flag_enabled(RTE_CPUFLAG_RISCV_ISA_V) + ? rte_lpm_lookupx4_rvv + : rte_lpm_lookupx4_scalar; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_LPM_RVV_H_ */ -- 2.49.0