[-- Attachment #1: Type: text/plain, Size: 302 bytes --] > -----Original Message----- > From: Sun, QinX <qinx.sun@intel.com> > Sent: Friday, December 17, 2021 7:08 PM > To: dts@dpdk.org > Cc: Fu, Qi <qi.fu@intel.com>; Sun, QinX <qinx.sun@intel.com> > Subject: [dts] [PATCH V1] tests/cvl_pps: add 4 new cases Tested-by: Qin Sun <qinx.sun@intel.com> [-- Attachment #2: TestCVLPPS.log --] [-- Type: application/octet-stream, Size: 12461 bytes --] 17/12/2021 10:48:06 dts: TEST SUITE : TestCVLPPS 17/12/2021 10:48:06 dts: NIC : columbiaville_100g 17/12/2021 10:48:06 dut.10.240.183.156: 17/12/2021 10:48:06 tester: 17/12/2021 10:48:06 TestCVLPPS: Test Case test_check_register_with_pin_id_0 Begin 17/12/2021 10:48:06 dut.10.240.183.156: 17/12/2021 10:48:06 tester: 17/12/2021 10:48:06 dut.10.240.183.156: x86_64-native-linuxapp-gcc/app/dpdk-testpmd -l 1,2 --file-prefix=dpdk_13533_20211217104742 -a 0000:18:00.0,pps_out='[pin:0]' -- -i --rxq=4 --txq=4 17/12/2021 10:48:07 dut.10.240.183.156: EAL: Detected CPU lcores: 56 EAL: Detected NUMA nodes: 2 EAL: Detected static linkage of DPDK EAL: Multi-process socket /var/run/dpdk/dpdk_13533_20211217104742/mp_socket EAL: Selected IOVA mode 'VA' EAL: 1024 hugepages of size 2097152 reserved, but no mounted hugetlbfs found for that size EAL: VFIO support initialized EAL: Using IOMMU type 1 (Type 1) EAL: Probe PCI driver: net_ice (8086:1592) device: 0000:18:00.0 (socket 0) ice_load_pkg_type(): Active package is: 1.3.27.0, ICE OS Default Package (double VLAN mode) Interactive-mode selected testpmd: create a new mbuf pool <mb_pool_0>: n=155456, size=2176, socket=0 testpmd: preferred mempool ops selected: ring_mp_mc Warning! port-topology=paired and odd forward ports number, the last port will pair with itself. Configuring Port 0 (socket 0) ice_set_rx_function(): Using AVX2 OFFLOAD Vector Rx (port 0). Port 0: 40:A6:B7:7B:3F:04 Checking link statuses... Done 17/12/2021 10:48:07 dut.10.240.183.156: read reg 0 0x00088998 17/12/2021 10:48:08 dut.10.240.183.156: port 0 PCI register at offset 0x88998: 0x00000007 (7) 17/12/2021 10:48:08 TestCVLPPS: check register pass 17/12/2021 10:48:08 dut.10.240.183.156: read reg 0 0x000889B8 17/12/2021 10:48:08 dut.10.240.183.156: port 0 PCI register at offset 0x889B8: 0x1DCD6500 (500000000) 17/12/2021 10:48:08 TestCVLPPS: check register pass 17/12/2021 10:48:08 dut.10.240.183.156: read reg 0 0x00088928 17/12/2021 10:48:08 dut.10.240.183.156: port 0 PCI register at offset 0x88928: 0xDAED35FF (3672978943) 17/12/2021 10:48:08 TestCVLPPS: check register pass 17/12/2021 10:48:08 dut.10.240.183.156: read reg 0 0x00088930 17/12/2021 10:48:08 dut.10.240.183.156: port 0 PCI register at offset 0x88930: 0x16C1696A (381774186) 17/12/2021 10:48:08 TestCVLPPS: check register pass 17/12/2021 10:48:08 dut.10.240.183.156: read reg 0 0x000880C8 17/12/2021 10:48:08 dut.10.240.183.156: port 0 PCI register at offset 0x880C8: 0x00000812 (2066) 17/12/2021 10:48:08 TestCVLPPS: check register pass 17/12/2021 10:48:08 TestCVLPPS: Test Case test_check_register_with_pin_id_0 Result PASSED: 17/12/2021 10:48:08 dut.10.240.183.156: kill_all: called by dut and prefix list has value. 17/12/2021 10:48:10 dut.10.240.183.156: Port 0: link state change event Killed [PEXPECT]# 17/12/2021 10:48:10 TestCVLPPS: Test Case test_check_register_with_pin_id_1 Begin 17/12/2021 10:48:10 dut.10.240.183.156: 17/12/2021 10:48:11 tester: 17/12/2021 10:48:11 dut.10.240.183.156: x86_64-native-linuxapp-gcc/app/dpdk-testpmd -l 1,2 --file-prefix=dpdk_13533_20211217104742 -a 0000:18:00.0,pps_out='[pin:1]' -- -i --rxq=4 --txq=4 17/12/2021 10:48:11 dut.10.240.183.156: EAL: Detected CPU lcores: 56 EAL: Detected NUMA nodes: 2 EAL: Detected static linkage of DPDK EAL: Multi-process socket /var/run/dpdk/dpdk_13533_20211217104742/mp_socket EAL: Selected IOVA mode 'VA' EAL: 1024 hugepages of size 2097152 reserved, but no mounted hugetlbfs found for that size EAL: VFIO support initialized EAL: Using IOMMU type 1 (Type 1) EAL: Probe PCI driver: net_ice (8086:1592) device: 0000:18:00.0 (socket 0) ice_load_pkg_type(): Active package is: 1.3.27.0, ICE OS Default Package (single VLAN mode) Interactive-mode selected testpmd: create a new mbuf pool <mb_pool_0>: n=155456, size=2176, socket=0 testpmd: preferred mempool ops selected: ring_mp_mc Warning! port-topology=paired and odd forward ports number, the last port will pair with itself. Configuring Port 0 (socket 0) ice_set_rx_function(): Using AVX2 OFFLOAD Vector Rx (port 0). Port 0: 40:A6:B7:7B:3F:04 Checking link statuses... Done 17/12/2021 10:48:11 dut.10.240.183.156: read reg 0 0x000889A0 17/12/2021 10:48:12 dut.10.240.183.156: port 0 PCI register at offset 0x889A0: 0x00000007 (7) 17/12/2021 10:48:12 TestCVLPPS: check register pass 17/12/2021 10:48:12 dut.10.240.183.156: read reg 0 0x000889C0 17/12/2021 10:48:12 dut.10.240.183.156: port 0 PCI register at offset 0x889C0: 0x1DCD6500 (500000000) 17/12/2021 10:48:12 TestCVLPPS: check register pass 17/12/2021 10:48:12 dut.10.240.183.156: read reg 0 0x00088938 17/12/2021 10:48:12 dut.10.240.183.156: port 0 PCI register at offset 0x88938: 0xC9585DFF (3378011647) 17/12/2021 10:48:12 TestCVLPPS: check register pass 17/12/2021 10:48:12 dut.10.240.183.156: read reg 0 0x00088940 17/12/2021 10:48:12 dut.10.240.183.156: port 0 PCI register at offset 0x88940: 0x16C1696B (381774187) 17/12/2021 10:48:12 TestCVLPPS: check register pass 17/12/2021 10:48:12 dut.10.240.183.156: read reg 0 0x000880CC 17/12/2021 10:48:12 dut.10.240.183.156: port 0 PCI register at offset 0x880CC: 0x00000912 (2322) 17/12/2021 10:48:12 TestCVLPPS: check register pass 17/12/2021 10:48:12 TestCVLPPS: Test Case test_check_register_with_pin_id_1 Result PASSED: 17/12/2021 10:48:12 dut.10.240.183.156: kill_all: called by dut and prefix list has value. 17/12/2021 10:48:14 dut.10.240.183.156: Port 0: link state change event Killed [PEXPECT]# 17/12/2021 10:48:14 TestCVLPPS: Test Case test_check_register_with_pin_id_2 Begin 17/12/2021 10:48:14 dut.10.240.183.156: 17/12/2021 10:48:15 tester: 17/12/2021 10:48:15 dut.10.240.183.156: x86_64-native-linuxapp-gcc/app/dpdk-testpmd -l 1,2 --file-prefix=dpdk_13533_20211217104742 -a 0000:18:00.0,pps_out='[pin:2]' -- -i --rxq=4 --txq=4 17/12/2021 10:48:15 dut.10.240.183.156: EAL: Detected CPU lcores: 56 EAL: Detected NUMA nodes: 2 EAL: Detected static linkage of DPDK EAL: Multi-process socket /var/run/dpdk/dpdk_13533_20211217104742/mp_socket EAL: Selected IOVA mode 'VA' EAL: 1024 hugepages of size 2097152 reserved, but no mounted hugetlbfs found for that size EAL: VFIO support initialized EAL: Using IOMMU type 1 (Type 1) EAL: Probe PCI driver: net_ice (8086:1592) device: 0000:18:00.0 (socket 0) ice_load_pkg_type(): Active package is: 1.3.27.0, ICE OS Default Package (single VLAN mode) Interactive-mode selected testpmd: create a new mbuf pool <mb_pool_0>: n=155456, size=2176, socket=0 testpmd: preferred mempool ops selected: ring_mp_mc Warning! port-topology=paired and odd forward ports number, the last port will pair with itself. Configuring Port 0 (socket 0) ice_set_rx_function(): Using AVX2 OFFLOAD Vector Rx (port 0). Port 0: 40:A6:B7:7B:3F:04 Checking link statuses... Done 17/12/2021 10:48:15 dut.10.240.183.156: read reg 0 0x000889A8 17/12/2021 10:48:16 dut.10.240.183.156: port 0 PCI register at offset 0x889A8: 0x00000007 (7) 17/12/2021 10:48:16 TestCVLPPS: check register pass 17/12/2021 10:48:16 dut.10.240.183.156: read reg 0 0x000889C8 17/12/2021 10:48:16 dut.10.240.183.156: port 0 PCI register at offset 0x889C8: 0x1DCD6500 (500000000) 17/12/2021 10:48:16 TestCVLPPS: check register pass 17/12/2021 10:48:16 dut.10.240.183.156: read reg 0 0x00088948 17/12/2021 10:48:16 dut.10.240.183.156: port 0 PCI register at offset 0x88948: 0xB7C385FF (3083044351) 17/12/2021 10:48:16 TestCVLPPS: check register pass 17/12/2021 10:48:16 dut.10.240.183.156: read reg 0 0x00088950 17/12/2021 10:48:16 dut.10.240.183.156: port 0 PCI register at offset 0x88950: 0x16C1696C (381774188) 17/12/2021 10:48:16 TestCVLPPS: check register pass 17/12/2021 10:48:16 dut.10.240.183.156: read reg 0 0x000880D0 17/12/2021 10:48:16 dut.10.240.183.156: port 0 PCI register at offset 0x880D0: 0x00000A12 (2578) 17/12/2021 10:48:16 TestCVLPPS: check register pass 17/12/2021 10:48:16 TestCVLPPS: Test Case test_check_register_with_pin_id_2 Result PASSED: 17/12/2021 10:48:16 dut.10.240.183.156: kill_all: called by dut and prefix list has value. 17/12/2021 10:48:18 dut.10.240.183.156: Port 0: link state change event Killed [PEXPECT]# 17/12/2021 10:48:18 TestCVLPPS: Test Case test_check_register_with_pin_id_3 Begin 17/12/2021 10:48:18 dut.10.240.183.156: 17/12/2021 10:48:19 tester: 17/12/2021 10:48:19 dut.10.240.183.156: x86_64-native-linuxapp-gcc/app/dpdk-testpmd -l 1,2 --file-prefix=dpdk_13533_20211217104742 -a 0000:18:00.0,pps_out='[pin:3]' -- -i --rxq=4 --txq=4 17/12/2021 10:48:19 dut.10.240.183.156: EAL: Detected CPU lcores: 56 EAL: Detected NUMA nodes: 2 EAL: Detected static linkage of DPDK EAL: Multi-process socket /var/run/dpdk/dpdk_13533_20211217104742/mp_socket EAL: Selected IOVA mode 'VA' EAL: 1024 hugepages of size 2097152 reserved, but no mounted hugetlbfs found for that size EAL: VFIO support initialized EAL: Using IOMMU type 1 (Type 1) EAL: Probe PCI driver: net_ice (8086:1592) device: 0000:18:00.0 (socket 0) ice_load_pkg_type(): Active package is: 1.3.27.0, ICE OS Default Package (single VLAN mode) Interactive-mode selected testpmd: create a new mbuf pool <mb_pool_0>: n=155456, size=2176, socket=0 testpmd: preferred mempool ops selected: ring_mp_mc Warning! port-topology=paired and odd forward ports number, the last port will pair with itself. Configuring Port 0 (socket 0) ice_set_rx_function(): Using AVX2 OFFLOAD Vector Rx (port 0). Port 0: 40:A6:B7:7B:3F:04 Checking link statuses... Done 17/12/2021 10:48:19 dut.10.240.183.156: read reg 0 0x000889B0 17/12/2021 10:48:20 dut.10.240.183.156: port 0 PCI register at offset 0x889B0: 0x00000007 (7) 17/12/2021 10:48:20 TestCVLPPS: check register pass 17/12/2021 10:48:20 dut.10.240.183.156: read reg 0 0x000889D0 17/12/2021 10:48:20 dut.10.240.183.156: port 0 PCI register at offset 0x889D0: 0x1DCD6500 (500000000) 17/12/2021 10:48:20 TestCVLPPS: check register pass 17/12/2021 10:48:20 dut.10.240.183.156: read reg 0 0x00088958 17/12/2021 10:48:20 dut.10.240.183.156: port 0 PCI register at offset 0x88958: 0xA62EADFF (2788077055) 17/12/2021 10:48:20 TestCVLPPS: check register pass 17/12/2021 10:48:20 dut.10.240.183.156: read reg 0 0x00088960 17/12/2021 10:48:20 dut.10.240.183.156: port 0 PCI register at offset 0x88960: 0x16C1696D (381774189) 17/12/2021 10:48:20 TestCVLPPS: check register pass 17/12/2021 10:48:20 dut.10.240.183.156: read reg 0 0x000880D4 17/12/2021 10:48:20 dut.10.240.183.156: port 0 PCI register at offset 0x880D4: 0x00000B12 (2834) 17/12/2021 10:48:20 TestCVLPPS: check register pass 17/12/2021 10:48:20 TestCVLPPS: Test Case test_check_register_with_pin_id_3 Result PASSED: 17/12/2021 10:48:20 dut.10.240.183.156: kill_all: called by dut and prefix list has value. 17/12/2021 10:48:22 dut.10.240.183.156: Port 0: link state change event Killed [PEXPECT]# 17/12/2021 10:48:22 dts: TEST SUITE ENDED: TestCVLPPS
add 4 new cases for pps according to test plan Signed-off-by: Qin Sun <qinx.sun@intel.com> --- tests/TestSuite_cvl_pps.py | 126 +++++++++++++++++++++++++++++++++++++ 1 file changed, 126 insertions(+) create mode 100755 tests/TestSuite_cvl_pps.py diff --git a/tests/TestSuite_cvl_pps.py b/tests/TestSuite_cvl_pps.py new file mode 100755 index 00000000..960e6f6e --- /dev/null +++ b/tests/TestSuite_cvl_pps.py @@ -0,0 +1,126 @@ +# BSD LICENSE +# +# Copyright(c) 2010-2021 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +import re +from framework.pmd_output import PmdOutput +from framework.test_case import TestCase + + +class TestCVLPPS(TestCase): + + def set_up_all(self): + """ + Run at the start of each test suite. + prerequisites. + """ + # Based on h/w type, chose how many ports to use + dut_ports = self.dut.get_ports(self.nic) + self.verify(len(dut_ports) >= 1, "Insufficient ports for testing") + # Verify that enough threads are available + self.cores = self.dut.get_core_list("1S/2C/1T") + self.verify(self.cores, "Insufficient cores for speed testing") + self.pci = self.dut.ports_info[dut_ports[0]]['pci'] + self.pmd_output = PmdOutput(self.dut) + self.GLTSYN_AUX = re.compile(r'0x00000007\s+\(7\)') + self.GLTSYN_CLKO = re.compile(r'0x1DCD6500\s+\(500000000\)') + self.pattern = re.compile('register\s+at\s+offset\s+.*:\s+(?P<hex>0x\w+)\s+\(\d+\)') + + def set_up(self): + """ + Run before each test case. + """ + pass + + def read_register(self, addr, port_id=0): + cmd = 'read reg {} {}'.format(port_id, addr) + return self.pmd_output.execute_cmd(cmd) + + def launch_testpmd(self, pin_id, rxq=4, txq=4): + self.out = self.pmd_output.start_testpmd(cores="1S/2C/1T", param="--rxq={} --txq={} ".format(rxq, txq), + eal_param="-a {},pps_out='[pin:{}]'".format(self.pci, pin_id)) + + def check_register(self, pin_id, addrs, port_id=0): + self.launch_testpmd(pin_id) + for i in range(len(addrs)): + out = self.read_register(addrs[i], port_id=port_id) + if i == 0: + pattern = self.GLTSYN_AUX + elif i == 1: + pattern = self.GLTSYN_CLKO + else: + pattern = self.pattern + res = pattern.search(out) + self.verify(res, 'pattern:{} not found in output info: {}'.format(pattern, out)) + if i == 4: + return res + if i > 1: + actual_value = int(res.group('hex'), 16) + self.verify(actual_value != 0, + 'check register failed, expected value is non-zero, actual value is:{}'.format(actual_value)) + self.logger.info('check register pass') + + def check_value(self, hex_value, target_value): + self.verify(hex_value[7] == target_value, + 'check register failed, target value is {} not match expected value {}'.format(hex_value[7], target_value)) + bit_4th = bin(int(hex_value, 16))[2:][-5] + self.verify(bit_4th == '1', 'check register failed, the 4th bit is {} not match expected value {}'.format(bit_4th, 1)) + self.logger.info('check register pass') + + def test_check_register_with_pin_id_0(self): + addrs = ['0x00088998', '0x000889B8', '0x00088928', '0x00088930', '0x000880C8'] + res = self.check_register(pin_id=0, addrs=addrs) + # check GLGEN_GPIO_CTL[0][2] 0x000880C8 is 8, the 4th bit is 1 + self.check_value(hex_value=res.group('hex'), target_value='8') + + def test_check_register_with_pin_id_1(self): + addrs = ['0x000889A0', '0x000889C0', '0x00088938', '0x00088940', '0x000880CC'] + res = self.check_register(pin_id=1, addrs=addrs) + # check GLGEN_GPIO_CTL[1][2] 0x000880CC is 9, the 4th bit is 1 + self.check_value(hex_value=res.group('hex'), target_value='9') + + def test_check_register_with_pin_id_2(self): + addrs = ['0x000889A8', '0x000889C8', '0x00088948', '0x00088950', '0x000880D0'] + res = self.check_register(pin_id=2, addrs=addrs) + # check GLGEN_GPIO_CTL[2][2] 0x000880CC is A, the 4th bit is 1 + self.check_value(hex_value=res.group('hex'), target_value='A') + + def test_check_register_with_pin_id_3(self): + addrs = ['0x000889B0', '0x000889D0', '0x00088958', '0x00088960', '0x000880D4'] + res = self.check_register(pin_id=3, addrs=addrs) + # check GLGEN_GPIO_CTL[3][2] 0x000880CC is B, the 4th bit is 1 + self.check_value(hex_value=res.group('hex'), target_value='B') + + def tear_down(self): + self.dut.kill_all() + + def tear_down_all(self): + self.dut.kill_all() -- 2.17.1
> -----Original Message----- > From: Qin Sun <qinx.sun@intel.com> > Sent: 2021年12月17日 19:08 > To: dts@dpdk.org > Cc: Fu, Qi <qi.fu@intel.com>; Sun, QinX <qinx.sun@intel.com> > Subject: [dts] [PATCH V1] tests/cvl_pps: add 4 new cases > > add 4 new cases for pps according to test plan > > Signed-off-by: Qin Sun <qinx.sun@intel.com> Could you add some description for your core functions: check_register and check_value. All registers are hard code, so how to compatible to following : when test the onboard NIC of HCC/SNR platform, the timer = 1, so all the register need to add 4 except GLGEN_GPIO_CTL. > +# Copyright(c) 2010-2021 Intel Corporation. All rights reserved. It's the year of 2022, and we don't have copyright of PAST. > + self.verify(actual_value != 0, > + 'check register failed, expected value is non-zero, actual value is:{}'.format(actual_value)) The verify failure message is valueless, definitely the actual value is zero, because it is checkout non-zero. > + self.logger.info('check register pass') Also, it is valueless, if target to get stage info, better to use something like: Check register <address>: pass > + def tear_down(self): > + self.dut.kill_all() Please use "quit()" in testpmd at first, kill_all should be used as a last resort.