From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id E6C8B9A92 for ; Tue, 26 May 2015 09:36:25 +0200 (CEST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP; 26 May 2015 00:36:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.13,496,1427785200"; d="scan'208";a="715562420" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by fmsmga001.fm.intel.com with ESMTP; 26 May 2015 00:36:25 -0700 Received: from shecgisg003.sh.intel.com (shecgisg003.sh.intel.com [10.239.29.90]) by shvmail01.sh.intel.com with ESMTP id t4Q7aMtj027982; Tue, 26 May 2015 15:36:22 +0800 Received: from shecgisg003.sh.intel.com (localhost [127.0.0.1]) by shecgisg003.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id t4Q7aKTp019486; Tue, 26 May 2015 15:36:22 +0800 Received: (from jingguox@localhost) by shecgisg003.sh.intel.com (8.13.6/8.13.6/Submit) id t4Q7aKOA019482; Tue, 26 May 2015 15:36:20 +0800 From: TangHaifeng To: dts@dpdk.org Date: Tue, 26 May 2015 15:35:41 +0800 Message-Id: <1432625755-19403-8-git-send-email-haifengx.tang@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1432625755-19403-1-git-send-email-haifengx.tang@intel.com> References: <1432625755-19403-1-git-send-email-haifengx.tang@intel.com> Cc: jingguox.fu@intel.com Subject: [dts] [dts 14/28] add unit_test_timer rst file into dts X-BeenThere: dts@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: test suite reviews and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 May 2015 07:36:26 -0000 --- test_plans/unit_tests_timer_test_plan.rst | 98 +++++++++++++++++++++++++++++ 1 files changed, 98 insertions(+), 0 deletions(-) create mode 100644 test_plans/unit_tests_timer_test_plan.rst diff --git a/test_plans/unit_tests_timer_test_plan.rst b/test_plans/unit_tests_timer_test_plan.rst new file mode 100644 index 0000000..5bf96c5 --- /dev/null +++ b/test_plans/unit_tests_timer_test_plan.rst @@ -0,0 +1,98 @@ +.. Copyright (c) <2010>, Intel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + - Neither the name of Intel Corporation nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + OF THE POSSIBILITY OF SUCH DAMAGE. + +=============== +Timer Autotests +=============== + +This section describes the test plan for the timer library. + +Description +=========== + +#. Stress tests. + + The objective of the timer stress tests is to check that there are no + race conditions in list and status management. This test launches, + resets and stops the timer very often on many cores at the same + time. + + - Only one timer is used for this test. + - On each core, the rte_timer_manage() function is called from the main loop + every 3 microseconds. + - In the main loop, the timer may be reset (randomly, with a + probability of 0.5 %) 100 microseconds later on a random core, or + stopped (with a probability of 0.5 % also). + - In callback, the timer is can be reset (randomly, with a + probability of 0.5 %) 100 microseconds later on the same core or + on another core (same probability), or stopped (same + probability). + +#. Basic test. + + This test performs basic functional checks of the timers. The test + uses four different timers that are loaded and stopped under + specific conditions in specific contexts. + + - Four timers are used for this test. + - On each core, the rte_timer_manage() function is called from main loop + every 3 microseconds. + + The autotest python script checks that the behavior is correct: + + - timer0 + + - At initialization, timer0 is loaded by the master core, on master core in + "single" mode (time = 1 second). + - In the first 19 callbacks, timer0 is reloaded on the same core, + then, it is explicitly stopped at the 20th call. + - At t=25s, timer0 is reloaded once by timer2. + + - timer1 + + - At initialization, timer1 is loaded by the master core, on the + master core in "single" mode (time = 2 seconds). + - In the first 9 callbacks, timer1 is reloaded on another + core. After the 10th callback, timer1 is not reloaded anymore. + + - timer2 + + - At initialization, timer2 is loaded by the master core, on the + master core in "periodical" mode (time = 1 second). + - In the callback, when t=25s, it stops timer3 and reloads timer0 + on the current core. + + - timer3 + + - At initialization, timer3 is loaded by the master core, on + another core in "periodical" mode (time = 1 second). + - It is stopped at t=25s by timer2. -- 1.7.4.4