From: Yong Liu <yong.liu@intel.com>
To: dts@dpdk.org
Subject: [dts] [PATCH 1/4] Optimize get core list function for Haswell cpu.
Date: Mon, 8 Jun 2015 10:21:25 +0800 [thread overview]
Message-ID: <1433730088-5601-2-git-send-email-yong.liu@intel.com> (raw)
In-Reply-To: <1433730088-5601-1-git-send-email-yong.liu@intel.com>
From: Marvin Liu <yong.liu@intel.com>
Create cpu id map for core allocation. Haswell cpu default core id is
[0, 1, 2, 3, 4, 8, 9, 10, 11, 16, 17, 18, 19, 20, 24, 25, 26, 27].
After conversion, cpu core id will be
[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17].
Change set object to list object in get_core_list for get core in sequence.
Signed-off-by: Marvin Liu <yong.liu@intel.com>
diff --git a/framework/crb.py b/framework/crb.py
index 2c01d48..f6ac811 100644
--- a/framework/crb.py
+++ b/framework/crb.py
@@ -423,6 +423,10 @@ class Crb(object):
"grep --color=never \"processor\\|physical id\\|core id\\|^$\" /proc/cpuinfo",
"#", alt_session=True)
cpuinfo = cpuinfo.split('\r\n\r\n')
+ # haswell cpu on cottonwood core id not correct
+ # need addtional coremap for haswell cpu
+ core_id = 0
+ coremap = {}
for line in cpuinfo:
m = re.search("processor\t: (\d+)\r\n" +
"physical id\t: (\d+)\r\n" +
@@ -432,11 +436,16 @@ class Crb(object):
thread = m.group(1)
socket = m.group(2)
core = m.group(3)
+
+ if core not in coremap.keys():
+ coremap[core] = core_id
+ core_id += 1
+
if self.crb['bypass core0'] and core == '0' and socket == '0':
self.logger.info("Core0 bypassed")
continue
self.cores.append(
- {'thread': thread, 'socket': socket, 'core': core})
+ {'thread': thread, 'socket': socket, 'core': coremap[core]})
self.number_of_cores = len(self.cores)
@@ -559,9 +568,9 @@ class Crb(object):
temp = []
for sock in sockList:
- core_list = set([int(n['core']) for n in partial_cores if int(
+ core_list = list([int(n['core']) for n in partial_cores if int(
n['socket']) == sock])
- core_list = list(core_list)[:nr_cores]
+ core_list = core_list[:nr_cores]
temp.extend(core_list)
core_list = temp
@@ -579,9 +588,9 @@ class Crb(object):
coreList_aux = [int(core_list[n])for n in range(
(nr_cores * i), (nr_cores * i + nr_cores))]
for core in coreList_aux:
- thread_list = set([int(n['thread']) for n in partial_cores if (
+ thread_list = list([int(n['thread']) for n in partial_cores if (
(int(n['core']) == core) and (int(n['socket']) == sock))])
- thread_list = list(thread_list)[:nr_threads]
+ thread_list = thread_list[:nr_threads]
temp.extend(thread_list)
thread_list = temp
i += 1
--
1.9.3
next prev parent reply other threads:[~2015-06-08 2:21 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-08 2:21 [dts] [PATCH 0/4] Add vxlan function and performance suite Yong Liu
2015-06-08 2:21 ` Yong Liu [this message]
2015-06-08 2:21 ` [dts] [PATCH 2/4] Add vxlan protocal support in etgen module Yong Liu
2015-06-08 2:21 ` [dts] [PATCH 3/4] Add vxlan test plan Yong Liu
2015-06-08 2:21 ` [dts] [PATCH 4/4] Add vxlan test suite Yong Liu
2015-06-09 6:38 ` [dts] [PATCH] Enhance vxlan checksum offload performance test case Yong Liu
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