From: Yong Liu <yong.liu@intel.com>
To: dts@dpdk.org
Subject: [dts] [PATCH] fix bug that read_cache option not work
Date: Thu, 9 Jul 2015 17:07:39 +0800 [thread overview]
Message-ID: <1436432859-1768-1-git-send-email-yong.liu@intel.com> (raw)
From: Marvin Liu <yong.liu@intel.com>
Cache file only can save string object, so skip save port net device object.
In prerequisties function, we will instantiate net device and save it into
ports_info structure.
Cache file now saved in output folder.
Signed-off-by: Marvin Liu <yong.liu@intel.com>
diff --git a/framework/dts.py b/framework/dts.py
index 2e67e40..6d8b950 100644
--- a/framework/dts.py
+++ b/framework/dts.py
@@ -235,7 +235,8 @@ def dts_crbs_init(crbInst, skip_setup, read_cache, project, base_dir, nic, virtt
"""
global dut
global tester
- serializer.set_serialized_filename('.%s.cache' % crbInst['IP'])
+ serializer.set_serialized_filename(FOLDERS['Output'] +
+ '/.%s.cache' % crbInst['IP'])
serializer.load_from_file()
dut = get_project_obj(project, Dut, crbInst, serializer)
diff --git a/framework/dut.py b/framework/dut.py
index 8c83075..0f523c0 100644
--- a/framework/dut.py
+++ b/framework/dut.py
@@ -44,8 +44,6 @@ from virt_resource import VirtResource
from utils import RED
-
-
class Dut(Crb):
"""
@@ -275,7 +273,6 @@ class Dut(Crb):
if total_huge_pages != arch_huge_pages:
self.set_huge_pages(arch_huge_pages)
-
self.mount_huge_pages()
self.hugepage_path = self.strip_hugepage_path()
@@ -541,19 +538,20 @@ class Dut(Crb):
port_info['ipv6'] = ipv6
def load_serializer_ports(self):
- self.ports_info = []
cached_ports_info = self.serializer.load(self.PORT_INFO_CACHE_KEY)
if cached_ports_info is None:
return
- for port in cached_ports_info:
- self.ports_info.append({'pci': port['pci'], 'type': port['type'],
- 'numa': port['numa']})
+
+ self.ports_info = cached_ports_info
def save_serializer_ports(self):
cached_ports_info = []
for port in self.ports_info:
- cached_ports_info.append({'pci': port['pci'], 'type': port['type'],
- 'numa': port['numa']})
+ port_info = {}
+ for key in port.keys():
+ if type(port[key]) is str:
+ port_info[key] = port[key]
+ cached_ports_info.append(port_info)
self.serializer.save(self.PORT_INFO_CACHE_KEY, cached_ports_info)
def scan_ports(self):
@@ -562,11 +560,35 @@ class Dut(Crb):
"""
if self.read_cache:
self.load_serializer_ports()
+ self.scan_ports_cached()
if not self.read_cache or self.ports_info is None:
self.scan_ports_uncached()
self.save_serializer_ports()
+ def scan_ports_cached(self):
+ """
+ Scan cached ports, instantiate tester port
+ """
+ scan_ports_cached = getattr(self, 'scan_ports_cached_%s' % self.get_os_type())
+ return scan_ports_cached()
+
+ def scan_ports_cached_linux(self):
+ """
+ Scan Linux ports and instantiate tester port
+ """
+ if self.ports_info is None:
+ return
+
+ for port_info in self.ports_info:
+ port = NetDevice(self, port_info['pci'], port_info['type'])
+ intf = port.get_interface_name()
+
+ self.logger.info("DUT cached: [000:%s %s] %s" % (port_info['pci'],
+ port_info['type'], intf))
+
+ port_info['port'] = port
+
def scan_ports_uncached(self):
"""
Scan ports and collect port's pci id, mac adress, ipv6 address.
@@ -700,7 +722,6 @@ class Dut(Crb):
def get_vm_core_list(self):
return VMCORELIST[self.crb['VM CoreList']]
-
def load_portconf(self):
"""
Load port configurations for ports_info. If manually configured infor
diff --git a/framework/tester.py b/framework/tester.py
index ce136e4..35581c8 100644
--- a/framework/tester.py
+++ b/framework/tester.py
@@ -65,7 +65,8 @@ class Tester(Crb):
self.NAME, self.get_password())
self.session.init_log(self.logger)
self.alt_session = SSHConnection(self.get_ip_address(),
- self.NAME + '_alt', self.get_password())
+ self.NAME + '_alt',
+ self.get_password())
self.alt_session.init_log(self.logger)
self.bgProcIsRunning = False
@@ -199,6 +200,9 @@ class Tester(Crb):
"""
Restore Linux interfaces.
"""
+ if self.skip_setup:
+ return
+
self.send_expect("modprobe igb", "# ", 20)
self.send_expect("modprobe ixgbe", "# ", 20)
self.send_expect("modprobe e1000e", "# ", 20)
@@ -218,7 +222,6 @@ class Tester(Crb):
sleep(2)
def load_serializer_ports(self):
- self.ports_info = []
cached_ports_info = self.serializer.load(self.PORT_INFO_CACHE_KEY)
if cached_ports_info is None:
return
@@ -243,6 +246,7 @@ class Tester(Crb):
"""
if self.read_cache:
self.load_serializer_ports()
+ self.scan_ports_cached()
if not self.read_cache or self.ports_info is None:
self.scan_ports_uncached()
@@ -253,6 +257,21 @@ class Tester(Crb):
for port_info in self.ports_info:
self.logger.info(port_info)
+ def scan_ports_cached(self):
+ if self.ports_info is None:
+ return
+
+ for port_info in self.ports_info:
+ if port_info['type'] == 'ixia':
+ continue
+
+ port = NetDevice(self, port_info['pci'], port_info['type'])
+ intf = port.get_interface_name()
+
+ self.logger.info("Tester cached: [000:%s %s] %s" % (
+ port_info['pci'], port_info['type'], intf))
+ port_info['port'] = port
+
def scan_ports_uncached(self):
"""
Return tester port pci/mac/interface information.
--
1.9.3
reply other threads:[~2015-07-09 9:07 UTC|newest]
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